NM93CS06 CS46 CS56 CS Bit Serial EEPROM with Data Protect and Sequential Read

Transcription

1 August 1996 NM93CS06 CS46 CS56 CS66 (MICROWIRE TM Bus Interface) Bit Serial EEPROM with Data Protect and Sequential Read General Description The NM93CS06 CS46 CS56 CS66 devices are bits respectively of CMOS non-volatile electrically erasable memory divided into bit registers Selected registers can be protected agait data modification by programming the Protect Register with the address of the first register to be protected agait data modification (all registers greater than or equal to the selected address are then protected from further change) Additionally this address can be locked into the device making all future attempts to change data impossible These devices are fabricated using National Semiconductor floating-gate CMOS process for high reliability high endurance and low power coumption The NM93CSXX Family is offered in both SO and TSSOP packages for small space coideratio The EEPROM interfacing is MICROWIRE compatible providing simple interfacing to standard microcontrollers and microprocessors There are a total of 10 itructio 5 which operate on the EEPROM memory and 5 which operate on the Protect Register The memory itructio are Block Diagram READ WRITE WRITE ALL WRITE ENABLE and WRITE DISABLE The Protect register itructio are PRREAD PRWRITE PRENABLE PRCLEAR and PRDISABLE Features Write protection in a user defined section of memory Sequential register read Typical active current of 200 ma and standby current of 10 ma No erase required before write Reliable CMOS floating gate technology MICROWIRE compatible serial I O Self timed write cycle Device status during programming mode 40 year data retention Endurance 10 6 data changes 4 5V to 5 5V operation in all modes of operation Packages available 8-pin SO 8-pin DIP 8-pin TSSOP NM93CS06 CS46 CS56 CS66 (MICROWIRE Bus Interface) Bit Serial EEPROM with Data Protect and Sequential Read TL D TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRETM is a trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL D RRD-B30M96 Printed in U S A http www national com

2 Connection Diagram Dual-In-Line Package (N) 8-Pin SO (M8) and 8-Pin TSSOP (MT8) Top View NS Package Number N08E M08A and MTC08 TL D CS SK DI DO GND PE PRE V CC Pin Names Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Protect Register Enable Power Supply Ordering Information Commercial Temp Range (0 Ctoa70 C) Order Number NM93CS06N NM93CS46N NM93CS56N NM93CS66N NM93CS06M8 NM93CS46M8 NM93CS56M8 NM93CS66M8 NM93CS46MT8 NM93CS56MT8 NM93CS66MT8 Extended Temp Range (b40 Ctoa85 C) Order Number NM93CS06EN NM93CS46EN NM93CS56EN NM93CS66EN NM93CS06EM8 NM93CS46EM8 NM93CS56EM8 NM93CS66EM8 NM93CS46EMT8 NM93CS56EMT8 NM93CS66EMT8 Automotive Temp Range (b40 Ctoa125 C) Order Number NM93CS06VN NM93CS46VN NM93CS56VN NM93CS66VN NM93CS06VM8 NM93CS46VM8 NM93CS56VM8 NM93CS66VM8 NM93CS46VMT8 NM93CS56VMT8 NM93CS66VMT8 http www national com 2

3 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Ambient Storage Temperature b65 Ctoa150 C All Input or Output Voltages a6 5V to b0 3V with Respect to Ground Lead Temperature (Soldering 10 sec ) a300 C ESD rating 2000V Operating Conditio Ambient Operating Temperature NM93CSxx NM93CSxxE NM93CSxxV Power Supply (V CC ) 0 Ctoa70 C b40 Ctoa85 C b40 Ctoa125 C 4 5V to 5 5V DC and AC Electrical Characteristics V CC e 4 5V to 5 5V unless otherwise specified Symbol Parameter Part Number Conditio Min Max Units I CCA Operating Current NM93CS06 NM93CS66 CS e V IH SKe1 0 MHz 1 ma NM93CS06E V NM93CS66E V SK e 1 0 MHz 1 I CCS Standby Current NM93CS06 NM93CS66 CS e V IL 50 NM93CS06E V NM93CS06E V 50 I IL Input Leakage V IN e 0V to V CC gb1 ma I OL Output Leakage (Note 3) V IL Input Low Voltage b V IH Input High Voltage 2 V CC a 1 V OL1 Output Low Voltage I OL e 2 1 ma 0 4 V OH1 Output High Voltage I OH eb400 ma 2 4 V OL2 Output Low Voltage I OL e 10 ma 0 2 V OH2 Output High Voltage I OH eb10 ma V CC b 0 2 f SK SK Clock Frequency NM93CS06 NM93CS66 (Note 4) 0 1 NM93CS06E V NM93CS66E V 0 1 t SKH SK High Time NM93CS06 NM93CS NM93CS06E V NM93CS66E V 300 t SKL SK Low Time 250 t SKS SK Setup Time SK Must Be at V IL 50 for t SKS before CS 50 goes high 100 t CS Minimum CS NM93CS06 NM93CS66 (Note 2) 250 Low Time NM93CS06E V NM93CS66E V 250 t CSS CS Setup Time 100 t PRES PRE Setup Time NM93CS06-NM93CS66 50 NM93CS06E V-NM93CS66E V 50 t DH DO Hold Time 70 t PES PE Setup Time NM93CS06 NM93CS66 50 NM93CS06E V NM93CS66E V 50 t DIS DI Setup Time NM93CS06 NM93CS NM93CS06E V NM93CS66E V 100 t CSH CS Hold Time 0 ma V V V MHz 3 http www national com

4 DC and AC Electrical Characteristics V CC e 4 5V to 5 5V unless otherwise specified (Continued) Symbol Parameter Part Number Conditio Min Max Units t PEH PE Hold Time NM93CS06 NM93CS NM93CS06E V NM93CS66E V 250 t PREH PRE Hold Time 50 t DIH DI Hold Time 20 t PD1 Output Delay to 1 NM93CS06 NM93CS NM93CS06E V NM93CS66E V 500 t PD0 Output Delay to 0 NM93CS06 NM93CS NM93CS06E V NM93CS66E V 500 t SV CS to Status Valid NM93CS06 NM93CS NM93CS06E V NM93CS66E V 500 t DF CS to DO in NM93CS06 NM93CS66 CS e V IL 100 TRI-STATE NM93CS06E V NM93CS66E V 100 t WP Write Cycle Time 10 ms Capacitance T A e 25 C f e 1 MHz Symbol Test Typ Max Units C OUT Output Capacitance 5 pf C IN Input Capacitance 5 pf Note 1 Stress ratings above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and operation of the device at these or any other conditio above those indicated in the operational sectio of the specification is not implied Exposure to absolute maximum rating conditio for extended periods may affect device reliability Note 2 CS (Chip Select) must be brought low (to V IL ) for an interval of t CS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle (this is shown in the opcode diagrams in the following pages) Note 3 Typical leakage values are in the 20 na range Note 4 The shortest allowable SK clock period e 1 f SK (as shown under the f SK parameter) Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet Within this SK period both t SKH and t SKL limits must be observed Therefore it is not allowable to set 1 f SK e t SKH (minimum) a t SKL (minimum) for shorter SK cycle time operation AC Test Conditio V CC Range V IL V IH V IL V IH V OL V OH I OL I OH Input Levels Timing Level Timing Level 4 5V s V CC s 5 5V 0 4V 2 4V 1 0V 2 0V 0 4V 2 4V (TTL Levels) Output Load 1 TTL Gate (C L e 100 pf) b2 1 ma 0 4 ma http www national com 4

5 Functional Description The NM93CSxx EEPROM Family has 10 itructio as described below All Data-In signals are clocked into the device on the low-to-high SK traition Read and Sequential Register Read (READ) The READ itruction outputs serial data on the D0 pin After a READ itruction is received the itruction and address are decoded followed by data trafer from the selected memory register into a 16-bit serial-out shift register A dummy bit (logical 0) precedes the 16-bit data output string Output data changes are initiated by a low to high traition of the SK clock In the sequential register read mode of operation the memory automatically cycles to the next register after each 16 data bits are clocked out The dummy-bit is suppressed in this mode and a continuous string of data is obtained Write Enable (WEN) When V CC is applied to the part it powers up in the Write Disable (WDS) state Therefore all programming modes must be preceded by a Write Enable (WEN) itruction Once a Write Enable itruction is executed programming remai enabled until a Write Disable (WDS) itruction is executed or V CC is completely removed from the part Write (WRITE) The WRITE itruction is followed by 16 bits of data to be written into the specified address After the last bit of data is put on the data-in (DI) pin CS must be brought low before the next rising edge of the SK clock This falling edge of the CS initiates the self-timed programming cycle The PE pin MUST be held high while loading the WRITE itruction however after loading the WRITE itruction the PE pin becomes a don t care The D0 pin indicates the READ BUS status of the chip if CS is brought high after the t CS interval D0 e logical 0 indicates that programming is still in progress D0 e logical 1 indicates that the register at the address specified in the itruction has been written with the data pattern specified in the itruction and the part is ready for another itruction Write All (WRALL) The WRALL itruction is valid only when the Protect Register has been cleared by executing a PRCLEAR itruction The WRALL itruction will simultaneously program all registers with the data pattern specified in the itruction Like the WRITE itruction the PE pin MUST be held high while loading the WRALL itruction however after loading the itruction the PE pin becomes a don t care As in the WRITE mode the DO pin indicates the READ BUS status of the chip if CS is brought high after the t CS interval This function is DISABLED if the Protect Register is in use to lock out a section of memory Write Disable (WDS) To protect agait accidental data disturb the Write Disable (WDS) itruction disables all programming modes and should follow all programming operatio Execution of a READ itruction is independent of both the WEN and WDS itructio Note For all Protect Register Operatio If the PRE pin is not held at V IH all itructio will be applied to the EEPROM array rather than the Protect Register Protect Register Read (PRREAD) The PRREAD itruction outputs the address stored in the Protect Register on the DO pin The PRE pin MUST be held high while loading the itruction sequence Following the PRREAD itruction the 6- or 8-bit address stored in the memory protect register is traferred to the serial out shift register As in the READ mode a dummy bit (logical 0) precedes the 6- or 8-bit address string Protect Register Enable (PREN) The PREN itruction is used to enable the PRCLEAR PRWRITE and PRDS modes Before the PREN mode can be entered the part must be in the Write Enable (WEN) mode Both the PRE and PE pi MUST be held high while loading the itruction sequence Note that a PREN itruction must immediately precede a PRCLEAR PRWRITE or PRDS itruction Protect Register Clear (PRCLEAR) The PRCLEAR itruction clears the address stored in the Protect Register and therefore enables all registers for the WRITE and WRALL itruction The PRE and PE pi must be held high while loading the itruction sequence however after loading the PRCLEAR itruction the PRE and PE pi become don t care Note that a PREN itruction must immediately precede a PRCLEAR itruction Please note that the PRCLEAR itruction and the PRWRITE itruction will both program the Protect Register with all 1s However the PRCLEAR itruction will allow the LAST register to be programmed whereas the PRWRITE itruction e all 1s will PREVENT the last register from being programmed In addition the PRCLEAR itruction will allow the use of the WRALL command where the PRWRITE e all 1s will lock out the Bulk programming opcode Protect Register Write (PRWRITE) The PRWRITE itruction is used to write into the Protect Register the address of the first register to be protected After the PRWRITE itruction is executed all memory registers whose addresses are greater than or equal to the address specified in the Protect Register are protected from the WRITE operation Note that before executing a PRWRITE itruction the Protect Register must first be cleared by executing a PRCLEAR operation and that the PRE and PE pi must be held high while loading the itruction however after loading the PRWRITE itruction the PRE and PE pi become don t care Note that a PREN itruction must immediately precede a PRWRITE itruction Protect Register Disable (PRDS) The PRDS itruction is a ONE TIME ONL itruction which renders the Protect Register unalterable in the future Therefore the specified registers become PERMANENTL protected agait data changes As in the PRWRITE itruction the PRE and PE pi must be held high while loading the itruction and after loading the PRDS itruction the PRE and PE pi become don t care Note that a PREN itruction must immediately precede a PRDS itruction 5 http www national com

6 Itruction Set for the NM93CS06 and NM93CS46 Itruction SB Op Code Address Data PRE PE Comments READ 1 10 A5 A0 0 X Reads data stored in memory starting at specified address WEN XXXX 0 1 Enable all programming modes WRITE 1 01 A5 A0 D15 D0 0 1 Writes address if unprotected WRALL XXXX D15 D0 0 1 Writes all registers Valid only when Protect Register is cleared WDS XXXX 0 X Disables all programming modes PRREAD 1 10 XXXXXX 1 X Reads address stored in Protect Register PREN XXXX 1 1 Must immediately precede PRCLEAR PRWRITE and PRDS itructio PRCLEAR Clears the Protect Register so that no registers are protected from WRITE PRWRITE 1 01 A5 A0 1 1 Programs address into Protect Register Thereafter memory addresses t the address in Protect Register are protected from WRITE PRDS ONE TIME ONL itruction after which the address in the Protect Register cannot be altered Note Address bits A5 and A4 become Don t Care for the NM93CS06 Itruction Set for the NM93CS56 and NM93CS66 Itruction SB Op Code Address Data PRE PE Comments READ 1 10 A7 A0 0 X Reads data stored in memory starting at specified address WEN XXXXXX 0 1 Enable all programming modes WRITE 1 01 A7 A0 D15 D0 0 1 Writes address if unprotected WRALL XXXXXX D15 D0 0 1 Writes all registers Valid only when Protect Register is cleared WDS XXXXXX 0 X Disables all programming modes PRREAD 1 10 XXXXXXXX 1 X Reads address stored in Protect Register PREN XXXXXX 1 1 Must immediately precede PRCLEAR PRWRITE and PRDS itructio PRCLEAR Clears the protect register so that no registers are protected from WRITE PRWRITE 1 01 A7 A0 1 1 Programs address into Protect Register Thereafter memory addresses t the address in Protect Register are protected from WRITE PRDS ONE TIME ONL itruction after which the address in the Protect Register cannot be altered Note Address bit A7 becomes Don t Care for the NM93CS56 http www national com 6

7 Timing Diagrams Synchronous Data Timing TL D READ PRE e 0 PE e X The memory automatically cycles to the next register with continued clocking of SK TL D http www national com

8 Timing Diagrams (Continued) WEN PRE e 0 D0 e TRI-STATE TL D WDS PRE e 0 PE e X DO e TRI-STATE TL D WRITE PRE e 0 TL D http www national com 8

9 Timing Diagrams (Continued) WRALL PRE e 0 (PROTECT REGISTER MUST BE CLEARED) TL D PRREAD PE e X TL D http www national com

10 Timing Diagrams (Continued) PREN D0 e TRI-STATE (A WEN CCLE MUST PRECEDE A PREN CCLE) TL D PRCLEAR (A PREN CCLE MUST IMMEDIATEL PRECEDE A PRCLEAR CCLE) TL D http www national com 10

11 Timing Diagrams (Continued) PRWRITE (PREN CCLES MUST IMMEDIATEL PRECEDE A PRWRITE CCLE ) TL D PRDS ( ONE TIME ONL INSTRUCTION A PREN CCLE MUST IMMEDIATEL PRECEDE A PRDS CCLE ) TL D http www national com

12 Physical Dimeio inches (millimeters) unless otherwise noted Molded Package Small Outline 0 15 Wide 8-Lead (M8) NS Package Number M08A http www national com 12

13 Physical Dimeio inches (millimeters) unless otherwise noted Note Unless otherwise specified Note 1 Reference JEDEC Registration M0153 Variation AA DAted Pin Molded TSSOP JEDEC (MT8) NS Package Number MTC08 13 http www national com

14 NM93CS06 CS46 CS56 CS66 (MICROWIRE Bus Interface) Bit Serial EEPROM with Data Protect and Sequential Read Physical Dimeio inches (millimeters) unless otherwise noted (Continued) LIFE SUPPORT POLIC Molded Dual-In-Line Package (N) NS Package Number N08E NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 (0) th Floor Straight Block Tel Arlington TX europe support c com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel a49 (0) Tsimshatsui Kowloon Fax 1(800) English Tel a49 (0) Hong Kong Fran ais Tel a49 (0) Tel (852) http www national com Italiano Tel a49 (0) Fax (852) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio