MODELING MEMORY ERRORS IN PIPELINED ANALOG-TO-DIGITAL CONVERTERS

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1 MODELING MEMORY ERRORS IN PIPELINED ANALOG-TO-DIGITAL CONVERTERS John P. Keane, Paul J. Hurst, and Stephen H. Lews Dept. of Electrcal and Computer Eng. Unversty of Calforna, Davs, CA 9566, USA. emal: ABSTRACT Swtched-capactor mplementatons of ppelned ADCs contan several sources of memory errors, ncludng capactor delectrc absorpton/relaxaton, ncomplete stage reset at hgh clock rates, and parastc capactance effects when op amps are shared between subsequent ppelne stages. Ths paper descrbes these sources of memory errors and presents a unfed model for ther effect. The dependence of these errors on crcut parameters and ADC samplng rate s also dscussed. The effect of these errors on ADC lnearty s then analyzed, showng how memory errors can lmt the performance of a ppelned ADC. KEY WORDS Analogue crcuts, analog-dgtal converson, swtched capactor crcuts, modellng, delectrc materals. Introducton A conventonal ppelned analog-to-dgtal converter ADC) archtecture s shown n Fgure. It conssts of an nput sample-and-hold amplfer SHA) and N ppelned stages. All sgnals shown are normalzed to the reference voltage V ref e.g. x 0 = V n /V ref where V n s the ADC nput voltage). The SHA samples the nput sgnal x 0 at a unform rate f s = /T where T s the sample perod, multples t by a gan G 0 where G 0 n general) and holds the output x as the nput of the frst ppelne stage. Each ppelne stage conssts of an analog-to-dgtal sub-converter ADSC), a dgtal-to-analog sub-converter DASC) and a SHA wth nomnal gan G. The ADSC generates a dgtal estmaton d of the stage nput x. Usng a DASC, d s converted to an analog sgnal K d that s subtracted from x to form the resdue y. y = x K d ) Ths resdue s multpled by a gan G and then sampled and held as the nput x + to the next ppelne stage. In general, the fnal stage N s smply an ADSC as only ts decson output d N, and not ts amplfed resdue, s requred. The transfer functon of each stage can be wrtten x + = G x K d ) ) The ADC produces a dgtal output x 0 [k] that s a x 0 x 0 G 0 SHA x T/H d d d d N Stage x Stage x 3 x Stage x + x N Stage N x y x G T/H x + ADSC K d d DASC Fgure. Ppelne ADC dgtal estmate of the normalzed analog nput x 0 [k] = V n kt)/v ref. Ths output s generated usng dgtal logc to calculate a weghted sum of the stage decson outputs d = d, d,..., d N ) T usng the weghts w = w, w,...,w N ) T x 0 = w T d = w d 3) = By referrng each DASC output to the ADC nput, the deal values of these weghts are computed as w = K 4) G j j=0 If the deal weghts n 4) are used n 3) then, assumng all components are deal and noseless, x 0 = x 0 + q 5) where the quantzaton error q s gven by N q = K N d N x N ) 6) G j j=0 As addtonal stages are added to the ppelne, q becomes smaller, and the resoluton of the converter ncreases. In order to smplfy the dgtal calculaton n 3), the gans K and G are usually desgned to be nteger powers of. In practce, accurate nterstage gan s dffcult to ensure n a modern VLSI process due to factors such as capactor msmatch and lmted op amp gan. In order to correct

2 for lnearty errors that would result from nterstage gan naccuracy, calbraton technques[, ] can be used. Whle these calbraton technques allow correcton for nterstage gan errors, they assume that each stage of the ppelne s memoryless. In practce, ths assumpton may not be true, and memory effects can cause lnearty errors that are not correctable usng these conventonal technques. Ths paper descrbes some sources of these memory errors and the effect that they have on ppelned ADC lnearty. Sources of Memory Effect. Capactor delectrc absorpton / relaxaton effects The memory effect of delectrc relaxaton on successveapproxmaton ADCs was descrbed n [3]. Recently ths effect was also shown to lmt the lnearty of a ppelned ADC[4] for a process usng a slcon ntrde SN) delectrc rather than conventonal slcon doxde SO ) delectrc for capactors. SN capactors have the advantage of much hgher densty than SO capactors and so have the potental to reduce de cost when large capactors are requred. However, these capactors exhbt a much larger memory effect due to capactor delectrc absorpton/relaxaton. Ths phenomenon s essentally due to carrers beng trapped n the delectrc and slowly released over tme and can be observed [4, 5] by the followng threephase procedure:. Charge a capactor to a voltage V C = V nt.. At tme t = 0, dscharge the capactor by shortng ts termnals together untl tme t = t Allow the capactor to float untl tme t = t f. The charge trapped n the delectrc durng phase above tends to gather back on the capactor plates durng phase 3, deally followng a logarthmc law[3, 4] V C t f, t 0 ) = γv nt 7) where γ = κlnt f /t 0 ) and κ s determned by the ntensty of the trap/release process n the delectrc. A common swtched-capactor mplementaton[6] of the ppelne stage n Fg. s shown n smplfed form n Fg. a). Although a sngle-ended crcut s shown for smplcty, n practce a fully dfferental crcut would be used. A tmng dagram for the clocks and used n ths stage are shown n Fg. b). Although short nonoverlappng tmes are often used between clock phases n practce[6], these are not shown here for smplcty and the duratons t and t of and, respectvely are both chosen to be T/. If the op amp s deal.e. a, offset=0) and there s no memory effect, then the output at the end of phase can be found from C f V + kt + T/) = C f + C n )V kt) 8) C n V DASC kt + T/) The parastc capactor C p has no effect n 8) as the nvertng termnal of the op amp s at the ground potental at the V t C n V DASC a) t C f C p a V + kt-t/ kt kt+t/ k+)t b) Fgure. a)swtched-capactor ppelne stage usng flparound archtecture, b) tmng dagram and are nonoverlappng). end of each phase. In ths paper, the tme ndex n e.g. d [n]) s used to denote the sgnals correspondng to a gven ADC nput sample and converson cycle. Although the stages n a ppelned ADC operate at dfferent tmes on resdues that correspond to one ADC nput sample, any sgnal that refers to the converson of the same nput sample wll be gven the same ndex. For example, although each stage output decson d [n] for a gven nput sample s generated at a dfferent tme, d [n] refers to the decson of stage correspondng to the converson of the nput sample x 0 [n] = x 0 nt). Usng ths conventon, defne the normalzed varables x [n] = V kt)/v ref 9) x + [n] = V + kt + T/)/V ref 0) d [n] = V DASC kt + T/)/K DASC ) where K DASC s the DASC gan n volts. In a typcal ppelned ADC[6], all stages, ncludng the SHA, have a delay of T/. In ths case k = n+0.5 n 9), 0) and ). Substtutng these expressons nto 8) gves x + [n] = G x [n] K d [n]) ) G = + C n /C f ) 3) K = K DASC /V ref )C n / C n + C f ) 4) Hence, for deal lnear capactors wthout memory effect, ths swtched-capactor ppelne stage can be modeled as shown n Fg. wth the transfer functon gven n ). In [4] a smple model for the memory effect caused by capactor delectrc absorpton/relaxaton was gven, representng the phenomenon as a smple one-tap fnte-mpulse response effect. In ths case, only relaxaton due to charge absorbed n the mmedately precedng phase s consdered. t

3 Usng normalzed varables, the stage transfer functon ncludng ths memory effect can be wrtten as: x + [n] = G x [n] K d [n]) 5) +γ f x + [n ] + γ n G K d [n ] V φ C C C n f φ C n f V V φ DASC DASC C p V m a V out where G and K are the same as for ) above. Here γ n and γ f model the memory effect of C n and C f, respectvely. From 7), Stage Stage γ n = κ n lnt/t ) = κ n ln) 6) γ f = κ f lnt/t ) = κ f ln) as t = T/ n ths case. If both C f and C n use the same delectrc materal κ n κ f and so γ n γ f. From 6), t can be seen that n ths case the magntude γ of ths memory effect s ndependent of the samplng rate f s = /T.. Incomplete stage reset effects In general, the perod T s chosen to be long enough to allow settlng n each phase of the resdue amplfer operaton to the requred accuracy of the converter. For hgh speed operaton, ths requres large swtches wth low onresstance, and a hgh-speed op amp to mnmze the settlng tme durng the amplfcaton phase. Incomplete settlng durng can be modeled as errors n the nterstage gan G and the DASC gan K f the settlng s lnear []. Such errors can be compensated for usng calbraton technques for nterstage gan errors [, ]. However, ncomplete settlng durng the reset phase causes memory-effect errors that can not be corrected usng these approaches. To llustrate ths pont, consder agan the ppelne stage n Fg.. Let the voltages on the capactors C n and C f be V Cn and V Cf, respectvely. Ideally, V Cn = V Cf = V at the end of. However, f the duraton of s too short to allow complete resettng of the voltages across C n and C f, V Cn and V Cf at the end of depend n part on the voltage changes that the crcut tres to mpress durng. From Fg. b), phase of sample perod k begns at tme t = kt T/ and ends at t = kt. If lnear settlng can be assumed, then V Cf kt) = V kt) γ f ) + γ f V Cf kt T ) 7) V Cn kt) = V kt) γ n ) + γ n V Cn kt T ) 8) where the factors γ f and γ n are constants determned by the duraton t of and the settlng tme constants of C f and C n. A fracton of the prevous capactor voltage s retaned after the reset phase n 7) and 8) resultng n a memory effect smlar to that descrbed n Secton.. In ths case, the values of γ f and γ n can be reduced by operatng at a lower rate f s = /T, whch ncreases t. If the op amp s deal and complete settlng s assumed durng, then the stage transfer functon n ths case s Fgure 3. Swtched-capactor ppelne stage usng shared op amp. V out = V + durng and V out = V + durng. gven by 5), but wth G = γ f ) + γ n )C n /C f. 9) Hence, the stage output x + [n] depends on ts prevous output x + [n ] and DASC nput d [n ], whch consttutes a memory effect that can not be corrected for usng nterstage gan calbraton technques..3 Op amp sharng effects As descrbed above, the ppelne stage shown n Fg. operates n two phases. Durng the reset phase the capactors are reset by chargng them to the stage nput voltage V. Durng the amplfcaton phase, the op amp s used to perform the subtractng and amplfcaton functons of the stage. In general, subsequent stages of the ppelne operate n opposte phases,.e. whle stage amplfes, stage s reset and vce-versa. Snce the op amp s only requred durng the amplfcaton phase, op amp sharng between subsequent stages has been proposed [7] n order to reduce the number of requred op amps by a factor of and hence reduce power and area requrements. The structure used n [7] s shown n Fg. 3. Comparng to Fg. shows that Fg. 3 contans two cascaded ppelne stages that share a sngle op amp. Durng the op amp generates the output V out = V + of stage, whle drvng the nput of stage. Durng, the op amp generates the output V out = V + of stage and drves subsequent stage 3. Addtonal swtches are added to the negatve op amp nput termnal the summng node), to allow t to be swtched between the two stages. Whle ths archtecture can yeld sgnfcant power savngs, t can result n memory effects due to the parastc capactance C p at the negatve termnal of the op amp, as noted n [7]. Ths memory effect occurs when the op amp gan a s lmted and so the voltage V m = V out /a at the end of the amplfyng phase s sgnfcant. At the end of, the op amp output V out = V + kt T/), so ts nput s V m = V + kt T/)/a. At t = kt + T/ the op amp s swtched from stage to stage and the capactor C p njects a charge C p V + kt T/)/a at the summng node of the second stage whle t s generatng V out = V + kt) durng. The transfer functon of stage can be calculated as

4 x [n] x + [n] x + [n-] G z - β x G + [n-] + K d [n] K d [n-] + + Stage Stage a) the output of each odd stage. Therefore, ths memory effect can be modeled entrely n the even stages wthout changng the output of a ppelned ADC that conssts of a cascade of the structures shown n Fg. 3. In ths case, an equvalent model for the ADC transfer functon s gven when each stage s modeled as x + [n] = G x [n] K d [n]) + γ x + [n ] 7) ~ ~ x [n] x + [n] x + [n-] G z - G + K d [n] K d [n-] + + Stage Stage b) βg + z - x + [n-] and γ = 0 for odd and γ = G β for even. Eqn. 5) shows that the memory effect n ths case s ndependent of the samplng rate f s = /T but can be reduced by ncreasng the op amp gan a and/or decreasng the parastc capactance C p. Alternatvely, an addtonal clock phase can be added to reset C p after, but ths adds extra complexty and may reduce the maxmum converson rate. Fgure 4. Model of opamp sharng x + [n] = G + x + [n] K + d + [n]) 0) C f + C n + C p /a G + = ) C f + C f + C n + C p )/a ) KDASC C n K + = C f + C n + C p /a ) V ref Snce the output x + [n] n 0) depends only on the current nput x + [n] and stage decson d + [n], no memory effect results. The parastc capactor C p causes only a change n the factors K and G. Now consder stage when the op amp s swtched from generatng V out = V + kt) durng to generatng V out = V + kt +T/) durng. In ths case, the capactor C p njects a charge C p V + kt)/a onto the summng node of stage durng. The transfer functon of stage can be calculated as x + [n] = G x [n] K d [n]) + β x + [n ] 3) C f + C n G = 4) C f + C f + C n + C p )/a C p /a β = 5) C f + C f + C n + C p )/a ) KDASC C n K = 6) C f + C n V ref Snce the output x + of stage n 3) depends on the prevous output x + of stage, a memory effect exsts that can result n nonlnearty. Combnng 0) and 3) gves the model shown n Fg. 4a). Ths model shows that a delayed verson of the output of the even stage s added to the output of the odd stage. The model can be changed so that the memory effect s completely contaned wthng one stage, as shown n Fg. 4b). The key step n ths transformaton s to note that an even stage follows and processes 3 Lnearty errors due to memory effects To consder the effect on converter accuracy of the memory effect n each stage, consder the stage transfer functon. The result n 5), whch apples to the memory effects descrbed n Sectons. and., can be summarzed by the expresson: x + [n] = G x [n] K d [n]) 8) +γ x + [n ] + δ G K d [n ] where γ and δ correspond to the memory effects γ f and γ n of the stage output and DASC output of stage, respectvely. The memory effect descrbed n Secton.3 resulted n the equvalent stage transfer functon gven n 7). Ths s dentcal to 8) except that δ = 0 for all stages n ths case. Computng the z-transform of 8) and rearrangng terms gves X z) = δ z )K z)d z) 9) + G γ z )X + z) N where X z) and D z) are the z-transforms of x [n] and d [n], respectvely. The nput SHA stage 0) can also be modeled by 9) f t s consdered as a stage wth the DASC removed.e. D 0 z) = 0). From 9), X + z) s gven by G X + z) = X γ z z) δ z )K D z) ) 30) The stage model usng 30) s shown n Fg. 5a). For the case where δ = 0, as n the opamp sharng memory effect descrbed n Secton.3, the stage can be modeled as n Fg. 5b). For the case where δ = γ, as can often be assumed for the memory effects descrbed n Sectons. and., 30) can be rewrtten as X + z) = G γ z G K D z) 3)

5 K D z) K D z) K D z) - δ z - Y z) Y z) G a) G b) S z) - γ z - c) - γ z - - γ z - G Fgure 5. Ppelne stage model a) ncludng memory effect, b) wth δ = 0, c) wth δ = γ. and modeled as shown n Fg. 5c). In general, the fnal ppelne stage stage N) conssts of an ADSC only and hence does not suffer from the memory effects dscussed n Secton. In ths case, from 6), X N z) can be wrtten as N X N z) = K N D N z) Qz) G K 3) k=0 where Qz) s the z-transform of the ADC quantzaton error q[n]. Startng wth the defnton 3) for X N z), 9) s recursvely appled for = N, N,...,0 to gve [ ] X 0 z) = w D z) δ z ) γ k z ) = k=0 N Qz) γ k z ) 33) k=0 where w are the weghts as defned n 4) and δ N = 0 when the fnal stage s an ADSC only. If the expresson n 3) s used to calculate the dgtal output x 0 [n], ts z-transform X 0 z) s gven by X 0 z) = w D z) 34) = In ths case, combnng 33) and 34) gves X 0 z) X 0 z) = N k=0 γ + Qz) 35) kz ) ) δ z + w D z) N k= γ kz ) = The frst term n 35) corresponds to a lnearly fltered verson of the nput X 0 z). The second term corresponds to the quantzaton error of the converter. The last term contans a weghted sum of past stage decsons. Ths s the term that contrbutes nonlnearty to the overall ADC transfer functon. To demonstrate the effects of ths term on converter lnearty, frst consder only memory effect n the SHA.e. γ = 0 for > 0 and δ = 0 for all stages). Here, 35) becomes X 0 z) = X 0z) + Qz) 36) γ 0 z Note that 36) has only lnear flterng of X 0 z), and hence wll not degrade the lnearty of the converter, although t wll add a hgh-frequency pole to ts frequencydoman transfer functon, resultng n some low-pass flterng. Next, consder memory effect only n the SHA and frst ppelne stage.e. γ = 0 and δ = 0 for > ). Here 35) becomes X 0 z) X 0 z) = γ 0 z ) γ z 37) ) + K ) D z) δ γ G 0 γ z z + Qz) An addtonal pole has been added to the lnear flterng of the nput X 0 z) due to the memory effect of stage. The second term n 37) nvolves the prevous values of the frst stage decson d. Snce these past decsons are correlated wth the the current nput X 0 n general, nonlnearty n the form of spectral tones wll result from ths term. However, n the common case where δ γ, the second term n 37) wll almost dsappear and so the memory effect of the frst stage wll not cause sgnfcant ADC nonlnearty. Extendng the memory effect to two stages gves X 0 z) = X 0 z) =0 γ z ) + K D z) G 0 + K D z) G 0 G 38) δ γ γ )z + γ γ z ) γ z ) γ z ) ) z + Qz) δ γ γ z In ths case the output contans terms relatng to prevous decsons d and d of stage and stage, respectvely. Even n the case where γ = δ, terms relatng to prevous values of d wll reman, causng converter nonlnearty. Intutvely, the reason that memory effect n the frst stage does not cause nonlnearty when γ = δ s that the memory effect of the output x and the decson d combne to form an equvalent memory effect on the frst stage nput x only, as shown n Fg. 5c). Snce x contans no quantzaton error, only lnear flterng of the nput results. However, snce the output of each stage n a ppelned ADC s an amplfed verson of the quantzaton error of

6 INL LSB) INL LSB) INL LSB) Code a) Code b) 5 0 f=f 0 f=f Code c) Fgure 6. Smulated INL at -bt level for.5b/stage ppelne ADC wth γ = δ = a) for frst stage only, b) for frst stages, and c) for all stages wth nput full-scale snewave at frequences f /T sold) and f 0 dashed). the prevous stage, memory effects n subsequent stages wll nclude ths nonlnear quantzaton error and hence cause overall converter nonlnearty. Ths s shown when the memory effect s extended to stages n 38). Fg. 6 shows the smulated converter ntegral nonlnearty INL) at -bt level for a conventonal -stage.5 bt/stage ppelne ADC[6]. A.5 bt stage has nomnal gan G =, ADSC thresholds at ±V ref /4 and DASC levels of 0, ±V ref /. The test sgnal s an nput snewave wth ampltude 95% of full-scale at frequences f 0 = 0.007/T. sold) and f 0 dashed). The result n Fg. 6a) s for memory effect wth γ = δ = for the frst stage only. Snce the ADC s otherwse deal, the INL s almost zero n ths case. Ths verfes that memory effect n the frst stage when γ = δ does not cause nonlnearty. In Fg. 6b), the INL s shown where the frst two stages have a memory effect wth γ = δ = and all others are deal. The memory effect results n an INL of ±3.7 LSB. When the nput snewave frequency s doubled from f 0 to f 0, the wdth of the INL dscontnutes around the frst stage ADSC thresholds of ±V ref /4 ncreases. Hence, the measured INL s frequency-dependent. These dscontnutes are caused when an nput sample s mmedately preceded by a sample that s on the other sde of an ADSC threshold. In ths case, the DASC output jumps by one level, but a memory stll exsts of the prevous DASC output resultng n a memory error. When the nput frequency ncreases, the dfference between the current and last nput sample ncreases, so INL errors occur due to ths effect occur for codes further away from the ADSC thresholds. When the memory effect s extended to all stages, Fg. 6c) shows the resultng converter INL of ±5.3 LSBs. Ths slght ncrease shows that the memory error n ths case s domnated by the second stage. The INL n ths case can also be seen to vary slghtly wth the nput frequency. 4 Concluson Sources of memory effects n ppelned ADCs due to capactor delectrc absorpton/relaxaton, ncomplete stage reset, and op amp sharng have been descrbed and modeled. Whle errors due to ncomplete stage reset can be reduced by decreasng the ADC converson rate f s = /T, the other effects descrbed are ndependent of f s. These memory effects can lmt the ADC lnearty. However, for common cases, memory effects n the SHA and frst ppelne stage do not cause ADC nonlnearty. Ths allows some flexblty of the desgn of these stages, whch typcally domnate the power and area of a ppelned ADC due to nose consderatons. Acknowledgements Ths research was supported by UC MICRO Grant No and by NSF Grant No. CCR References [] A. N. Karancolas, H.-S. Lee, and K. L. Barcrana, A 5-b -Msample/s dgtally self-calbrated ppelne ADC, IEEE Journal of Sold-State Crcuts, 993, 8), [] J. Mng and S. H. Lews, An 8-bt 80-Msample/s ppelned analog-to-dgtal converter wth background calbraton, IEEE Journal of Sold-State Crcuts, 00, 360), [3] J. W. Fattaruso, M. de Wt, G. Warwar, K-S. Tan, and R. K. Hester, The effect of delectrc relaxaton on charge-redstrbuton A/D converters, IEEE Journal of Sold-State Crcuts, 990, 56), [4] A. Zanch, F. Tsay, and I. Papantonopoulos, Impact of capactor delectrc relaxaton on a 4-bt 70-MS/s ppelne ADC n 3-V BCMOS, IEEE Journal of Sold- State Crcuts, 003, 38), [5] H. Resnger, G. Stenlesberger, S. Jakschk, M. Gutsche, T. Hecht, M. Leonhard, U. Schroder, H. Sedl, and D. Schumann, A comparatve study of delectrc relaxaton losses n alternatve delectrcs, Int. Electron Devces Mtg. Tech. Dg., Washngton, D.C., USA, 00, [6] S. H. Lews, H. S. Fetterman, G. F. Gross Jr, R. Ramachandran, and T. R. Vswanathan, A 0-b 0- Msample/s analog-to-dgtal converter, IEEE Journal of Sold-State Crcuts, 99, 73), [7] K. Nagaraj, H. S. Fetterman, J. Andjar, S. H. Lews, and R. G. Rennnger, A 50-mW, 8-b, 5-Msamples/s parallel-ppelned A/D converter wth reduced number of amplfers, IEEE Journal of Sold-State Crcuts, 997, 33), 3 30.