Bob York. Simple FET DC Bias Circuits

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1 Bob York Simple FET DC Bia Circuit

2 Loa-Line an Q-point Conier the effect of a rain reitor in the comnon-ource configuration: Smaller + g D out KL: Thi i the equation of a line that can be uperimpoe on the FET - characteritic a hown at right. Thi i the loa-line. / Larger Q point g = tn +.0 g = tn +.5 g = tn +.0 ncreaing g knee The point of interection repreent the allowe evice voltage an rain current for the reitor-fet combination. Thee are the quiecent operating conition or Q point, i.e. the DC bia conition. There are a number of poible Q-point along the loa-line, epening on the gate voltage. t i the job of the circuit eigner to chooe thi Q-point. The choice of Q-point will vary with the circuit application. For imple amplifier circuit a Q- point in the mile of the aturation region i often eirable.

0 ncreaing g knee The point of interection repreent the allowe evice voltage an rain current for the reitor-fet combination. Thee are the quiecent operating conition or Q point, i.e. the DC bia conition.

3 FET DC Biaing Conier the eign of the circuit to et a certain Q-point: FET Parameter: +0 D out Deign goal: K t n out 5mA/ 6 0mA 45mA 0mA 5mA g = 4 g = 3 g = g To get a 4 rop acro the rain 0mA current require a reitor value mA 6 0 The eign goal put the Q-point right in the mile of the aturation region in the - curve where K ( ) n g t g 0mA t 3 K 5mA/ n With a plot of the FET - curve we can quickly tell at a glance whether the Q-point i in the aturation or ohmic region. Without the viual plot we coul make an initial gue an then check to ee whether the anwer i conitent with thi aumption: Saturation require: g t 0 3

region in the - curve where K ( ) n g t g 0mA t 3 K 5mA/ n With a plot of the FET - curve we can quickly tell at a glance whether the Q-point i in the

4 Simple NMOS Gate Bia Network The previou eign example require two DC ource: a rain upply (+0) an a gate upply (+3) A impler olution for enhancement-moe evice i to ue jut a ingle upply at the rain an generate the require gate voltage uing a reitor ivier: +0 oltage ivier to et the gate voltage require for a certain kω Ω +6 0 ma emember: no current flow into the gate. Thi implifie the eign an analyi of the gate bia circuit 300 kω n icrete circuit the gate bia reitor uually have large value. You will learn why in ECE C when we icu AC amplifier. n ntegrate Circuit (C) eign, large reitor take up too much pace an a ifferent approach i taken. We will explore thi later.

emember: no current flow into the gate. Thi implifie the eign an analyi of the gate bia circuit 300 kω n icrete circuit the gate bia reitor uually have large value.

5 Simple PMOS Biaing Example MΩ g MΩ g +9 out Problem: Fin the rain voltage an current auming the following FET parameter: The voltage at the gate noe i: g K tp p ma/ M 9 6 MM The ource-gate voltage i then: g 96 3 kω Auming the evice i in aturation, the rain current i: ma/ 3 4mA an the output voltage i:? g tp 4mA k 4 out Double-check that the evice i in aturation: Note: if the rain reitor wa increae to kω the evice woul no longer be in aturation an we woul nee to re-analyze the circuit uing the equation appropriate to the ohmic region. out

6 Stabilizing the Bia Point: Source eitance All example o far have ue a contant g bia cheme. The problem with thi approach i evient when we conier thing like temperature variation or manufacturing tolerance on evice parameter. A hown at right, two ifferent evice can yiel a large ifference in rain current when biae at the ame voltage g g g D t t Device # Device # g g A imple olution i to a a ource reitance. Thi provie negative feeback to tabilize the rain current with repect to evice parameter variation g D g lope g g g g Another loa-line g S f rain current increae ue to parameter change, will rie an thi lower g which in turn reuce t t g g

A hown at right, two ifferent evice can yiel a large ifference in rain current when biae at the ame voltage g g g D t t Device # Device # g g A imple olution i

7 The Four-eitor Bia Network g The tanar bia network for icrete eign g g g = 0 g + D S g g Deign Proceure for a given FET Specify Q-point ( an ) Net reitance can be etermine from loa-line: ( ) Loa-line now a function of both an Often there will be contraint on or impoe by the application. f or i pecifie, then Once an are known we can eign the gate bia network. equire g etermine from - curve. n aturation: Then gate voltage an voltage-ivier can be eigne accoring to: or g g g g g t K n lope ncreaing g Alway ouble-check that the eign i conitent with aumption!

application. f or i pecifie, then Once an are known we can eign the gate bia network. equire g etermine from - curve.

8 FET Bia Builing Block A FET with rain an gate connecte i a common builing block in C bia network Thi connection force the evice into aturation uch that K n out t Common eign problem: Fin the that give a pecifie out or out W / L out g out pecifie K n out t or pecifie t K n emember: the evice W/L ratio can alo be manipulate to vary K n : W Kn kn L Fin the out or for a given out t 4 Kn ( t ) K n 4 K ( ) t n t Kn

pecifie out or out W / L out g out pecifie K n out t or pecifie t K n emember: the evice W/L ratio can

9 Some Example with Drain-Gate Connection Can you fin an out in each cae? ma 3kΩ out out out out 4 ma 3kΩ Aume: t K ma/ +5 4 ma 3kΩ out out out out 4 ma 3kΩ

+5 +5 +5 4 ma 3kΩ out out out out 4 ma 3kΩ

Tripping Current and Short Circuit Current of High Voltage Tester

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