Design of The Feedback Controller (PID Controller) for The Buck Boost Converter

Transcription

1 Deign of The Feedback Controller (PID Controller) for The Buck Boot Converter )Sattar Jaber Al-Iawi ) Ehan A. Abd Al-Nabi Department of Electromechanical Eng. The High Intitute for Indutry-Libya-Mirata attarjaber@yahoo.com ABSTACT The aim of thi paper i to deign a bet compenator for the buck-boot converter ytem operate in a continuou conduction mode. The mall ignal of the buck boot i derived firt to find the line-to-output and control-to-output tranfer function which they help to deign the feedback controller and help in the tudy of the ytem tability. key word: Converter, Control, Switching.Introduction In all witching converter, the output voltage V o ( i a function of the line voltage V i (, the duty cycle d(, and the load current i Load (, a well a the converter circuit element value. In a dc-dc converter application, it i deired to obtain a contant output voltage Vo(Vo, in pite of diturbance in V i ( and i Load (, and in pite of variation in the converter circuit element value [,]. The ource of thee diturbance and variation are many, the input voltage of an off-line power upply may typically contain periodic variation at the econd harmonic of the ac power ytem frequency (00Hz or 0Hz), produced by a rectifier circuit. [3,4]. The magnitude of vi( may alo vary when neighboring power ytem load are witched on or off. The load current i Load ( may contain variation of ignificant amplitude, and a typical power upply pecification i that the output voltage mut remain within a pecification range when the load current take a tep change form. The value of the circuit element are contructed to a certain tolerance, and o in high volume manufacturing of a converter, converter are contructed whoe output voltage lie in ome diturbance [5,6].. Small Signal Model To derive the mall ignal model for the buck boot converter we have to follow the procedure below: t on Interval. During the ubinterval () when the witch ON hown in Fig.(). Fig.() ubinterval () The inductor voltage and capacitor current are: dil( vl ( L* vi(....() dvo( vo( ic( C *.....() Small ripple approximation: replace waveform with their low frequency averaged value. dil( vl ( L* vi(..(3) dvo( ic( C * (4) t off Interval During the ubinterval () when the witch OFF hown in Fig.().

2 Fig.() ubinterval () Inductor voltage and capacitor current are: dil( vl ( L* vo(...(5) dvo( vo( ic( C * il( (6) Small ripple approximation: replace waveform with their low frequency averaged value. dil( vl ( L*..(7) dvo( ic( C* il(.(8) Averaged the inductor waveform vl ( d ( * vi( d ( *.(9) d il( L* d ( * vi( d ( * vo(...(0) Averaged the capacitor waveform ic( d ( *[ ] d ( * [ il( ]...() d C * d ( * il(...() Averaged the input current i i il( ( 0 duringubint erval () duringubint erval () i ( d( * i ( (3) i i The converter averaged equation are: d il( L* d ( * vi( d ( *...(4) d C * d ( * il( (5) ii ( d( * ii (...(6) where, d'(-d( Thee equation are non-linear. By conidering a certain teady tate value and add a mall a.c variation (the a.c component are very mall), the above equation become: d( IL ilˆ( ) L* ( D dˆ( )*( Vi viˆ( ) ( d ( t ))*( Vo )...(7) The d.c term equal zero, and the econd order ac term are mall value and can be neglected. dilˆ( L* D * viˆ( t ) dˆ( t ) * ( Vi Vo) * n *...(8) The a.c equivalent circuit of the above equation i hown in Fig.(3). Fig.(3) The a.c equivalent circuit of inductor loop. The averaged value i :

3 To linearize the capacitor equation: d ( Vo ) C * ( d ( )*( IL ilˆ( ) ( Vo )...(9) The d.c term equal zero, and the econd order ac term are mall value and can be neglected. C * * ilˆ( Io* dˆ(.(0) The a.c equivalent circuit of the above equation i hown in Fig(4). Fig.(4)The a.c equivalent circuit of capacitor node To linearize the input current: ( Ii iˆ ( ) ( D dˆ( )* ( IL iˆ ( )...() i The d.c term equal zero, and the econd order ac term are mall value and can be neglected. iˆ i ( D * ilˆ( n * dˆ( * IL... () The a.c equivalent circuit i hown in Fig.(5) L 3. Tranfer Function of Buck Boot Converter The mall ignal change in the output voltage of the converter can be repreented a follow: v oˆ ( Gvi( * viˆ( Gvd( * dˆ(.(3) where, Gvi Gvd viˆ( ( dˆ 0 vdˆ( ( viˆ 0. (4)..(5) By olving the mall ignal model we can get thee tranfer function a follow: D Gvi(....(6) L LC Vi Vo Gvd * C L C L IL*( )...(7) C 4. Effect of Negative Feedback The block diagram which model the mall-ignal ac variation of the complete ytem of the converter i a hown in Fig.(6) below: Vref Vg( Ve( Vc( i Load Z G Vo( G r G c / G Fig.(5) The a.c equivalent circuit of the input port. H ( Fig.(6) Block diagram which model the mallignal ac variation of the complete ytem of the converter. 3

4 The formula of output voltage variation that repreent the effect of the feedback control on the ytem i a follow: T Gvi( vrefˆ( * viˆ( * H ( T T iload ˆ * Zout...(8) T where, H ( * Gc( * Gvd ( T(..(9) VM From equation (8) it i very clear that the change of the reference voltage, input voltage and load current depend on a certain tranfer function T/(T) and /(T). Thee tranfer function are very important in the deign of the compenator. 5.Controller Deign A Combined PID compenator will be ued to control the dc-dc Buck-Boot converter ytem. The firt tep i to elect the feedback gain H(. The gain H i choen uch that the regulator produce a regulated -5V dc output. Let a aume that we will ucceed in deigning a good feedback ytem, which caue the output voltage to accurately follow the reference voltage. Thi i accomplihed via a large loop gain T(, which lead to a mall error voltage: ve 0. Hence, Hvvref. So we hould chooe : Vref 5 H ( Vo 5 3 The quiecent duty cycle i given by the teady-tate olution of the converter: D Vo V * D by inerting the input and output voltage, we can find the duty cycle: D 5 48* D 0.38 D D D The quiecent value of the control voltage, Vc, will be equal: VcD*VM Vc0.38*30.74V Thu, the quiecent condition of the ytem are known. It remain to deign the compenator gain Gc(. The open loop converter normalized tranfer function derived from the mall ignal model i: ( ) Gvd( * wz (30) ( ) ( ) Qo* Gvi( Gio*...(3) ( ) ( ) Qo* ω o Gio D 0.38 D 0.76 Vo D * L fo. 56KHz 50* * * C *0*0 C Qo * * L wz * D* L fo KHz rad db / ec By uing the above equation, The loop gain of the ytem i: T ( Gc( *( ) * Gvd ( * H ( (3) VM or ( ) Gc ( )* H( * T( wz...(33) VM ( ) ( ) Qo* 4

5 The uncompenated loop gain Tu(, with unity compenator gain Gc(, i: ( ) H( * Tu( wz..(34) VM ( ) ( ) Qo* where the dc gain i: H* 0.334*8.7 Tuo db VM 3 The uncompenated loop gain ha a croover frequency of approximation 3. khz with phae margin 0 degree. In thi paper, we will deign a compenator to attain a croover frequency of fc0khz, or one twentieth of the witching frequency. The uncompenated loop gain ha a magnitude at 0 khz equal to -8 db. In addition the compenator hould improve the phae margin, ince the phae of the uncompenated loop gain i nearly - 0 degree at 0KHz. So a PD compenator i needed. According to the relation between the phae margin and the Q-factor, we will elect the phae margin equal to 5 degree to get Q-factor equal to. With fc0khz and Ө5 degree, lead to the following compenator pole and zero frequencie: in(5) fz (0KHz) * 3. 44KHz in(5) in(5) fp ( 0KHz) * 9KHz in(5) To obtain unity loop gain at 0 KHz and approximate the compenated loop gain by it high frequency, then the low frequency compenator gain mut be: fc fz Gco ( ) * ( ) * db fo Tuo fo The loop gain with the PD controller become: ( )*( ) H( * T( wz wz...(35) VM ( )*( ( ) ( ) ) wp Qo* The low frequency regulation can be further improved by addition of an inverted zero. A PID controller i then obtained. The compenator tranfer function become: wl ( ) *( ) Gc( Gcm wz...(36) ( ) wp 6.8k ( ) *( ) Gc(.8*.66k ( ) 8.k The pole and zero fp and fz are unchanged. The midband gain (Gcm) i choen to be the ame a the previou (Gco). Hence, for frequencie greater than the fl, magnitude of the loop gain i unchanged by the inverted zero. The loop continue to exhibit a croover frequency of 0 KHz. The frequency fl will choen to be one-tenth of the cro over frequency, or KHz. The inverted zero will then increae the loop gain at frequencie below KHz, improving the low frequency regulation of output voltage. With PID controller, the loop gain will be: wl ( )*( )*( ) H( * T( wz wz VM ( )*( ( ) ( ) wp Qo* By doing many tet for different croover frequency, we found that increaing the cro over frequency more than 0K will reduce the phae margin and that will effect the tability of the ytem. It i found that when we deign compenator for croover frequency equal to 0kHz (0% of the witching frequency), the phae margin will be equal ) 5

6 to 3 degree. Alo, by putting the cro over frequency equal to 30KHz (5% of the witching frequency) the phae margin will be equal to 4 degree. The mall value of the phae margin ( in T() cae the cloe loop tranfer function (/(T)) and (T/(T)) to exhibit reonant pole with high Q. The ytem tranient repone exhibit overhoot and ringing. A the phae margin i reduce thee characteritic become wort (higher Q, longer ringing) until the ytem become untable. From the previou figure of bode plot, we can ee that the loop gain at 0Hz i equal to 47 db. Thi gain can be improved by increaing (fl); however, thi would require redeign of the PD portion of the compenator to maintain an adequate phae margin. 6. Simulation A MATLAB/Simulink model i build to imulate the deign of buck boot compenator which i deigned before. Fig.( 7) and Fig.( 8) how the output voltage veru the input voltage tep change from 44V to 5V at and from 5V to 44V at From thee figure it i very clear that the controller repond very well under thi change. Fig.( 7)Output voltage veru the input voltage tep change from 44V to 5V at and from 5V to 44V at Fig.( 8)Output voltage veru the input voltage tep change from 44V to 5V at and from 5V to 44V at

7 The overhoot and the ettling time for the input change from the 44V to 5V are equal to 0.5% and zero ( according to the definition of ±%, but if we jut calculate the time till it become table i equal to 0.5m repectively. The overhoot and the ettling time for the input change from the 5V to 44V are equal to % and zero (according to the definition of ±% of the output ignal, but if we jut calculate the time till it become table i equal to 0.5m repectively. Fig.( 9) and Fig.(0) how the output voltage veru the load tep change from 00% to 50% at and from 50% to 00% at From thee figure it i very clear that the controller repond very well under thi change. The overhoot and the ettling time for the load change from the 00% to 50% are equal to 0.66% and zero ( according to the definition of ±%, but if we jut calculate the time till it become table i equal to 0.m repectively. The overhoot and the ettling time for the load change from the 50% to 00% are equal to 0.8% and zero (according to the definition of ±% of the ignal, but if we jut calculate the time till it become table i equal to 0.mrepectively. Fig.(0)The output voltage veru the load tep change from 00% to 50% at and from 50% to 00% at Fig.( 9)The output voltage veru the load tep change from 00% to 50% at and from 50% to 00% at Fig.() and Fig.() how the output voltage veru the voltage reference tep change from 0V to 5V at 0.00 and from 5V to 0V at From thee figure it i very clear that the controller can not overcome the big change in the reference voltage. The overhoot and the ettling time for the reference voltage change from the 0V to 5V are equal to 73% and 0.00 repectively. The overhoot and the ettling time for the reference voltage change from the 5V to 0V are equal to zero and repectively. 7

8 7. Concluion Fig.() Output voltage veru the voltage reference tep change from 0V to 5V at In thi paper a deign of the feedback controller (PID controller) for the buck boot converter i done to get the bet performance. A MATLAB/Simulink model i build to verify the performance of the compenator deign. By applying large ignal variation (for example by applying change for the reference voltage from 0V to 5V) the ytem work fine but there i ome overhoot and underhoot at the time of change. Alo, the compenator i tet for change in the input voltage and change in the load. During thee change the ytem behave very well with very le overhoot and ettling time. The PI compenator i ued to increae the low frequency loop gain, uch that the output i better regulated at d.c and at frequencie well below the loop croover frequency. PD i ued to increae the bandwih of the feedback loop and to increae the phae margin at the croover frequency. The croover frequency (fz) i hould be choen to be uccefully le than croover frequency, uch that an adequate phae margin i maintained. eference Fig.() Output voltage veru the voltage reference tep change from 5V to 0V at [].Sattar Jaber Al-Iawi, Ehan A. Abd Al-Nabi "DESIGN A DISCETE CONTOL SYSTEM OF PWM AC-AC CONVETE", Drive,Proc. Of Int. UPEC, 008. [].M.M.Hamada et al, "Harmonic Current of Lighting Controller (Dimmer", 37 th Int. UPEC,00 [3] H.P. Tiwari &.A. Gupta, Tranient Behaviour of -Pule Cycloconverter Fed Induction Motor Drive,Proc. Of Int. UPEC, pp , 00. [4] A. K. Chattopadhayaya, Cycloconverter Fed Drive: A eview, Journal of Indian Intitute of cince,vol.77 pp , Sept.-Oct., 997. [5].A.Kawamura,. Chuaryapratip," Deadbeat Control of PWM Inverter with Modified Pule Pattern for Unintirruptible Power Supply", IEEE Tran. On Ind. Elect. Vol 35 n [6] Collin & E. andolph, Torque and lip Behaviour of ingle phae induction motor driven from variable frequency upplie, IEEE Tran. on Ind., Appln.Vol.8,, May-Jaune,