# Invited Talk: Introduction to Electromigration-Aware Physical Design

Save this PDF as:

Size: px
Start display at page:

## Transcription

2 where A is a constant based on the crosssectional area of the interconnect, J is the current density, E a is the activation energy (e.g. 0.7 ev for grain boundary diffusion in aluminum), k is the Boltzmann constant, T is the temperature and n a scaling factor (usually set to 2 according to Black [1]). It is clear that current density J and (less so) the temperature T are deciding factors in the design process that affect electromigration. This talk concentrates on the possibilities during physical design of manipulating current density in order to obviate the negative effects of electromigration on the reliability of electronic interconnects. We will first explain the physical causes of electromigration, and then introduce ways of influencing current density during the physical design of an electronic circuit. Although the observations mainly concern analog circuits or power supply lines in digital circuits, they are also of relevance for most of today s digital designs. 2. THE ELECTROMIGRATION PROCESS Current flow through a conductor produces two forces to which the individual metal ions in the conductor are exposed. The first is an electrostatic force F field caused by the electric field strength in the metallic interconnect. Since the positive metal ions are to some extent shielded by the negative electrons in the conductor, this force can be ignored in most cases. The second force F wind is generated by the momentum transfer between conduction electrons and metal ions in the crystal lattice. This force works in the direction of the current flow and is the main cause of electromigration. Force on metal ions resulting from momentum transfer from the conduction electrons Anode + F wind << F field Al + Interaction of electric field on metal ions Cathode Figure 2. Two forces are acting on metal ions which make up the lattice of the interconnect material. Electromigration is the result of the dominant force, i.e. the momentum transfer from the electrons which move in the applied electric field. In a homogeneous crystalline structure, because of the uniform lattice structure of the metal ions, there is hardly any momentum transfer between the conduction electrons and the metal ions. However, this symmetry does not exist at the grain boundaries and material interfaces, and so here momentum is transferred much more vigorously from the conductor electrons to the metal ions. Since the metal ions in these regions are bonded much more weakly than in a regular crystal lattice, once the electron wind has reached a certain strength, atoms become separated from the grain boundaries and are transported in the direction of the current. This direction is also influenced by the grain boundary itself, because atoms tend to move along grain boundaries. E If the current direction of an excessive current is kept constant over an extended period of time, voids and hillocks appear in the wire. For this reason, analog circuits or power supply lines in digital circuits are particularly susceptible to the effects of electromigration. When the current direction varies, for example in digital circuits with their alternating capacitive charging and discharging in conductors, there is a certain amount of compensation due to a material flow back (selfhealing effect). Nonetheless, interconnect failures are still possible, with thermal migration playing a major role. Furthermore, the susceptibility of wires to electromigration depends on grain size and thus on the distribution of grain sizes. Smaller grains encourage material transport, because there are more transport channels than in coarsegrained material. The result of this is that voids tend to appear at the points of transition from coarse to fine grains, since at these points atoms flow out faster than they flow in. Conversely, where the structure turns from fine grains to coarse, hillocks tend to form, since the inflowing atoms cannot disperse fast enough through the coarse structure. These sorts of variations in grain size appear in interconnects at every contact hole or via. Because the current here commonly encounters a narrowing of the conductive pathway, contact holes and vias are particularly susceptible to electromigration. Diffusion processes caused by electromigration can be divided into grain boundary diffusion, bulk diffusion and surface diffusion (Figure 3). In general, grain boundary diffusion is the major migration process in aluminum wires [5][7], whereas surface diffusion is dominant in copper interconnects [4][6][8][9]. (c) (a) Figure 3. Illustration of various diffusion processes within the lattice of an interconnect: (a) grain boundary diffusion, (b) bulk diffusion, and (c) surface diffusion. Detailed investigations of the various failure mechanisms of electromigration can be found in [2] [5]. 3. DESIGN CONSTRAINTS AFFECTING ELECTROMIGRATION 3.1 Wire Material It is known that pure copper used for Cumetallization is more electromigrationrobust than aluminum. Copper wires can withstand approximately five times more current density than aluminum wires while assuming similar reliability requirements. This is mainly due to the higher electromigration activation energy levels of copper caused by its superior electrical and thermal conductivity as well as its higher melting point [4][6]. Alternatively, the Almetallization material can be alloyed with small amounts of copper and silicon (AlSiCu) in order to reduce (b)

3 the migration effect by increasing its electromigration activation energy as well [5][7]. Furthermore, a good selection and deposition of the passivation over the metal interconnect reduces electromigration damage by limiting extrusions and suppressing surface diffusion. 3.2 Wire Temperature In Equation (1), the temperature of the conductor appears in the exponent, i.e. it strongly affects the MTTF of the interconnect. The temperature of the interconnect is mainly a result of the chip environment temperature, the selfheating effect of the current flow, the heat of the neighboring interconnects or transistors, and the thermal conductivity of the surrounding materials. The following example demonstrates the significance of thermal conductivity: While conventional household copper wires would melt at current densities of over 10 4 A/cm 2, a silicon chip can tolerate current densities up to A/cm 2 without the wire melting [10]. What is responsible for this is the significantly higher thermal conductivity of the silicon substrate. (So the limiting factor in chip wiring is no longer the melting point, but the occurrence of electromigration.) There is a further, often overlooked connection between the temperature of a conductor and the current density: In Equation (1), the temperature T is on the same side as current density J. For an interconnect to remain reliable in rising temperatures, the maximum tolerable current density of the conductor must necessarily decrease. Figure 4 shows the relationship between maximum current density and temperature, as demonstrated by the constant reliability of the aluminum wiring in Equation (1). It becomes clear, that for example when the working temperature of an interconnect is raised from 25ºC (77ºF) to 125ºC (257ºF), the maximum tolerable current density is reduced by about 90%. J max (T) / J max (T = 25 C) ,1 0,01 J max (T) compared to J max (T ref = 25 C) [1] Consumer Electronics Figure 4. The maximum permissible current density of an aluminum metallization, calculated at e.g. 25 C, is reduced significantly when the temperature of the interconnect rises. 3.3 Wire Size and Metal Slotting Temperature T [Celsius] Automotive Electronics As Equation (1) shows, apart from the temperature, it is the current density that constitutes the main parameter affecting the MTTF of a wire. Since the current density is obtained as the ratio of current I and crosssectional area A, and since most process technologies assume a constant thickness of the printed interconnects, it is the wire width that exerts a direct influence on current density: The wider the wire, the smaller the current density and the greater the resistance to electromigration. However, there is an exception to this accepted wisdom: If you reduce wire width to below the average grain size of the wire material, the resistance to electromigration increases, despite an increase in current density. This apparent contradiction is caused by the position of the grain boundaries, which in such narrow wires as in a bamboo structure lie perpendicular to the width of the whole wire (Figure 5). As we have already mentioned, material transport occurs as much in the direction of the current flow as along the grain boundaries (socalled grain boundary diffusion). Because the grain boundaries in this type of bamboo structure are at right angles to the current flow, the boundary diffusion factor is excluded, and material transport is correspondingly reduced. Reliability MTTF [h] w < Grains (Bamboo Wires) w MTTF_min Grain Boundaries I = constant T = constant Wire Width w [µm] Figure 5. Reduced wire width below the average grain size increases the reliability of the wire with regard to electromigration. Socalled bamboo wires are characterized by grain boundaries which lie perpendicular to the direction of the electron wind and thus permit only limited grain boundary diffusion. So the bamboo structure increases reliability, and in order to exploit this, wire widths are deliberately kept so narrow that a bamboo structure is maintained; also, the wire material can be selectively annealed during IC processing in order to support bamboo formation. However, the maximum wire width possible for a bamboo structure is usually too narrow for signal lines of largemagnitude currents in analog circuits or for power supply lines. In these circumstances, slotted wires are often used, whereby rectangular holes are carved in the wires. Here, the widths of the individual metal structures in between the slots lie within the area of a bamboo structure, while the resulting total width of all the metal structures meets power requirements. On the same principle, often a finegrain power mesh is laid over the circuit. Because it has so many wires, their individual widths are within the area of a bamboo structure. It is also noteworthy that process variations play an important role in variations of wire widths (e.g. etch loss, lithography issues) and of wire heights (e.g. variations of metal deposition) as well as affecting the via fill rate. Hence, related worstcase process w

4 variations must always be considered to establish reliable interconnect dimensions. Metal1 I 3.4 Wire Length There is also a lower limit for the length of the interconnect that will allow electromigration to occur. It is known as Blech length, and any wire that has a length below this limit (typically in the order of µm) will not fail by electromigration. Here, a mechanical stress buildup causes a reversed migration process which reduces or even compensates the effective material flow towards the anode (Figure 6). Specifically, a conductor line is not susceptible to electromigration if the product of the wire s current density J and the wire length l is smaller than a processtechnologydependent threshold value (J l) threshold [3]. Metal1 I Metal2 Metal2 Current Density (150 Celsius) min max R Sheet (Metal1) > R Sheet (Metal2) F N1 F N2 F N3 F N4 F N5 Al+Al+ Al+ Al+ Al+ + Al+ Electromigration (EM) Stress Migration (SM) F N1 F N2 F N3 F N4 F N5 Al+ Al+ Al+ Al+ Al+ Al+ Al+ + F N1 F N2 F N3 F N4 F N5 Figure 7. Currentdensity distribution within various vias of a via array. In the upper example, the lower left via is overloaded while the upper right vias hardly carry any current at all. A better arrangement is presented below. Attention must also be paid to bends in interconnects. In particular, 90degree corner bends must be avoided, since the current density in such bends is significantly higher than that in oblique angles of, for example, 135 degrees (Figure 8). Equilibrium between EM and SM if l wire < Blech length Al+ Al+ Al+ Al+ Al+ + Al+ Figure 6. An illustration of stress migration caused by the hillock area in a short wire. This reversed migration process essentially compensates the material flow due to electromigration. The Blech length must be considered when designing test structures for electromigration. Due to various implementation problems, exploiting this compensation effect in order to generate socalled immortal wires has shown only limited applicability in realworld circuits so far. 3.5 Via Arrangements and Corner Bends Particular attention must be paid to vias and contact holes, because generally the ampacity of a (tungsten) via is less than that of a metal wire of the same width. Hence multiple vias are often used, whereby the geometry of the via array is very significant: Multiple vias must be organized such that the resulting current flow is distributed as evenly as possible through all the vias (Figure 7). The socalled Reservoir effect [11] can be utilized to significantly improve the via array lifetime. Here, increased metalvia layer overlaps enlarge the material reservoir in the via. (a) Figure 8. Currentdensity visualization of different corner bend angles of (a) 90, (b) 135, and (c) Terminal Connections Analog terminals (pins) are distinguished by a great variety of shapes and sizes. When connecting such a terminal to a wire, designers must bear in mind that different connection positions of a wire to this terminal can cause different current loads within the terminal structure. For this reason, a current density verification should include not only the interconnects, but also all terminal structures. While designing the interconnects (the routing step), it is advisable to determine the ampacities of the various terminal regions (Figure 9) and compare them with the maximum current of the wire(s) reaching the terminal. The terminal areas of ampacity below the expected maximum wire current should then be eliminated as candidates for circuit connections. (b) min. (c) max.

5 4.2 Terminal Currents Figure 9. Terminal regions of a Ushaped pin consisting of one metallization layer. Currentdensity correct terminal connections require the verification of all terminal regions with regard to their maximum permissible currents and a subsequent consideration of these values when connecting the wire(s) to the terminal. 4. CURRENT CONSIDERATIONS 4.1 Current Models 2 ma 0.5 ma 3 ma 2 ma 0.5 ma As we mentioned already, the current waveform and the electromigrationrobustness of the interconnect are closely related. Studies (such as in [12] [15]) show an increased electromigrationrobustness of the interconnect for bidirectional and pulsed current stress compared to single direction current and constant current stress. One of the reasons for this dependency is the socalled selfhealing effect due a material flow back caused by alternating current directions, which reduces the effective material migration [12][13]. When considering terminal and wire currents in an electromigrationaware design flow, various models are applied based on the frequency of the current flow: (1) the effective current model based on the rootmeansquare value of the currents (RMS currents) for frequencies smaller than 1 Hz, (2) the average current model for frequencies greater than 1 Hz, and (3) the peak current model which considers ESD (electrostatic discharge) events. The RMScurrentbased does not take into account the selfhealing effect. This model represents a more conservative approach and so it is suitable for all analog DC nets and reliabilitycritical applications in general. The averagecurrentbased model considers the selfhealing effect of alternating current directions. It is commonly applied to current flows within digital signal nets. A peakcurrent flow (such as shorttime current flows due to an ESD event) has to be considered separately from RMS or averagecurrentbased models. This is due to different damaging effects within the metallization resulting in different design rules for conductor dimensioning. A problem for any electromigrationaware physical design methodology is the determination of realistic current values for each net terminal. Extensive studies have been conducted to address this issue (such as in [12] [15]). Most approaches use a single socalled equivalent current value per terminal by considering the current waveform, duty cycle and frequency. However, single current values are not sufficient in order to calculate currents in various Steiner point connections. For example, a current value propagation problem arises within a Steiner point if two connected net terminals are characterized by reversed worst case currents flows. We suggest two current value models that are capable of resolving the above mentioned current value propagation problem by utilizing either a single current value pair or a vector of current value pairs. In our first current value model, the results from one or more simulations are postprocessed by calculating a set of current vectors satisfying Kirchhoff s current law. They represent a snapshot of the circuits operation at the time of minimum and maximum currents at each terminal (Figure 10). This reduces the simulation results to a vector of worst case current value ranges. For a net with m terminals, this may lead to up to m current value pairs (i.e. 2m current values) attached to each terminal i terminal : i terminal = [[i i_min(terminal_1), i i_max(terminal_1) ], [i i_min(terminal_2), i i_max(terminal_2) ], [i i_min(terminal_m), i i_max(terminal_m) ]], (e.g. i terminal = [[0.5mA, 1.8mA], [0, +0.4mA],..., [0.2mA, 0]]). T1 ( 0.5 ma/1.8 ma / ma / 0.4 ma /...) T3 (0.4 ma /0.4 ma/ ma / 0.5 ma /...) 2 T2 (0.4 ma/0.7 ma/ 0.8 ma /0.9 ma /...) T4 (0.3 ma / 0.4 ma/ ma/1.2 ma/...) T5 (0.8 ma/ 0.3 ma / ma / 0.5 ma /...) Currents attached to terminal T 1 T 1 T 2 T 3...T m t 1_min t 1_max t 2_min t 2_max : <2m> : Current vector at time t terminal_1_max Figure 10. An illustration of the first approach utilizing current vectors. Current values assigned to terminals are their respective minimum and maximum values (shown in italic) and the current values at the other terminals minimum and maximum points of time. Every current vector satisfies Kirchhoff s current law, i.e., its current sum is zero. The second approach uses a vector with one current value pair for each of n time slots S x (x = 1 n). The minimum and maximum current values of a current value pair are determined between the start and end time of the particular time slot. The current values are obtained either by circuit simulation, by manual

6 attachment to the net terminal in the schematic, or determined from a device library. This model accounts for independent current flow events originated from multiple net terminals. i terminal = [[S 1, i min_1, i max_1 ], [S 2, i min_2, i max_2 ],, [S n, i min_n, i max_n ]] (e.g. i terminal = [[S 1, 1mA, +3mA], [S 2, +2mA, +3mA], ]). 5. ELECTROMIGRATIONAWARE DESIGN FLOW We propose an electromigrationaware physical design flow that has been implemented and verified in a commercial design environment tailored to analog and mixedsignal ICs for automotive applications [16] [18]. This flow includes three modules that have been specifically developed to address electromigrationrelevant physical design constraints: currentdriven routing, currentdensity verification, and currentdriven layout decompaction (Figure 11). Start Circuit Simulation Schematic Finally, currentdriven layout decompaction performs a postroute adjustment of layout segments with currentdensity violations and inhomogeneous current flows, respectively. Currentdriven decompaction has been shown to be an effective point tool when addressing currentdensityrelated violations without invoking a repetition of the entire place and route cycle. 5.1 CurrentDriven Routing A currentdriven routing procedure consists of three basic steps: (1) wire planning comprising net topology planning and terminal connection checking, (2) calculation of required wire and via array dimensions, and (3) final routing of the pointtopointconnections utilizing a detailed router. The major challenge facing any currentdriven signal routing is the inherent feature that segment currents are only known after the entire topology of the net has been laid out. In other words, currents strengths are altered in a previously routed subnet whenever a new terminal is linked to the net (Figure 12). However, segment currents should be considered when deciding the routing sequence of net segments. To address this cyclic conflict, a wire planning step is introduced. Its major characteristic is concurrent net topology planning and segment current calculation. Physical Design Partitioning + Floorplanning Placement 2 ma T 3 4 ma CurrentDriven Routing CurrentDensity Verification EM Violations No Electromigration Robust Design Yes CurrentDriven Layout Decompaction Figure 11. Our electromigrationaware analog and mixedsignal design flow includes currentdriven routing, verification and layout decompaction tools intended for an electromigrationrobust IC layout. Currentdriven routing ensures that the widths of all automatically routed interconnect structures are laid out correctly to fulfill all predefined electromigration and ESD reliability requirements. The subsequently applied currentdensity verification tool automatically checks current densities within all layout segments, including arbitrarily shaped terminal and routing fragments and any manually routed interconnects. It also verifies the homogeneity of the current flow. (Homogeneity can be achieved during routing only to a certain level. This is due to the effects of the sequential character of any routing procedure as well as the limited capabilities of global interconnect planning. An inhomogeneous current flow favors the occurrence of electromigration.) 2 ma T 3 T 4 T 2 3 ma 4 ma T 1 T 4 2 ma T 3 T 4 2 ma Figure 12. Illustration of the cyclic conflict whereby the sequence of all terminals to be connected must be known in order to allow for a current calculation within net segments. At the same time, laying out the sequence of connections requires currents to be known in order to fulfill certain optimization criteria. (Single terminal current values instead of boundary current values are used here for simplicity.) During wire planning, a currentdriven net topology is determined by calculating an optimized routing tree. Its major optimization goal is a minimization of the interconnect area (rather than simple length minimization), i.e. currentintensive segments are kept as short as possible. At the same time, the currentstrength capabilities of net terminals to be connected have to be verified (Section 3.6). T 2 3 ma T 2 3 ma T 1 3 ma 4 ma T 1 2 ma requires Complete net topology... Current flow within net segments requires

### Defects Introduction. Bonding + Structure + Defects. Properties

Defects Introduction Bonding + Structure + Defects Properties The processing determines the defects Composition Bonding type Structure of Crystalline Processing factors Defects Microstructure Types of

### Chapter Outline Dislocations and Strengthening Mechanisms

Chapter Outline Dislocations and Strengthening Mechanisms What is happening in material during plastic deformation? Dislocations and Plastic Deformation Motion of dislocations in response to stress Slip

### Electro-Migration Model Parameters Sensitivity Analysis Based on the Monte Carlo Method

A publication of CHEMICAL ENGINEERING TRANSACTIONS VOL. 33, 2013 Guest Editors: Enrico Zio, Piero Baraldi Copyright 2013, AIDIC Servizi S.r.l., ISBN 978-88-95608-24-2; ISSN 1974-9791 The Italian Association

### Digital VLSI design. Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips

Digital VLSI design Lecture 2: Complementary Metal Oxide Semiconductor (CMOS) Chips What will we learn? How integrated circuits work How to design chips with millions of transistors Ways of managing the

### THE WAY TO SOMEWHERE. Sub-topics. Diffusion Diffusion processes in industry

THE WAY TO SOMEWHERE Sub-topics 1 Diffusion Diffusion processes in industry RATE PROCESSES IN SOLIDS At any temperature different from absolute zero all atoms, irrespective of their state of aggregation

### Lecture 22: Integrated circuit fabrication

Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................

### Matching of Resistors and Capacitors

Matching of Resistors and Capacitors Group Leader Jepsy Asim Bob Sandra Shawn Measuring Mismatch The mismatch between any two devices is expressed as a deviation of the measured device ratio from the intended

### Circuit and System Representation. IC Designers must juggle several different problems

Circuit and System Representation IC Designers must juggle several different problems Multiple levels of abstraction IC designs requires refining an idea through many levels of detail, specification ->

### Stress-Induced Voiding in Dual-Damascene Cu Interconnects

Term paper for EM 397: Thin Film Mechanics Fall 2006 Stress-Induced Voiding in Dual-Damascene Cu Interconnects Abstract Stress-induced voiding (SIV) is investigated in Cu-based, deep-submicron, dual damascene

### LED Display Backlighting Monitor Applications using 6-lead MULTILED Application Note

LED Display Backlighting Monitor Applications using 6-lead MULTILED Application Note Abstract This application note describes two reference designs for LCD backlighting using the 6-lead MULTILED LRTB G6SG

### Current and Temperature Ratings

Document 361-1 Current and Temperature Ratings Introduction This application note describes: How to interpret Coilcraft inductor current and temperature ratings Our current ratings measurement method and

### StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs

White Paper StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs May 2010 Krishnakumar Sundaresan Principal Engineer and CAE Manager, Synopsys Inc Executive Summary IC

### Basic Properties and Application Examples of PGS Graphite Sheet

Basic Properties and Application Examples of 1. Basic properties of Graphite sheet 2. Functions of Graphite sheet 3. Application Examples Presentation [Sales Liaison] Panasonic Electronic Devices Co.,

### AORC Technical meeting 2014

http : //www.cigre.org B1-196 AORC Technical meeting 214 Evaluation of Insulating Materials for HVDC Transmission Cable using Space Charge Measurement Y. TANAKA Tokyo City University Japan SUMMARY Some

### 4 SENSORS. Example. A force of 1 N is exerted on a PZT5A disc of diameter 10 mm and thickness 1 mm. The resulting mechanical stress is:

4 SENSORS The modern technical world demands the availability of sensors to measure and convert a variety of physical quantities into electrical signals. These signals can then be fed into data processing

### Lecture: 33. Solidification of Weld Metal

Lecture: 33 Solidification of Weld Metal This chapter presents common solidification mechanisms observed in weld metal and different modes of solidification. Influence of welding speed and heat input on

### Discontinued. LUXEON V Portable. power light source. Introduction

Preliminary Technical Datasheet DS40 power light source LUXEON V Portable Introduction LUXEON is a revolutionary, energy efficient and ultra compact new light source, combining the lifetime and reliability

### 3. Diodes and Diode Circuits. 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1

3. Diodes and Diode Circuits 3. Diodes and Diode Circuits TLT-8016 Basic Analog Circuits 2005/2006 1 3.1 Diode Characteristics Small-Signal Diodes Diode: a semiconductor device, which conduct the current

### Designing Your PCB for High Reliability. John Isaac Director of Market Development Systems Design Division

Designing Your PCB for High Reliability John Isaac Director of Market Development Systems Design Division Reliability What Makes Electronic Systems Fail? Heat Vibration Electromagnetic interference PCB

### Chapter Outline Dislocations and Strengthening Mechanisms

Chapter Outline Dislocations and Strengthening Mechanisms What is happening in material during plastic deformation? Dislocations and Plastic Deformation Motion of dislocations in response to stress Slip

### Electrolytic Electromigration of Metallic Material and Silver Filled Epoxy

Electrolytic Electromigration of Metallic Material and Silver Filled Epoxy Electrolytic Electromigration Basics The most common electrolytic electromigration process in modern electronics is that associated

### Motor-CAD Software for Thermal Analysis of Electrical Motors - Links to Electromagnetic and Drive Simulation Models

Motor-CAD Software for Thermal Analysis of Electrical Motors - Links to Electromagnetic and Drive Simulation Models Dave Staton, Douglas Hawkins and Mircea Popescu Motor Design Ltd., Ellesmere, Shropshire,

### Thermal Modeling Methodology for Fast and Accurate System-Level Analysis: Application to a Memory-on-Logic 3D Circuit

Thermal Modeling Methodology for Fast and Accurate System-Level Analysis: Application to a Memory-on-Logic 3D Circuit Cristiano Santos 1,2, Pascal Vivet 1, Philippe Garrault 3, Nicolas Peltier 3, Sylvian

### Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

Introduction to VLSI Fabrication Technologies Emanuele Baravelli 27/09/2005 Organization Materials Used in VLSI Fabrication VLSI Fabrication Technologies Overview of Fabrication Methods Device simulation

### High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures

High Open Circuit Voltage of MQW Amorphous Silicon Photovoltaic Structures ARGYRIOS C. VARONIDES Physics and EE Department University of Scranton 800 Linden Street, Scranton PA, 18510 United States Abstract:

### Electrostatic Discharge (ESD)

Electrostatic Discharge (ESD) ELEC 353 Electronics II Instructor: Prof. C. Saavedra What is ESD? A sudden current flow between two objects that are at different potentials ESD currents are large and of

### Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron

### Sheet Resistance = R (L/W) = R N ------------------ L

Sheet Resistance Rewrite the resistance equation to separate (L / W), the length-to-width ratio... which is the number of squares N from R, the sheet resistance = (σ n t) - R L = -----------------------

### Thermal Management in Surface-Mounted Resistor Applications

VISHAY BEYSCHLAG Resistive Products 1. INTRODUCTION Thermal management is becoming more important as the density of electronic components in modern printed circuit boards (PCBs), as well as the applied

### Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE 6450 - Dr. Alan Doolittle

Lecture 12 Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12 Evaporation and Sputtering (Metalization) Evaporation For all devices, there is a need to go from semiconductor to metal.

### Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,

### Implementation Of High-k/Metal Gates In High-Volume Manufacturing

White Paper Implementation Of High-k/Metal Gates In High-Volume Manufacturing INTRODUCTION There have been significant breakthroughs in IC technology in the past decade. The upper interconnect layers of

### CFD Based Air Flow and Contamination Modeling of Subway Stations

CFD Based Air Flow and Contamination Modeling of Subway Stations Greg Byrne Center for Nonlinear Science, Georgia Institute of Technology Fernando Camelli Center for Computational Fluid Dynamics, George

### INJECTION MOLDING COOLING TIME REDUCTION AND THERMAL STRESS ANALYSIS

INJECTION MOLDING COOLING TIME REDUCTION AND THERMAL STRESS ANALYSIS Tom Kimerling University of Massachusetts, Amherst MIE 605 Finite Element Analysis Spring 2002 ABSTRACT A FEA transient thermal structural

### Development of High-Speed High-Precision Cooling Plate

Hironori Akiba Satoshi Fukuhara Ken-ichi Bandou Hidetoshi Fukuda As the thinning of semiconductor device progresses more remarkably than before, uniformity within silicon wafer comes to be strongly required

### slip lines which are close to, but not coincident with, the slip lines formed in

FATIGUE CRACK NUCLEATION IN AIETALS* BY T. II. LIN ANI) Y. A11. ITO UNIVERSITY OF CALIFORNIA (LOS ANGELES) Communicated by T'. Y. Thomas, December 18, 1968 Abstract. One of the unanswered questions in

### Accelerometer and Gyroscope Design Guidelines

Application Note Accelerometer and Gyroscope Design Guidelines PURPOSE AND SCOPE This document provides high-level placement and layout guidelines for InvenSense MotionTracking devices. Every sensor has

### MOLECULAR DYNAMICS INVESTIGATION OF DEFORMATION RESPONSE OF THIN-FILM METALLIC NANOSTRUCTURES UNDER HEATING

NANOSYSTEMS: PHYSICS, CHEMISTRY, MATHEMATICS, 2011, 2 (2), P. 76 83 UDC 538.97 MOLECULAR DYNAMICS INVESTIGATION OF DEFORMATION RESPONSE OF THIN-FILM METALLIC NANOSTRUCTURES UNDER HEATING I. S. Konovalenko

### Chapter 3 Fabrication of CMOS Integrated Circuits. Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan

Chapter 3 Fabrication of CMOS Integrated Circuits Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Background The CMOS Process Flow Latchup Antenna Rules

### SPACE CHARGE ACCUMULATION UNDER THE EFFECTS OF TEMPERATURE GRADIENT ON SOLID DIELECTRIC DC CABLE

ISBN 978--658-9 Proceedings of the 6 th International Symposium on High Voltage Engineering Copyright c 9 SAIEE, Innes House, Johannesburg SPACE CHARGE ACCUMULATION UNDER THE EFFECTS OF TEMPERATURE GRADIENT

### LUXEON LEDs. Circuit Design and Layout Practices to Minimize Electrical Stress. Introduction. Scope LED PORTFOLIO

LED PORTFOLIO LUXEON LEDs Circuit Design and Layout Practices to Minimize Electrical Stress Introduction LED circuits operating in the real world can be subjected to various abnormal electrical overstress

### Outline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. 4th Ed.

Lecture 14: Wires Outline Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters 2 Introduction Chips are mostly made of wires called interconnect

### COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL DESIGN. (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida)

COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL DESIGN Chetan Sharma & Shobhit Jaiswal 2 (M.Tech-VLSI Department, JSS Academy of Technical Education, Noida) ( chetan202@gmail.com ) & 2 ( jaiswalshobhit9@gmail.com

### The atomic packing factor is defined as the ratio of sphere volume to the total unit cell volume, or APF = V S V C. = 2(sphere volume) = 2 = V C = 4R

3.5 Show that the atomic packing factor for BCC is 0.68. The atomic packing factor is defined as the ratio of sphere volume to the total unit cell volume, or APF = V S V C Since there are two spheres associated

### Pulsed Over Current Driving of Cree XLamp LEDs: Information and Cautions

Pulsed Over Current Driving of Cree XLamp LEDs: Information and Cautions Application Note CLD-AP6 rev 1B Table of contents Introduction...1 Single pulse over current events...2 Repetitive pulsing...3 Ripple

### 08. Printed Circuit Board (PCB)

08. Printed Circuit Board (PCB) Bei Yu Reference: Chapter 5 of Ground Planes and Layer Stacking High speed digital design by Johnson and Graham 1 Introduction What is a PCB Why we need one? For large scale

### Development of New Inkjet Head Applying MEMS Technology and Thin Film Actuator

Development of New Inkjet Head Applying MEMS Technology and Thin Film Actuator Kenji MAWATARI, Koich SAMESHIMA, Mitsuyoshi MIYAI, Shinya MATSUDA Abstract We developed a new inkjet head by applying MEMS

### Silicon-On-Glass MEMS. Design. Handbook

Silicon-On-Glass MEMS Design Handbook A Process Module for a Multi-User Service Program A Michigan Nanofabrication Facility process at the University of Michigan March 2007 TABLE OF CONTENTS Chapter 1...

### AN3022. Establishing the Minimum Reverse Bias for a PIN Diode in a High-Power Switch. 1. Introduction. Rev. V2

Abstract - An important circuit design parameter in a high-power p-i-n diode application is the selection of an appropriate applied dc reverse bias voltage. Until now, this important circuit parameter

### Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., Given at CMSE, Portsmouth 2008

Shrinking Silicon Feature Sizes Consequences for Reliability Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., www.micross.com Given at CMSE, Portsmouth 2008 1 The

### 1150 hp motor design, electromagnetic and thermal analysis

115 hp motor design, electromagnetic and thermal analysis Qasim Al Akayshee 1, and David A Staton 2 1 Mawdsley s Ltd., The Perry Centre, Davey Close, Waterwells, Gloucester GL2 4AD phone: +44 1452 888311

### Ampacity simulation of a high voltage cable to connecting off shore wind farms

Ampacity simulation of a high voltage cable to connecting off shore wind farms Eva Pelster 1, Dr. David Wenger 1 1 Wenger Engineering GmbH, Einsteinstr. 55, 89077 Ulm, mail@wenger-engineering.com Abstract:

### MIT 2.810 Manufacturing Processes and Systems. Homework 6 Solutions. Casting. October 15, 2015. Figure 1: Casting defects

MIT 2.810 Manufacturing Processes and Systems Casting October 15, 2015 Problem 1. Casting defects. (a) Figure 1 shows various defects and discontinuities in cast products. Review each one and offer solutions

### Avoiding AC Capacitor Failures in Large UPS Systems

Avoiding AC Capacitor Failures in Large UPS Systems White Paper #60 Revision 0 Executive Summary Most AC power capacitor failures experienced in large UPS systems are avoidable. Capacitor failures can

### Thermal Diffusivity, Specific Heat, and Thermal Conductivity of Aluminum Oxide and Pyroceram 9606

Report on the Thermal Diffusivity, Specific Heat, and Thermal Conductivity of Aluminum Oxide and Pyroceram 9606 This report presents the results of phenol diffusivity, specific heat and calculated thermal

### A8 Thermal properties of materials

A8 Thermal properties of materials Thermal properties the melting temperature, T m, and the glass temperature (temperatura de transição vítrea), T g, relate directly to the strength of the bonds in the

### Introduction To Materials Science FOR ENGINEERS, Ch. 5. Diffusion. MSE 201 Callister Chapter 5

Diffusion MSE 21 Callister Chapter 5 1 Goals: Diffusion - how do atoms move through solids? Fundamental concepts and language Diffusion mechanisms Vacancy diffusion Interstitial diffusion Impurities Diffusion

### Layout, Fabrication, and Elementary Logic Design

Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design Adapted from Weste & Harris CMOS VLSI Design Overview Implementing switches with CMOS transistors How to compute logic

### Chapter 16. Diodes and Applications. Objectives

Chapter 16 Diodes and Applications Objectives Understand the basic structure of semiconductors and how they conduct current Describe the characteristics and biasing of a pn junction diode Describe the

### Efficient Meshing in Sonnet

100 Elwood Davis Road North Syracuse, NY 13212 USA Efficient Meshing in Sonnet Volker Mühlhaus Dr. Mühlhaus Consulting & Software GmbH 2008 Sonnet Software, Inc. Sonnet is a registered trademark of Sonnet

### Yrd. Doç. Dr. Aytaç Gören

H2 - AC to DC Yrd. Doç. Dr. Aytaç Gören ELK 2018 - Contents W01 Basic Concepts in Electronics W02 AC to DC Conversion W03 Analysis of DC Circuits W04 Transistors and Applications (H-Bridge) W05 Op Amps

### Reliability Data. Introduction. Index. Reliability Datasheet RD07

Reliability Datasheet RD07 LUXEON Rebel Reliability Data Introduction This reliability datasheet summarizes the reliability performance of LUXEON Rebel. Overall product reliability depends on the customer's

### Metallization ( Part 2 )

1 Metallization ( Part 2 ) Chapter 12 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra TFE4180 Semiconductor Manufacturing Technology, Norwegian University of Science and

### Chapter 2. MOS Transistors. 2.1 Structure of MOS transistors

Chapter 2 MOS Transistors 2.1 Structure of MOS transistors We will discuss the structure of two MOS Field-Effect-Transistors (FETs) that are building blocks for all digital devices. The nmos transistor

### A Study of a MV Cable Joint

SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 7, No. 1, May 2010, 1-11 UDK: 621.315.35:537.212 A Study of a MV Cable Joint Radiša Dimitrijević 1, Neda Pekarić-Nađ 2, Miodrag Milutinov 3 Abstract: Construction

### Cree TR2227 LEDs Data Sheet CxxxTR2227-Sxx00

Cree TR2227 LEDs Data Sheet CxxxTR2227-Sxx00 Cree s TR LEDs are the newest generation of solid-state LED emitters that combine highly efficient InGaN materials with Cree s proprietary device technology

### USING MERCURY PROBES TO CHARACTERIZE USJ LAYERS

USING MERCURY PROBES TO CHARACTERIZE USJ LAYERS James T.C. Chen and Wei Liu Four Dimensions, Inc. Hayward, CA 94545 It is well established that uniformity and dosage of drain-source ion implantation on

### Transient electrical thermal analysis of ESD process using 3-D finite element method.

Title Transient electrical thermal analysis of ESD process using 3-D finite element method Author(s) Hou, Yuejin; Tan, Cher Ming Citation Hou, Y., & Tan, C. M. (2009). Transient electrical thermal analysis

### TR3547M LEDs CxxxTR3547M-Sxx00

Data Sheet: CPR3FL Rev. - TR3547M LEDs CxxxTR3547M-Sxx Data Sheet Cree s TR3547M LEDs are the next generation of solid-state LED emitters that combine highly efficient InGaN materials with Cree s proprietary

### 3D Power Inductor: Calculation of Iron Core Losses

3D Power Inductor: Calculation of Iron Core Losses L. Havez*, E. Sarraute, Y. Lefevre LAPLACE Laboratory/INPT-ENSEEIHT, Electrical and Automation Engineering, * 2 Rue Charles Camichel, Toulouse, FRANCE

### Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation

Datasheet Create a Better Starting Point for Faster Physical Implementation Overview Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical delivers superior quality

### EFFECT OF OBSTRUCTION NEAR FAN INLET ON FAN HEAT SINK PERFORMANCE

EFFECT OF OBSTRUCTION NEAR FAN INLET ON FAN HEAT SINK PERFORMANCE Vivek Khaire, Dr. Avijit Goswami Applied Thermal Technologies India 3rd Floor,C-Wing,Kapil Towers, Dr. Ambedkar Road, Pune- 411 1 Maharashtra,

### Flex Circuit Design and Manufacture.

Flex Circuit Design and Manufacture. Hawarden Industrial Park, Manor Lane, Deeside, Flintshire, CH5 3QZ Tel 01244 520510 Fax 01244 520721 Sales@merlincircuit.co.uk www.merlincircuit.co.uk Flex Circuit

### Making of a Chip Illustrations

Making of a Chip Illustrations 22nm 3D/Trigate Transistors Version January 2012 1 The illustrations on the following foils are low resolution images that visually support the explanations of the individual

### Investigations of interfacial features in thick Al wire bonds

Investigations of interfacial features in thick Al wire bonds G. Khatibi a,, B. Weiss a, J. Bernardi b, S. Schwarz b a) University of Vienna, Faculty of Physics b) Vienna University of Technology, USTEM

### Differential and bidirectional differential pressure sensors, taking AMS 5812 as an example

In pressure sensor technology there is a difference between various physical methods of measurement, depending on the application. These include the measurement of absolute pressure, relative pressure,

### Analysis of Blind Microvias Forming Process in Multilayer Printed Circuit Boards

POLAND XXXII International Conference of IMAPS - CPMT IEEE Poland Pułtusk - 4 September 008 Analysis of Blind Microvias Forming Process in Multilayer Printed Circuit Boards Janusz Borecki ), Jan Felba

### Lecture 19: Solar cells

Lecture 19: Solar cells Contents 1 Introduction 1 2 Solar spectrum 2 3 Solar cell working principle 3 4 Solar cell I-V characteristics 7 5 Solar cell materials and efficiency 10 1 Introduction Solar cells

### Chapter Outline. Diffusion - how do atoms move through solids?

Chapter Outline iffusion - how do atoms move through solids? iffusion mechanisms Vacancy diffusion Interstitial diffusion Impurities The mathematics of diffusion Steady-state diffusion (Fick s first law)

### Simulation of EMI in Hybrid Cabling for Combining Power and Control Signaling

Simulation of EMI in Hybrid Cabling for Combining Power and Control Signaling Outline Motivation Hybrid cable design Cable parameters, impedance EMI and screening Connector modeling Cascaded analysis Transient

### TR3547 LEDs CxxxTR3547-Sxx00

TR3547 LEDs CxxxTR3547-Sxx Data Sheet Cree s TR3547 LEDs are the next generation of solid-state LED emitters that combine highly efficient InGaN materials with Cree s proprietary device technology and

### Interconnections: Aluminum Metallization

Spring 2003 Interconnections: Aluminum Metallization Advances in the multilevel interconnect technology 70 s Poly-Si Aluminum 80 s Local planarization Aluminum alloys Silicide contacts Polycide gates 90

### Three Channel Optical Incremental Encoder Modules Technical Data

Three Channel Optical Incremental Encoder Modules Technical Data HEDS-9040 HEDS-9140 Features Two Channel Quadrature Output with Index Pulse Resolution Up to 2000 CPR Counts Per Revolution Low Cost Easy

### Modern Construction Materials Prof. Ravindra Gettu Department of Civil Engineering Indian Institute of Technology, Madras

Modern Construction Materials Prof. Ravindra Gettu Department of Civil Engineering Indian Institute of Technology, Madras Module - 2 Lecture - 2 Part 2 of 2 Review of Atomic Bonding II We will continue

### Solid shape molding is not desired in injection molding due to following reasons.

PLASTICS PART DESIGN and MOULDABILITY Injection molding is popular manufacturing method because of its high-speed production capability. Performance of plastics part is limited by its properties which

### Objectives. Electric Current

Objectives Define electrical current as a rate. Describe what is measured by ammeters and voltmeters. Explain how to connect an ammeter and a voltmeter in an electrical circuit. Explain why electrons travel

### Reliability Data. LUXEON Rebel. Introduction. Index. Reliability Datasheet RD07

Reliability Datasheet RD7 LUXEON Rebel Reliability Data Introduction This reliability datasheet summarizes the reliability performance of LUXEON Rebel. Overall product reliability depends on the customer's

### Module 3 : Fabrication Process and Layout Design Rules Lecture 12 : CMOS Fabrication Technologies

Module 3 : Fabrication Process and Layout Design Rules Lecture 12 : CMOS Fabrication Technologies Objectives In this course you will learn the following Introduction Twin Well/Tub Technology Silicon on

### Automotive Electronics Council

ATTACHMENT 2 AEC - Q200-002 REV-B HUMAN BODY MODEL ELECTROSTATIC DISCHARGE TEST Page 1 of 14 NOTICE AEC documents contain material that has been prepared, reviewed, and approved through the AEC Technical

### New Methods of Testing PCB Traces Capacity and Fusing

New Methods of Testing PCB Traces Capacity and Fusing Norocel Codreanu, Radu Bunea, and Paul Svasta Politehnica University of Bucharest, Center for Technological Electronics and Interconnection Techniques,

### New Approach to Analysis of the Switching Current Data in Ferroelectric Thin Films

Ferroelectrics, 291: 27 35, 2003 Copyright c Taylor & Francis Inc. ISSN: 0015-0193 print / 1563-5112 online DOI: 10.1080/00150190390222510 New Approach to Analysis of the Switching Current Data in Ferroelectric

### Sputtered AlN Thin Films on Si and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties

Sputtered AlN Thin Films on and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties S. Mishin, D. R. Marx and B. Sylvia, Advanced Modular Sputtering,

### A bidirectional DC-DC converter for renewable energy systems

BULLETIN OF THE POLISH ACADEMY OF SCIENCES TECHNICAL SCIENCES Vol. 57, No. 4, 2009 A bidirectional DC-DC converter for renewable energy systems S. JALBRZYKOWSKI, and T. CITKO Faculty of Electrical Engineering,

### PL-277x Series SuperSpeed USB 3.0 SATA Bridge Controllers PCB Layout Guide

Application Note PL-277x Series SuperSpeed USB 3.0 SATA Bridge Controllers PCB Layout Guide Introduction This document explains how to design a PCB with Prolific PL-277x SuperSpeed USB 3.0 SATA Bridge

### Principles of Adjustable Frequency Drives

What is an Adjustable Frequency Drive? An adjustable frequency drive is a system for controlling the speed of an AC motor by controlling the frequency of the power supplied to the motor. A basic adjustable

### ME 612 Metal Forming and Theory of Plasticity. 1. Introduction

Metal Forming and Theory of Plasticity Yrd.Doç. e mail: azsenalp@gyte.edu.tr Makine Mühendisliği Bölümü Gebze Yüksek Teknoloji Enstitüsü In general, it is possible to evaluate metal forming operations

### A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI)

A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI) Ajay Joshi Georgia Institute of Technology School of Electrical and Computer Engineering Atlanta, GA 3332-25

### 1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.

.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost \$00, get one million miles to the gallon and explode once a year Most of slides