NEWSLETTER 03 July 2014

Transcription

1 July 2014 CONTENTS of this newsletter: About PARADIGM Fact and Figures Partners How to contact us PARADIGM new partners PARADIGM Technology Spectrometer on a chip: 100 channels across 100 nm JePPIX training JePPIX MPW schedule Wandering light,... Bridging EU projects About PARADIGM PARADIGM aims to create the foundations for a powerful, cost effective and versatile foundry platform in Europe. This will lead to a dramatic reduction of fabrication, packaging and testing costs as well as the development time of Application Specific Photonic ICs (ASPICs) based on Indium Phosphide (InP) and thereby pave the way for the breakthrough of the large-scale application of photonics in our daily lives.» read more... How to contact us: For further information about PARADIGM please look on our website, or contact: David Robbins (issue editor): dave.robbins@willowphotonics.co.uk Meint Smit: m.k.smit@tue.nl PARADIGM welcomes new partners PARADIGM welcomes new partners VLC Photonics and EFFECT Photonics. VLC and EFFECT join PARADIGM for its final year, bringing extra depth to the PARADIGM design team in MPW cycle 4 support. Specialises in Optical chip design in multiple photonic technologies UP Valencia spin-off, presence in Spain and the Netherlands seven members having extensive academic and industrial experience 10+ years in the field of integrated optics and photonics EFFECT Photonics spun out from Eindhoven University of Technology (TU/e) in EFFECT: covers the entire process from application selection through chip design, prototype manufacture, packaging design, electronics/module design, prototype production and on to volume production. has an outsourced business model and is one of the early adopters of the Generic Integration Platforms developed in the European photonics research community over the last decade. has a main focus on telecommunications and sensors modules based on InP based photonic integration. 1

2 PARADIGM Technology The ultimate objective targeted in the PARADIGM project by the foundry partners Oclaro and Fraunhofer HHI is to accomplish a generic InP integration platform that encompasses both transmit and receive functionality (TxRx) photonic integrated circuits (PICs). In pursuit of this very ambitious goal, PARADIGM takes the idea of generic photonic integration substantially further than the preceding EC funded project EuroPIC ( ) where Oclaro focused mainly on Tx- and HHI on high speed Rx-only platforms, building on their established and world-leading tunable laser and electro-optic modulator, and high-speed waveguideintegrated photo-detector technologies. In PARADIGM the partners follow a convergent path towards PIC platforms with transmit and receive functionality on the high speed, S.I. substrate. The generic platforms are built up from established building blocks and to this end Oclaro has been working intensively on adapting various building blocks to InP:Fe substrate technology, while the challenge for HHI is to incorporate laser device structures into the existing semi-insulating waveguide/ photo-detector platform. MPW cycle4, currently entering its design phase, is the culmination of over three years of intensive research and development work with both fabs trialing TxRx platforms. PARADIGM MPW runs Since our last newsletter PARADIGM has finalised designs for MPW Cycle 3 at the Oclaro and HHI fabs. These designs are now in process at the Foundries with the first chips expected out shortly. A call for the Cycle 4 designs in January 2014 was heavily oversubscribed and attracted about 50 applications, most from within Europe but also some from North America and the Far East. It is therefore true to say that as of Cycle 3 PARADIGM has gained a truly global reach and has been effective in developing the eco-system around the generic PIC platform. MPW Cycle 2 chips are still being assessed but initial measurements have been very encouraging, with high quality performance and good uniformity across chips. Watch out for results in our next Newsletter. Demonstration: 100 channels across 100 nm AWG-based (de)multiplexing with integrated photo-diodes. Since the early days of photonic integrated circuits (PIC), a pivotal functionality has been wavelength multiplexing and demultiplexing. Without doubt, it is a functionality that has strongly contributed to the success of PICs in telecom applications over the last two decades. In todays world of a maturing foundry model in photonics, as developed in PARADIGM, (de) multiplexing capability remains in the front row and extends its reach beyond telecom applications into fields like sensing. Arguably, the most versatile and adaptable component to realize (de)multiplexing in PICs is the arrayed-waveguide grating (AWG). Hence, it is highly desirable that a MPW run demonstrates and offers high-quality AWG components, i.e. AWGs that exhibit low (excess) loss, are accurately aligned in the wavelength domain, and by using high-contrast waveguide bends, can achieve a fairly small footprint. 2

3 In the second PARADIGM MPW cycle Bright Photonics put the demultiplexing performance of the HHI platform to a challenging test: A design of a 100 channel receiver PIC across a 100 nm wavelength span between 1500 and 1600 nm, i.e. most of the S, C and L band. The device layout is shown below. The device is 6x7 mm2 in size. The PIC incorporates 100 integrated photo-diodes, one for each channel and a spot-size converter matched to the 10 µm diameter of a cleaved standard fibre. The device is also an excellent test vehicle for the reliability and yield of large numbers of photo diodes, which include dense patterns of metal contact lines. Demultiplexing in the device is accomplished by a 1x10 AWG cascade. The central wavelength and channel spacing of the AWGs in the seconds stage have been individually aligned aligned to wavelengths in the outputs of the first stage AWG. To realize low loss and simultaneously smallsize AWGs we combined low and high-contrast waveguides in the designs. The photo-diodes have p and n top-contacts, where n-contacts have been grounded together into four groups to reduce the number of wire-bond connection in case of packaging from 200 down to 104. To give an impression, measurement and simulation Photograph of the final 100 channel receiver chip results are plotted above. All 100 channels are fully operational, an indication of the reliability of the design and fabrication process. AWGs in the cascade are sufficiently wavelength aligned with each other. Excess loss of the AWG cascade is about 1 db. The diodes have a responsivity of 0.8 A/W. All but one diodes showed a dark current of less than 3 na, whereas one showed 7 na. These low dark currents are useful for low noise sensing applications. Although the diodes have not been specifically designed for high-speed we measured a 3 db bandwidth of 5 GHz. This suggests that when employed as a WDM receiver this device can reach 100 channel receiver performance. a 0.5 Tb/s bandwidth using low speed electronics. 3

4 Overall, the results demonstrate state-of-the-art multiplexers in a receiver PIC, designed and fabricated in the PARADIGM platform process; the layout was created by employing the Bright Photonics AWG module in the PhoeniX Software OptoDesigner platform with the HHI design kit. For more information see M. Baier et al, ECOC JePPIX TRAINING The JePPIX training schedule for 2014 includes one 5-day course for Photonic Integrated Circuit design and fabrication, and a two-weeks-long course on Photonic IC technology. The courses offer: photonic IC design with experts hands-on sessions with various software tools introduction to practical fab and measurements aspects working with the JePPIX MPW service to realize photonic IC designs packaging aspects of photonic ICs. These intensive courses aim to provide insight, knowledge about photonic components and circuits, and to prepare designers just starting in the field to get their Photonic ICs ready for fabrication. The training courses are supported by the Nanolab at TU/e, commercial software partners: JePPIX About JePPIX JePPIX is the name by which the InP photonics platforms, and now also the TriPleX platform, present themselves to the photonics community. It is supported by Eindhoven University of Technology Joint European Platform for Photonic Integration of InP-based Components and Circuits JePPIX assists organizations around the globe to get access to advanced fabrication facilities for Photonic Integrated Circuits. JePPIX aims at low-cost development of application specific PICs using generic foundry model, and rapid prototyping via industrial Multi-Project Wafer PhoeniX Software, Filarete, Photon Design, and professional Design Houses: Bright Photonics and VLC Photonics. The training focus in on both the InPbased technology platforms and TriPleX technology for low-loss dielectric waveguides. Training schedule: June 16-20, 2014: Training in Photonic Integrated Circuit Design: InP technology, Boston University, US October 27 November 7, 2014: Training in InP Photonic Integrated Circuit Technology: TU Eindhoven, the Netherlands Costs and registration: for academic participants there is a 50% discount. For more information visit: Put your novel ideas into life! Start designing and prototyping your photonic ICs with JePPIX! runs. It collaborates closely with Europe s key players in the field of photonic integration, including manufacturing and packaging partners, photonic CAD software partners, R&D labs and design houses for photonic ICs. Would you like to become a JePPIX member, for free? Visit: For further information about JePPIX please look on the website or contact Katarzyna Ławniczuk at coordinator@jeppix.eu 4

5 The JePPIX MPW schedule for 2014 JePPIX MPW schedule: tape-out dates for JePPIX provides access to advanced fabrication processes for photonic ICs via full-scale industrial multi-project wafer (MPW) runs. JePPIX aims at rapid prototyping of photonic devices using the Indium Phosphide (InP)-based monolithic integration platforms of Oclaro, Fraunhofer HHI and SMART Photonics and the low-loss dielectric TriPleX waveguide technology of LioniX. The InP platforms of Oclaro and Fraunhofer HHI are the result of research and development conducted under the EuroPIC and PARADIGM FP7 programmes whilst SMART Photonics offers active-passive integration processes developed at COBRA-TU/e. The building block portfolio includes active elements such as SOAs, lasers, DBR gratings, Electro-Optic modulators, phase shifters, and photo-detectors. A broad range of passive devices is also included; for example, straight and curved waveguides, MMIs, and AWGs. With our partners, PhoeniX Software, Filarete and PhotonDesign we offer access to advanced design libraries and software design kits. JePPIX packaging partners, Linkra and Technobis, provide packaging services for InP photonic devices. The packages include electrical and optical interfaces to be assembled with photonic ICs. The package templates have been implemented within the PhoeniX Software and are available for MPW users. 5

6 A choice of fixed chip sizes is available for all MPW foundries. Typical sizes are between 12 mm 2 and 48 mm 2. For the recently started semi-commercial InP-based MPW runs, the entry costs are between 5000 for a small chip and up to 40,000 for a large PIC that can integrate up to several hundred components, including passives, lasers, optical amplifiers, 10 Gb/s modulators and 40 Gb/s detectors. HOW TO GET STARTED WITH YOUR CHIP DESIGN? It is very simple: 1. Join photonic ICs design training or discuss your design with professionals; 2. Reserve your spot on the next MPW run and get the required software and documentation from JePPIX; 3. Start designing your photonic IC with fab s Process Design Kit and Design Manual, or get a Design House support; 4. Make sure to be ready before the deadline. JePPIX seeks to partner European companies and SMEs in the ACTPHAST (FP7) open call for innovation support. ACTPHAST offers support for prototype development of photonic solutions using one of the seven platform technologies. They include platforms for fabrication of Photonic ICs in InP, Silicon and TriPleX technology. ACTPHAST offers support with design, fabrication and testing of prototypes, and for SMEs this service is free. JePPIX together with the LightJumps project supports individual SMEs with development plans for photonics-enabled products and services, and provides connection to photonic clusters. We will support a few selected SMEs in applying for grants (up to 2.5 M ) in the Horizon 2020 dedicated SME Instrument. Wandering light, an obstacle to VLSI Photonics Once you know what it is, you stay away from it. But it may not always be possible. In dealing with real photonic waveguides and circuits, the unavoidable presence of fabrication tolerances and imperfections causes the light to travel along unplanned paths, reaching ideally isolated ports or components and generating misbehaviours with respect to the designed and simulated circuit. A typical example is light scattering from distributed roughness along the sidewall, a phenomenon that can be largely reduced with a careful tuning of the technological process but cannot be avoided completely. Inevitably, etching processes cause a random deviation of the waveguide width from its nominal value, resembling the effect of a nano-scale chisel on the vertical sidewalls. Even though these vertical stripes are generally only few nanometers deep, they can severely affect the propagation of the optical mode within the waveguide. The interaction of the light with sidewall roughness induces a coupling mechanism which transfers part of the optical power from the propagating mode(s) to other guided modes (propagating and counterpropagating) and radiative modes, generating backscattering and light radiation. These phenomena have been thoroughly investigated in PARADIGM, resulting in a novel and unified vision of roughness-related impairments, referred to as the n w model (whose details are reported in D. Melati et al., Journal of Optics, vol. 16, no. 5, 2014). Supported 6

7 Sidewall roughness generates backscattering and radiative cross talk, which can be detected also far beyond the typical distances of evanescent coupling. and validated by a large amount of experimental data, the n w model reveals for the first time that, given the properties of the sidewall roughness (defined by the technology), both backscattering and radiative losses depend only on the sensitivity (derivative) of the mode effective index to waveguide width perturbation. This result has been demonstrated to be in very good agreement with existing models that individually describe radiative loss or backscattering only. Further, the n w model finds general application to both 2D and 3D waveguide structures and is not related to any particular technology or waveguide shape, being an essential property of the guiding structure itself. Unfortunately, this is only part of the story since only rarely does a waveguide lie isolated on a chip. If back-reflected light can affect the functionality of a circuit in itself, e.g. degrading the transfer function of a passive filter or the quality of the emission of an integrated laser, radiated light can also be a risk, producing much more than a simple power leakage. Radiation represents another way for the light to sneak out from the desired path and reach unwanted regions. As sidewall roughness couples power from a guided mode to radiative modes, like an emitting antenna, it can also work in the other direction (receiving antenna), collecting radiated light and exciting back a guided mode in a nearby waveguide. In other words, sidewall roughness generates radiative optical crosstalk between closely spaced components, thus limiting the density of devices on a chip. Even in this case, PARADIGM has succeeded in producing a detailed characterization of this phenomenon (D. Melati et al., Optics Letters, vol. 39, no. 14, 2014) and a model able to predict the strength of the crosstalk generated by the sidewall roughness, which remains significant far beyond the typical distances of evanescent coupling. Obviously the problem of back-reflections and crosstalk are not only related to a distributed effect such as sidewall roughness. They commonly appear also as consequence of a localized bulk variation of the waveguide geometry or cross-section. This problem has been addressed in PARADIGM in relation to the interfaces between active and passive waveguides, a point of particular interest because of the presence of integrated laser sources directly coupled to passive structures. It was observed that non-optimized butt-joints interfaces can lead to high losses and crosstalk levels even with devices placed hundreds of microns away from the laser source. 7

8 Regardless the source of reflections and crosstalk, it is clear that it is of primary importance for a designer to be able to predict the impact of these phenomena on the circuit, in order to correct the design and mitigate their effects. In this case, what is the best choice? Since this evaluation has to be done during the design phase, the simulation speed is fundamental, and avoiding the aggressive use of electromagnetic approaches such as FDTD is therefore important. Circuit simulation seems to be a good approach because it allows very fast simulations without reducing the accuracy of the results. The tricky part is that this kind of simulation requires the underlying models to be sufficiently accurate to simulate realistic behaviours, in particular for random phenomena such as those generated by sidewall roughness. The joint efforts of the PARADIGM partners have allowed us to overcome this problem. Extremely advanced circuit models finally closed the loop between theoretical investigations, experimental measurements and instruments for the designers, who can find, through the Process Design Kits, a way to chase and tame the rebellious light. Effect of sidewall roughness on the drop port of a Bragg-grating-based add-drop multiplexer. Backscattering (green curve, bottom) reduces the off-band isolation by more than 20 db with respect to the ideal case (blue curve). 8

9 Bridging EU projects: PARADIGM meets BBOI Two apparently different European projects that exchange ideas, share facilities and mutually exploit their results. It is not a story we can read very often, but when it happens it is a great success, not only for the involved partners but for the whole EU funding scheme. And this is the case of PARADIGM and BBOI, the latter being a recently started FET project coordinated by one of the partners of PARADIGM, Politecnico di Milano. BBOI (website: aims at Breaking the Barriers of Optical Integration by boosting the complexity of photonic architectures well beyond the state of the art, without increasing power consumption in proportion. The key of the BBOI recipe is a multifunctional photonic platform equipped with novel optical probes and actuators, driven and supervised by algorithmic intelligence never conceived before. Although BBOI focuses on Silicon Photonics, its first breakthrough, a transparent optical probe named CLIPP (ContactLess Integrated Photonic Probe), has been successfully exported to Indium Phosphide (InP) technology. This has been made possible by the open collaboration between BBOI and PARADIGM partners, and thanks to the PARADIGM InP foundries, HHI and Oclaro. But why bring a transparent detector onto an InP platform? InP technology is the most complete and best assessed photonic platform available today: almost every kind of passive functionality, CW and pulsed sources, intensity and phase modulators, photodetectors and high speed functions are available on most industrial and academic foundries. So many ingredients enable designers to conceive very complex photonic circuits, which can implement arbitrary functions, and apparently nothing is missing. However, when a large number of photonic building blocks are integrated, their working points need to be controlled by placing monitor photodetectors in suitable positions on the chip. Unfortunately, conventional photodetectors absorb (by definition) a portion of the light, contributing to the overall insertion loss. In this way, if tens or hundreds of photonic elements are integrated, much of the power is likely to be wasted just for monitoring operations. As mentioned, BBOI conceived and patented CLIPP, a non-invasive light observer that neither absorbs extra photons in excess to the loss of the bare waveguide, nor impacts on the propagating light. In other words CLIPP is really transparent, because the light is not aware that someone is looking at it. The CLIPP is amazingly simple, because it consists of only two small metal pads placed close to the optical waveguide. Any metal technology can be used, so that no additional process steps are required if there are existing metal layers on the chip (e.g. for modulators or photodetectors). 9

10 CLIPP on an InP waveguide (left) and on a Silicon Photonics waveguide (middle). Dependence of the waveguide conductance on the power flowing in the InP (red) and SOI (black) waveguide. The CLIPP working principle exploits a physical effect named Surface State Absorption (SSA) that causes a small absorption of photons locally on the few atomic surface layers of the waveguide. This absorption mechanism is often neglected, because it introduces a very small contribution to the waveguide attenuation. However, the few absorbed photons generate free electrical carriers that slightly vary the electrical conductance of the waveguide. SSA occurs both in silicon and InP waveguides, independently on the waveguide surface quality, and is almost linearly dependent on the optical power flowing in the waveguide. Reading this small change of the waveguide conductance is the trickiest part of the work. BBOI succeeded to do it by using an impedimetric detection scheme combining a low noise integrated transimpedance amplifier and lock-in mixer, realized in the AMS foundry through the Europractice scheme. This result, whose technical details can be found in F. Morichetti et. al, J. Selected Topics in Quantum Electronics, July 2014, has been highlighted in Stalking light, Nature Photonics, Vol. 8 April First conceived and demonstrated on Silicon Photonics, the same CLIPP concept was successfully tested within PARADIGM on InP chips provided by HHI and Oclaro. But this is just the beginning of the story. BBOI will participate as a user to the fourth PARADIGM MPW run to fully demonstrate the applicability of the CLIPP concept on the InP generic foundry platform and to realize the first InP based feedback controlled photonic circuit through CLIPP. 10

11 About PARADIGM (Continued from page 1) Covering the complete product creation process from idea to product, from research to manufacturing, PARADIGM targets the following areas: Technology convergence and roadmapping. To create methods and tools. To set up generic packaging and testing. To exploit and disseminate the project results. During the course of the project direct access for external users to the generic platforms is being provided, whilst they are in development, by offering both circuit fabrication and user support in four multi-project wafer (MPW) foundry cycles. Fact and Figures: Project reference: FP7 ICT Co-ordinator contact: Prof. M.K. (Meint) Smit Website: Timeline: Start date: 01/10/2010 End date: 30/09/2014 Budget: Total Cost: EUR Partners: Technische Universiteit Eindhoven, Netherlands Willow Photonics Ltd, UK The Centre for Integrated Photonics, UK Oclaro Technology ltd, UK Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.v, (HHI and IZM), Germany Chalmers Tekniska Hoegskola AB, Sweden Filarete s.r.l., Italy PhoeniX BV, Netherlands Gooch & Housego (Torquay) Ltd, UK Photon Design Ltd, UK Alcatel-Thales III-V Lab, France University of Cambridge, UK Linkra S.R.L., Italy Politecnico di Milano, Italy Warsaw University of Technology, Poland Bright Photonics, Netherlands VLC Photonics, Spain EFFECT Photonics, Netherlands How to contact us: For further information about PARADIGM please look on our website, or contact: David Robbins (issue editor): Meint Smit: 11