NEWSLETTER 04 July 2015

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1 CONTENTS of this newsletter: Editorial: What has PARADIGM achieved? PIC design environment PICWave and Building Block Creation Second Eastern European Workshop for generic InP technology A Low-Energy, High-Performance 8x8 SOA Switch A 2 8 photonic integrated switch for FTTx networks Editorial: What has PARADIGM achieved? This is the fourth and last PARADIGM newsletter; the project reached its conclusion at the end of May The last four and a half years have seen some remarkable advances in photonic integrated circuits fabricated on generic platforms. In 2010 the PARADIGM partners were taking their first steps to define generic InP platforms which could be run in industrial fabs, in an initiative which was unique in the world.» read more... PIC platforms at HHI Integrated mode-locked lasers Development of PIC Packaging SAG for extended wavelength operation Generic on-wafer testing JePPIX roadmap 2015, published JePPIX training courses Open letter to participants in MPW-runs About PARADIGM Fact and Figures Partners How to contact us PIC design environment The key to creating and verifying innovative products for any technology is a set of pre-characterized building blocks, which a designer can use to create a complex device or system. For electronic design and manufacture, mature EDA (Electronics Design Automation) oriented flows require foundries to offer a set of building blocks, with corresponding verification rules, which a designer can integrate to create complex digital CMOS based electronic integrated circuits to meet a desired need.» read more... 1

2 1. Editorial: What has PARADIGM achieved? (continued from page 1) By David Robbins (Willow Photonics) and Mike Wale (Oclaro) The last four and a half years have seen some remarkable advances in photonic integrated circuits fabricated on generic platforms. In 2010 the PARADIGM partners were taking their first steps to define generic InP platforms which could be run in industrial fabs, in an initiative which was unique in the world. Now in 2015 it is possible for interested users to access multi-project wafer (shuttle) runs on InP on a semi-commercial basis, accessing platforms at the Fraunhofer HHI (Berlin), SMART Photonics (a spin off from PARADIGM partner COBRA at TU Eindhoven), and shortly at Oclaro in the UK. In 2010 supporting software tools were almost non-existent, now the PARADIGM partners can provide photonic design kits tailored to the capabilities of each fab, and a variety of simulation tools for active and passive circuit level modelling. The task of integrating these tools using the PDAFlow foundation set up by the earlier EuroPIC project, has fallen to PARADIGM. The API (application programming interface) brings a high level of standardisation and interoperability to platform software tools. Many software tools are now API compliant, as discussed by Twan Korthorst of PhoeniX Software in this newsletter. PARADIGM has also moved ahead under the JePPIX banner with its brokering operation, to provide user access and support beyond PARADIGM; JePPIX is a part of TU Eindhoven. PARADIGM has been able to put in place a first release of platform technology which can be readily accessed by users, and although there is plenty of work left to be done, for example in qualification and test and verification, these platforms are sufficiently mature to enable Universities, SMEs and larger companies to access the technology at reasonable cost and try out their ideas quickly. We hope that such ideas can mature alongside the platforms into fully fledged and profitable products in the near future. There are many aspects to the PARADIGM technical programme: platform technology, software tools, packaging and test to identify but a few. This newsletter showcases some of the more than 100 PIC designs fabricated over the 7 full MPW runs carried out in the project and the software tools which supported the designs; however, PARADIGM is fundamentally a technology development programme. The consortium has made great strides forwards, creating new platform building blocks for 40GHz operation and trialling fully integrated transmit and receive platform functionality, ahead of a second generic platform technology release planned for 2016/2017. One of these technology developments is a process building block based on selective area growth (SAG), capable of offering operating wavelengths over a 150nm wavelength range on a single wafer as discussed later. The PARADIGM platforms already offer a leading edge InP-based PIC technology which is unmatched by other photonics platform technologies in terms of content and capability. The newly published JePPIX roadmap for 2015 explains how we believe this technology, and access to it, will develop in the coming years ( 2

3 2. PIC design environment: VPIphotonics joins the PDAFlow initiative (continued from page 1) By Twan Korthorst (PhoeniX BV) The key to creating and verifying innovative products for any technology is a set of pre-characterized building blocks, which a designer can use to create a complex device or system. For electronic design and manufacture, mature EDA (Electronics Design Automation) oriented flows require foundries to offer a set of building blocks, with corresponding verification rules, which a designer can integrate to create complex digital CMOS based electronic integrated circuits to meet a desired need. This concept also applies to today s Photonics Design Automation (PDA) oriented flows; however, the PDA oriented flow allows for a greater emphasis on novel implementation and analysis of the photonic building blocks (BBs) to develop new and innovative photonics products. A second key differentiation between EDA and PDA is the large parameter space typical photonic BBs have, where transistors are typically describe by 1 or 2 parameters with a limited value range, basic photonics components can easily have 5 to 10, with large value ranges. This is mainly caused by having analogue rather than digital design. A typical workflow for digital IC design contains several automated steps including logical synthesis and autogeneration of the circuit layout. An analogue IC design flow is much more comparable with photonics IC design, with many manual steps, like component design and routing. In PARADIGM, the software partners Filarete, Photon Design and PhoeniX Software have been collaborating to further develop an integrated design flow, tailored to the needs of designing application specific PICs, using a generic foundry process at one of the foundry partners in the project. From its earliest beginnings the designers in the field of integrated photonics have been working with a bottom-up approach, starting from the fabrication technology and materials and taking these as a starting point to develop photonic integrated devices. SYSTEM Simulations CIRCUIT Simulations PICWave (time-domain) OptoDesigner (freq.-domain) ASPIC (freq.-domain) COMPONENT Simulations FIMMWave FIMMProp OmniSIM OptoDesigner Mode-solvers, Propagation, Actives COMPONENT Layout Implementation OptoDesigner Layout, Functional Verification CIRCUIT Layout & Routing OptoDesigner Routing VERIFICATION Design to Manufacture OptoDesigner DRC, maskprep, processflow MANUFACTURING Chip Fabrication Living Database Process & Measurement data Figure 1 Overview of PARADIGM software partners solutions in the integrated photonics design flow. 3

4 With the introduction of more standardised and generic fabrication processes, and the resulting creation of design kits (PDKs), a mixed design approach has evolved in which one group of designers is developing the contents of the design kits and another group of designers is using these design kits in a top-down driven approach starting from the system or circuit level. The software tools required to create a full Photonics Design Flow include circuit simulators, mask layout tools, design rule checkers, but also physical modelling tools such as mode solvers and propagation simulators. With all relevant information available in one defined PDK standard, it becomes possible to start designing a circuit at the conceptual level, validating it with time-domain and frequency-domain simulations and, only when satisfied, generating the mask layout information. For this purpose an API (Application Programming Interface) was developed in project EuroPIC and this has been further extended and developed in PARADIGM. The main purpose of this API is to allow interoperability of software tools from different vendors, using standardized information contained in a PDK from a foundry. Recently, VPIphotonics decided to join this initiative 1 and implemented the required interfaces in its VPIcomponentMaker Photonic Circuits product. As a result of this work VPIphotonics and PhoeniX Software were recently able to demonstrate the transfer of a circuit design made in the VPI tool, based on information in the PDK from project partner Fraunhofer HHI, to OptoDesigner to finish the mask layout by fitting it into a standardised packaging template The PDAFlow Foundation is a non-profit organization set up for the development; support and licensing of software standards for photonic design automation (PDA). The PDAFlow Foundation was formed in 2013 to further develop, support and (sub-) license the PDAFlow API to automate photonics design flows and create sustainable standards. The goal of the PDAFlow API is to enhance research, process and product development by improving interoperability of (PDA) software tools and provide access to Process Design Kits (PDKs). More information is available at 2 The design used for this demonstration and shown in Figure 2 is taken from the paper: Transmitter PIC for THz Applications Based on Generic Integration Technology, F.M. Soares, J. Kreissl, M. Theurer, E. Bitincka, T. Goebel, M. Moehrle, N. Grote, IPRM2013, May 19-23, 2013, Kobe, Japan Figure 2 Example of a design transfer from circuit level to mask layout, based on the FhG/HHI PDK 2 4

5 3. PICWave and the Art of Building Block Creation By Richard Lycett and Andrew Dabbs (Photon Design) Photon Design s circuit simulator, PICWave, is a time-domain CAD tool for designing and simulating photonic circuits containing both active and passive components. PICWave features a powerful building block (BB) system that enables an expert designer to build a library of building blocks or a design kit. The kits contain a BB or model for each component, such as an SOA, laser, bend, MMI, etc. Each BB can be parameterised to allow flexibility within the fabrication restrictions and calibrated to capture the behaviour of the actual component. A circuit designer can then be given a design kit for a fab to build and simulate their own application specific photonic integrated circuit without having to worry about the underlying materials and fabrication process. Such a high abstraction approach opens up photonic circuits to be exploited by a much wider community. SOA gain (linear) HHI Platform - Active BBs current [ma] Figure 3 Active BBs (top) now available in PICWave s Fraunhofer HHI design kit. Characterisation results (bottom) for a Fraunhofer HHI 400 µm long SOA, comparing experimental and simulated gain vs. current where latter uses a fitted active material model which captures material gain response over wide range of wavelength and currents, and form basis of SOA, DFB and DBR models. PICWave provides the tools to build and use BB libraries and allow circuit designers to: combine passive (waveguides, MMIs, gratings etc.) and active optical components (SOAs, lasers, modulators etc.) in a time-domain circuit simulation model non-linearity and stochastic noise in active components and detailed wavelength response of passive components build sophisticated electrical models which can handle arbitrary circuits of inductors, capacitors, resistors, voltage and current sources and couple these to the photonic components adjust BBs by selected limited parameters, set by fab and design kit author, effectively ensuring that a design stays within the constraints of the design rules generate a variety of circuit results at any point in your circuit to diagnose any design flaws: e.g. eyediagrams, time-evolving spectra and measure power/ wavelength at any point build combined building blocks, CBBs, which can allow non-expert users to create a group of BBs to be used just like a BB, putting together commonly grouped components into a single object export finished circuit designs as a netlist for layout generation in compatible software 5

6 PARADIGM InP Design Kits As part of the PARADIGM project, design kits for both the Fraunhofer Heinrich Hertz Institute (HHI), and Oclaro InP platforms have been further developed and are available for PICWave. The latest version includes active BB models for the HHI design kit. The sophisticated PICWave SOA models have been carefully calibrated to experimental measurements, enabling an active circuit simulation to accurately predict spectral gain and optical saturation and noise effects. (See Figure 3.) Figure 4 shows an MZI-regenerator; this device can amplify an input signal and convert it to another wavelength. This is a highly non-linear device which relies on gain competition between the different signals that are injected in the SOAs. The BB model captures and includes the side-effect of noise added to the regenerated signal by the SOAs. Using PICWave with the Oclaro and HHI design kits reveals that a similar performance for this device could be achieved in both fabs with the same footprint. Such information can be vital when choosing a fab as some designs may be better suited to one fab over another. PICWave and the BBs developed through the work in PARADIGM can now provide a powerful prototyping aid for InP Multi-project Wafer designs on the Oclaro and HHI platforms. With it one can model the physics including active, passive and optoelectronic interactions. The circuit design can then be exported in a PDAFlow compliant netlist to be used in a mask layout tool for further design rule checking and, ultimately, the submission of the design to the fab. Input data signal (λ 1) CW source (λ 2) Regenerated signal (λ 2) CW balance (λ 1) Input signal (λ 1) ON/OFF ratio = 5 Regenerated signal (λ 2) amplified x4 ON/OFF ratio increased by > order of mag. Figure 4 MZI regenerator circuit with example input and regenerated signals in oscilloscope plots. 6

7 4. Generic Integration Technologies for Photonics: 2 nd Eastern European Workshop for Research Institutes, SMEs and Large Companies: 21st - 22nd May 2015, Warsaw University of Technology, Poland The 2 nd Eastern European Workshop Generic Integration Technology for Photonics was successfully held on 21st and 22nd May 2015 at the Faculty of Electronics and Information Technology of the Warsaw University of Technology. The event gathered nearly one hundred of participants from universities, research institutes and companies. The scope of the workshop covered all aspects of the generic approach to photonic integration. The general concept was presented and all consecutive stages of the generic manufacturing chain were discussed in detail by toplevel experts in the field. These were complemented by a tutorial on designing photonic integrated circuits with dedicated CAD software. Also the capabilities of different technological platforms were presented and financial mechanisms supporting further development of integrated photonics were discussed. Finally, ASPIC users, who participated in PARADIGM multi-project wafer runs, provided their feedback on their own experience in exploitation of the generic foundry platform and cooperation with the PARADIGM consortium and Eastern Europe Design Hub in particular. For further information please visit the website 5. Low-Energy, High-Performance, 8x8 SOA Switch By Adrian Wonfor (University of Cambridge) The University of Cambridge Centre for Photonic Systems has a history of designing and testing high performance integrated optical switches, with a particular emphasis on lossless operation, short switching times and energy efficient operation. The group demonstrated the world s first 16x16 port lossless integrated SOA based switch 1. This design used all active components, however, and as a result had an energy efficiency of 100pJ/bit at per channel data rates of 10Gb/s A. Wonfor, H. Wang, R. V. Penty, and I. H. White, Large Port Count High-Speed Optical Switch Fabric for Use Within Datacenters [Invited] J. Opt. Commun. Netw., vol. 3, pp. A32-A39,

8 Recently we have devoted particular effort in improving the energy efficiency of such switches, in line with our commitments as part of the Greentouch consortium ( ), devoted to improving energy efficiency in global ICT networks. To this end we have benefitted greatly from our participation within the PARADIGM project, which has enabled us to design compact, energy efficient SOA based switches. The ability to design photonic integrated circuits which use standard building blocks for both active and passive components has enabled us realise world class PICs fabricated at state-of-the-art commercial facilities. Second stage First stage 4 mm In Out Power penalty [db] 14.5 db With out bias control With bias control 6 mm Third stage Input power [dbm] Circular bend 90 degree crossing 2x1 MMI combiner SOA gate Transition element Figure 5 Photograph of the 8x8 port switch PIC, which was fabricated by Oclaro. Figure 6 Input power dynamic range plot and error free eye diagrams of the operating switch. Such a PIC, shown in Figure 5, is an 8x8 port SOA based switch 2. The design is based upon a Clos architecture, with both the input and outputs on the same side of the switch, easing optical access and packaging challenges. The switch is very uniform in operation with on-chip gain between 3.8 and 7.8dB for all paths on, through the switch. The dynamic performance of the switch is excellent, with error free operation exhibited over a 14.5dB input power dynamic range for a 1dB power penalty, as shown in Figure 6. Switching operation is also fast, with 3.3ns rise times and 1.8ns fall times. In summary this switch operates error free with excellent switching times and a greatly diminished energy consumption of 15.8pJ/bit a reduction of 6.4 times the energy consumption compared to our all active switch Q. Cheng, A. Wonfor, J. L. Wei, R. V. Penty, and I. H. White, Low- Energy, High-Performance Lossless 8 8 SOA Switch OFC 2015 Los Angeles,

9 photonic integrated switch for FTTx networks By Ryszard Piramidowicz (Warsaw University of Technology) Fibre-optic communication systems are a field in continuous dynamic development. It is observed in every part of telecommunication network, but access systems experience definitely the most impressive evolution. The expanding range of offered services, combined with an increasing number of telecom operators and end users necessitates intensive development of efficient, reliable and low cost equipment, dedicated for use in access systems, implemented typically as fibre-to-the-x (FTTx 1 ) networks. Application of photonic switching elements allows us to design reconfigurable network architectures, which in turn helps us to use the available fibre infrastructure in more efficient way. in1 in2 out8 out1 out2 out3 out4 out5 out6 out7 The 2 8 photonic integrated switch, presented in Figure 7, provides for flexible use of the last mile of FTTx networks in a multi-operator environment. The device is to be located at a splitting node, which is usually the last splitter in a point-to-multipoint architecture. It is assumed that all of the operators use the same wavelength channel. The switch determines from which operator (input port) the incoming optical signal goes to which subscriber (output port). The photonic circuit was designed by the Eastern Europe Design Hub at the Institute of Microelectronics and Optoelectronics of the Warsaw University of Technology and fabricated at Fraunhofer HHI in Berlin. Characterization results have proved the targeted properties of the integrated switch; the extinction ratio is above 25 db within the C-band, while the drive current is around 25 ma for a single switching cell FTTx is a collective term for a number of different fibre based network Figure 7 Circuit Schematic (top) and Photograph (bottom) of the 2 8 photonic integrated switch which was fabricated at Fraunhofer HHI, Berlin. topologies, ranging from Fibre to the Home (FTTH) to Fibre to the Neighbourhood (FTTN) with final data connections spanning zero to a few km. 9

10 7. PIC platforms at HHI By Norbert Grote (Fraunhofer HHI) HHI s PIC platform is particularly suited for high speed applications, thanks to the ample use of semi-insulating material for waveguides and substrate. On the receiver side photodiodes with 40GHz bandwidth have been implemented on the platform right from the start of its development in the preceding EuroPIC project. With the extension to a platform capable of both transmitter and receiver functions (TxRx) in PARADIGM. Integrated lasertype devices are also available now as building blocks, in particular fast DFB lasers. As an outcome of the previous Multi-Project Wafer run we characterized the high-speed performance of such devices integrated with passive input/output waveguides. Having a 200µm long cavity, as offered as part of the Tx/Rx PDK, they showed a room temperature bandwidth of ~15GHz at 70mA bias current enabling direct modulation at 25GBaud. Furthermore, using quaternary pulse amplitude modulation (PAM-4) transmission of 50Gb/s could be demonstrated over 5 km of standard single mode fibre. Applying receiver-side signal equalization the bit-error ratio was below the FEC limit. These results highlight the capabilities of HHI s PIC platform to generally meet the challenges of next ultra-high data rate transmission systems, namely the upcoming 400Gbit/s Ethernet standard. More on this achievement will be presented at the next IPRM conference ( to be held in Santa Barbara, USA, from 28 th June - 2 nd July this year. AR-coated Facet DBF Laser Monitor PD AR-coated Facet Passive Waveguides Figure 8 DFB laser PIC used in PAM-4 25 GB transmission experiment 8. Integrated mode-locked lasers By Valentina Moskalenko (TU Eindhoven) A mode-locked laser is a light source that produces a periodic train of light pulses. The high intensity and short duration of such pulses allows one to use them in various applications ranging from research areas requiring time-resolved measurements to material processing (drilling holes, surface treatment and as a laser scalpel in ophthalmology). In the spectral domain mode-locked lasers feature wide coherent optical combs, which make them very attractive as a source in high-speed gas sensing and wavelength division multiplexing schemes. 10

11 Due to their simple design mode-locked lasers can be realized on a single monolithic chip. One of the ways to achieve mode-locking is to use a so-called passive mode-locking technique. The advantage of this method is that there is no need for an external RF source or optical pump. Using a PARADIGM ridgelaser platform a resonator can be formed by integrating a semiconductor optical amplifier (SOA) with a saturable absorber (SA). The SA is realized as a short SOA section. The SOA section typically has a length from hundreds of micrometers to a few millimetres. The SA section is much shorter, typically a few tens of microns. Integration of mode-locked lasers allows one to also reduce their costs and brings an opportunity to combine them with other optical elements into more complex systems on the same chip. Figure 9 shows the mask layout and the optical output spectrum of a 20GHz mode-locked laser realized on the Oclaro platform. a) 2 mm SOA SOA SA b) Power, db Lambda, nm Figure 9 The mask layout (top) and the optical output spectrum (bottom) of a 20GHz mode-locked laser 9. Approaches to PIC Packaging and the development of packaging standards By Bob Musk (Gooch and Housego) and Antonello Vannucci (LINKRA) PARADIGM resources have stimulated a significant amount of development of suitable packaging for generic PICs. PARADIGM has pioneered a new packaging approach; PIC designers are required to adhere to a predefined template for package compatibility; PARADIGM has set out to design the PIC to fit the package, and standardisation of the PIC I/O and geometry has enabled PARADIGM partners to develop two packages capable of satisfying most of the circuit requirements brought forward by our users. LINKRA now offers a commercial packaging service for InP PICs. For more details see the JePPIX website The package features: Dual in line DC leads pin for I/O DC signals fully available 2+2 extra leads (added to the 48 I/O) for thermal system management Optical feedthrough for two lensed fibres Temperature control 4 GPPO connectors for HF ports up to 40GHz 11

12 Figure 10 The PARADIGM-LINKRA package showing details of the chip, enclosure and electrical (dc - side and RF - rear) connectors. Inset shows internal details of the fibre chip interface A novel actively aligned package: As highlighted in the first PARADIGM newsletter, PARADIGM has pioneered a highly novel, but open sourced, package design which we are now seeking to make a global standard through the IEC 1. In April 2015 the IEC approved a new project: SC86C WG4 PIC (Photonic Integration Circuit) packaging, based on input from PARADIGM partners. This committee will work with IEC JWG9. Much attention has been paid with regard to the standardisation of the package platform, processes, materials and interface components in order to support and promote this packaging approach. In addition, a simplified active alignment process has been developed which does not require the use of expensive functional test equipment. In summary, this package will be capable of supporting the following electrical and optical attributes: TEC temperature control if required Hermetic package 36 DC/low speed connections 10 high speed (up to 25GHz each) connections in GSG configuration. Up to 12 single mode fibres supported, either pigtailed or connector interface QSFP+ compatible Figure 11 The PARADIGM active aligned package showing the chip enclosure and connector with the connector and fibre ribbon. 12

13 10. SAG for extended wavelength operation By Jean Decobert, Mohand Achouche (III-V Labs) and Norbert Grote (Fraunhofer HHI) Butt-Joint Passive Waveguide (E1700) broadbandar coating index-coupled DFB laser w/100µm SOA PL1 1457nm wavelenght (nm) PL4 1520nm PL7 PL4 1581nm 1601nm Figure 12 Part of a DFB/SOA PIC array (left) relying on AlGaInAs based SAG technology. Output spectra (right) for elements of the laser array. Power (dbm/nm) PL2 1477nm 155nm PL6 1561nm A key challenge for monolithic photonic integration is the implementation of building blocks that, for a given operation wavelength, would require different bandgaps of the active materials to provide optimal performance. Butt-joint technology is a widely used approach but requires dedicated and multiple epitaxial growth steps for each of those diverse devices. Another powerful approach which can significantly extend design freedom in conjunction with butt-joint technology is referred to as Selective-Area-Growth (SAG) technology. It makes use of enhanced growth rates when depositing III-V materials in restricted areas of an otherwise masked (e.g. SiO 2 ) substrate wafer, associated with band gap changes of MQW structures in one single epigrowth step. This band gap engineering technology has been intensely developed at PARADIGM partner III-V Lab in recent years for versatile integration mainly of transmitter components and functions (for example lasers, modulators, passive waveguides, ), and demanding Photonic Integrated Circuits have been demonstrated with extended functionalities and enhanced performance. SAG can be used for longitudinal integration, i.e. in the optical waveguide direction, of active components such as lasers, electroabsorption modulators (EAMs), semiconductor optical amplifiers (SOAs), together with passive sections such as spot size converters (SSCs). SAG can also be used for parallel integration, with large wavelength shift of numerous juxtaposed devices such as laser arrays with a passive multimode interference (MMI) coupler, for coarse-wavelength division multiplexing (CWDM) 1. Within PARADIGM, III-V Lab together with Fraunhofer HHI, is exploring the best methodology to adapt and transfer SAG technology to the generic foundry model. To this end, DFB/SOA arrays have been fabricated at HHI using III-V Lab s AlGaInAs SAG-based epi-structures in trial runs. Array devices with good performance have been accomplished across a spectral range of as wide as 150nm, Figure 12. This achievement clearly shows the large potential of such a SAG platform for extending the capabilities of the present PIC platforms, paving the way to the next PIC generation - an approach exclusively feasible in III-V technology more may be read in: J. Decobert et al., AlGaInAs MOVPE selective area growth for photonic integrated circuits, Adv. Opt. Technol. 2015; 4(2), p ) 13

14 11. Generic on-wafer testing 2015 By Meint Smit (TU Eindhoven) The generic foundry model in integrated photonics is enabling low-cost rapid prototyping of complex Photonic ICs. To make the rapid PIC development sustainable a significant change in characterization methodologies needs to take place. A significant reduction of the testing time and cost can be achieved by moving a large part of the testing from the circuit (chip) level to the building block level (generic testing). If the building blocks are within specs, and the design satisfies a complete set of design rules, the chip functioning should also be correct. Further cost reduction can be achieved by moving from die-level testing to wafer-level testing, which requires moving from the optical to the electrical testing domain. To realize on-wafer characterization for validating generic ICs we have developed dedicated test modules for characterizing the performance of the most important Basic Building Blocks. Each of the dedicated test modules comprises an integrated light source and an integrated detector. The integrated input and output offer the possibility for validation of optical properties in the electrical domain. By shifting the characterization from the optical to the electrical domain the critical and time consuming optical alignment is avoided and test cells can be characterized on-wafer, before cleaving and dicing. Moreover, the use of an integrated source greatly reduces the excitation of higher order modes or other polarizations that can easily be excited during optical input coupling. Characterizing all the Basic Building Blocks (BBBs) in the electrical domain through electrical signals opens the way to an automated measurement procedure for quick and accurate cross-wafer characterization of the BBBs. We have reported electrical on-wafer characterization of propagation loss in passive waveguides using a dedicated test module 1. More recently we have adapted this test module to enable simultaneous measurement of phase modulation efficiency. The test module is shown in Figure 13 as an inset of a full wafer E. Bitincka, G. Gilardi, M. K. Smit, On-wafer Optical Loss Measurements Using Ring Resonators With Integrated Sources and Detectors, IEEE Photonics Journal, 6, 5, (2014). DBR laser 2x2MMI PD 0.32mm 3.1mm Phase modulator Figure 13 Full processed wafer (left). Microscope photograph (right) of the test module for electrical characterization of waveguide loss and phase modulation efficiency 14

15 The fabricated test module shown in the inset of Figure 13 consists of a tunable Distributed Bragg Reflector (DBR) laser as an integrated source, an integrated photo detector, and a high sensitivity ring resonator, which contains a phase modulator. The resonator will show periodic dips in the transmission when sweeping the wavelength or the voltage over the internal phase modulator. The depth and the widths of the dips are strongly dependent on the propagation loss of the ring. By measuring the depth and the width of the resonance dips in the transmission of the resonator, while sweeping the wavelength, we can measure the propagation loss of the ring, and by comparing the loss of two rings with a different length of the straight waveguide sections in the ring, we have achieved a measurement accuracy of 0.2dB/cm, which is significantly better than that realized with timeconsuming manual measurements on cleaved dies. Further, by measuring the shift of the dips as a function of the voltage on the integrated phase modulators, we can calculate the phase modulation efficiency. The test structures developed in the PARADIGM project are a first step to rapid automatic on-wafer testing of a number of important chip and wafer properties. 12. JePPIX roadmap 2015 on integrated photonics and generic foundry approach By Katarzyna Ławniczuk (TU Eindhoven) The generic foundry approach is initiating a revolution in micro and nanophotonics, just as it did in micro electronics thirty years ago. Generic integration causes a dramatic reduction in the entry costs for applying Photonic ICs in improved or novel products, and brings them within reach for many SMEs, large companies and research institutes. So far, most applications of photonic ICs (PICs) have been in the field of telecommunications and data communications, but presently they are becoming much broader; examples are fibre sensor readout units, gas sensors, medical diagnostics, metrology, THz and antenna systems. In the recently published JePPIX roadmap 2015 a road to a multi-billion Euro market in Integrated Photonics is predicted before 2020, and enabled by Photonic Integrated Circuit (PIC) products. The expectation is based on the rapid development of industry participation in multi-project wafer (MPW) runs. JePPIX roadmap addresses aspects of generic model in photonics and application of photonic ICs, technology, process design kit, packaging and testing aspects; addresses business opportunities, cost, market, private and public R&D investment, training and education. The business cases for many companies targeting Photonic ICs in novel or improved products are strong. A rapidly growing market for PIC designers is foreseen; the anticipated growth of the market will demand a rapidly growing number of PIC designs. A more than tenfold increase of the present design capacity will be required within the next few years. Training and educational activities must, therefore, have high priority. For foundries manufacturing generic PICs there will be an increasingly attractive business case as the market volume of PICs grows. 15

16 In the coming years a further increase in the performance and the maturity of the four JePPIX foundry platforms is foreseen (provided by Oclaro, Fraunhofer HHI, SMART Photonics and LioniX), to a level where the technology will be extremely competitive with application-specific processes. The development of process capabilities and performance will be accompanied by the development of sophisticated, fab-calibrated, Process Design Kits which will provide the users with models and tools for accurate and efficient design of Photonic ICs. Standardized packages are also being developed within the JePPIX community. Access to a high performance package available at a reasonable cost is equally important for rapid prototyping and product development. Through the application of the generic foundry model the entry costs for a PIC prototype are dramatically reduced, down to a level that is affordable for many SMEs and universities, while production costs for generic InP PICs are also highly competitive. The first generic PIC based products will become commercially available in Very significant investments in photonic foundries have been announced recently in the US. For Europe to retain its competitive edge, continued public and private investment is important. Funding should focus on raising awareness of the opportunities that Photonic ICs offer for novel or improved products for a wide range of applications, increasing training and education capacity and creating proper conditions for enabling PIC foundries to provide the required manufacturing services. JePPIX is playing a central role in the eco-system for foundry-based PIC development and manufacturing. Because of the large overlap in skills and tools for designing InP and TriPleX chips, and the increasing synergy between the two technologies in the field of packaging and hybrid platform technology, JePPIX is taking the role of brokering organization for both InP and TriPleX technology. JePPIX roadmap 2015 is available on the JePPIX website: The road to a multi-billion Euro market in Integrated Photonics JePPIX ROADMAP JePPIX training courses on photonic IC design and technology aspects By Katarzyna Ławniczuk (TU Eindhoven) JePPIX education activity in 2015 is focused on organization of three training courses on photonic IC design and technology aspects. Two intensive 5-day training courses have already been held in 2015, one in early June in Berlin and the second, 29 June 3 July at ETRI, Daejeon, Korea. A further 2-weeks course is planned: 26 October - 6 November 2015, TU Eindhoven. 16

17 The 2-weeks JePPIX training has a long history and is traditionally held by the COBRA Institute at the Eindhoven University of Technology, the Netherlands. This year it will be organized from October 26 th to November 6 th. The JePPIX training courses are a rare opportunity to not only study PIC design with the experts and get hands-on experience with various software tools, but also to study practical fab aspects and, ultimately, to get some of your designs built through JePPIX shared MPW runs. Furthermore it is a unique opportunity to network with experts in photonics field, from foundries, software providers and design houses. Details about the training and registration are available on the JePPIX website: 5-days intensive JePPIX training course on Photonic Integration Technology During June 8 12 this year, JePPIX organized 5-days of intensive training on Photonic Integration Technology, held at the Fraunhofer HHI, Berlin, Germany, being one of the JePPIX foundry partners offering semi-commercial access to their technology platforms. Fourteen participants attended the course, and some of them will prepare designs for their photonic ASICs in upcoming JePPIX MPW runs. The course was supported by Nanolab@TU/e; the software partners PhoeniX Software, Photon Design and Filarete; design houses BRIGHT Photonics and VLC Photonics; foundry partners SMART Photonics, Oclaro, Heinrich Hertz Institute, LioniX; packaging partners Linkra and Technobis IPPS. The training course provided an extensive hands-on session in using the photonics design kits of Fraunhofer HHI, Oclaro and SMART Photonics, implemented in PICWave from Photon Design, Aspic from Filarete, OptoDesigner from PhoeniX Software and VPIphotonics; with lots of opportunity for 1:1 coaching sessions. Participants were taught to automatically translate their circuits to foundry s on-specs mask (GDSII) files. Moreover, the training was a great opportunity to learn about photonic platforms and to gain insights into manufacturing processes and chip characterization. The course was a successful networking event with experts in photonics, from foundries, software providers and design houses. 17

18 Open letter to participants in PARADIGM MPW-runs With the closing of the PARADIGM project ( ), we would like to inform you about your access rights to the software tools and PDKs that you have used to make your design as participant in one of our MPW-runs. Some of you have received a short term license for PICWave, Aspic or OptoDesigner. These licenses have already expired. If you would like to keep using the tools, get in touch with the software vendor to receive your personal offer. In addition to the software tools, PDKs have been provided to enable you to design for the MPWs at Fraunhofer HHI and/or Oclaro. These PDKs have been developed for the PARADIGM project and the right to use them, which was granted to you under NDA, also ended at the close of the project (May 2015). The PARADIGM partners recognize that you may need access and use of the PARADIGM PDK after that date. Should you need access to the PDK, for example to evaluate test results, change your design to a new PDK or re-run a simulations or mask generation, the project partners of PARADIGM will endeavour to support you with this until the end of September After this date no further maintenance or support can be given for these (old) PARADIGM PDKs. Meanwhile Fraunhofer HHI (and soon Oclaro) has started offering MPWs through the brokering organisation JePPIX ( The PDKs that are required for these services are different and will be actively further developed as the capability of the platforms increases. Thank you for your support and feedback over the last four years. With kindest regards Dave Robbins and Twan Korthorst (PARADIGM project contacts) 18

19 14. About PARADIGM PARADIGM aims to create the foundations for a powerful, cost effective and versatile foundry platform in Europe. This will lead to a dramatic reduction of fabrication; packaging and testing costs as well as the development time of Application Specific Photonic ICs (ASPICs) based on Indium Phosphide (InP) and thereby pave the way for the breakthrough of the large-scale application of photonics in our daily lives. Covering the complete product creation process from idea to product, from research to manufacturing, PARADIGM targets the following areas: Technology convergence and roadmapping. To create methods and tools. To set up generic packaging and testing. To exploit and disseminate the project results. During the course of the project direct access for external users to the generic platforms is being provided, whilst they are in development, by offering both circuit fabrication and user support in four multiproject wafer (MPW) foundry cycles. Fact and Figures: Project reference: ICT Co-ordinator contact: Prof. M.K. (Meint) Smit m.k.smit@tue.nl Website: Timeline: Start date: 01/10/2010 End date: 31/05/2015 Budget: Total Cost: Partners: Technische Universiteit Eindhoven, Netherlands Willow Photonics Ltd, UK The Centre for Integrated Photonics, UK Oclaro Technology ltd, UK Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.v, (HHI and IZM), Germany Chalmers Tekniska Hoegskola AB, Sweden Filarete s.r.l., Italy PhoeniX BV, Netherlands Gooch & Housego (Torquay) Ltd, UK Photon Design Ltd, UK Alcatel-Thales III-V Lab, France University of Cambridge, UK Linkra S.R.L., Italy Politecnico di Milano, Italy Warsaw University of Technology, Poland Bright Photonics, Netherlands VLC Photonics, Spain EFFECT Photonics, Netherlands How to contact us: For further information about PARADIGM please look on our website, or contact: David Robbins (newsletter editor): dave.robbins@willowphotonics.co.uk Meint Smit: m.k.smit@tue.nl Twan Korthorst: twan.korthorst@phoenixbv.com JePPIX coordinator@jeppix.eu 19