160Gb/s Serial Line Rates in a Monolithic Optoelectronic Multistage Interconnection Network

Transcription

1 European Commission 7th Framework Programme: BONE Network of Excellence Building the Future Optical Network in Europe 160Gb/s Serial Line Rates in a Monolithic Optoelectronic Multistage Interconnection Network A. Albores-Mejia, K.A. Williams* F. Gomez-Agiz, S. Zhang, H.J.S. Dorren, X. Leijtens, T. de Vries, S. Oei, M. Heck, L. Augustin, R. Notzel, D.J. Robbins M.K. Smit * Also with Cambridge University Engineering Department 17th IEEE Symposium on High Performance Interconnects

2 Outline Nanosecond-timescale reconfigurable interconnection State of the art using III-V technology Scaling optoelectronic circuits Experiment Circuit fabrication Optical multiplexing Ultrahigh speed serial routing Conclusions and prospects Slide 2

3 Outline Nanosecond-timescale reconfigurable interconnection State of the art using III-V technology Scaling optoelectronic circuits Experiment Circuit fabrication Optical multiplexing Ultrahigh speed serial routing Conclusions and prospects Slide 3

4 Ultrafast photonic interconnects Data Vortex at Columbia University OSMOSIS program with IBM and Corning Tens of connections at tens of Gigabit/s per connection Ultrafast nanosecond reconfiguration with III-V switch technology Pros for III-V semiconductor optical amplifer gates Fast switching, ease of electrical control, massive bandwidth Cons: complex implementation using discrete photonic parts Packaging dominates cost, energy losses, time delays, control A need for photonic integration Slide 4

5 Progress in photonic integration Slide 5

6 Integrated photonic interconnects Integrated photonics proposed for a broad range of interconnections on-chip wiring on-board wiring backplanes routers telco Point to point parallel optics through to wavelength managed busses Focus here on optoelectronic switching decouple bandwidth and energy use broadband (multi-terahertz) fabrics low intrinsic delay and latency scalable with intrinsic gain HOTI , Beausoleil, HP courtesy IBM Zurich University of Cambridge Slide 6

7 Switch circuits Low divergence Y-branches Multimode interference switches Mach-Zehnder interferometer Directional couplers Range of circuits proposed with varying degree of fabrication complexity and tolerancing Crosstalk improved for non-interferometric switch solutions Limited data on high data rate transmission and routing Broadcast/select Slide 7

8 Switch circuits Scaling so far to 4 inputs 4 outputs with crossbar and broadcast architectures Serial line rates at 10Gb/s Signal degradation in ICs Architectures scaling poorly Monolithic multistage interconnection networks offering route to higher connections Slide 8

9 Multistage Interconnection Clos/broadcast&select hybrid network Trade off between number of stages and connection scaling x16 switch architecture demonstrated with 4x4 fabrics at 8λx10Gb/s with just 3.4dB penalty H. Wang et al., Optical Fibre Conference, 2009 Slide 9

10 Monolithic multistage interconnect Input Shuffle Output splitters network combiners First stage crossbars Levels of complexity increasing in current generation of integrated switching circuits Low power penalty (signal degradation) 0.2dB for single stage, 0.5dB for two stages negligible crosstalk penalty Good power penalty performance, but unclear what the physical limits are A. Mejia et al., Optical Fibre Conference, 2009 Second stage crossbars Slide 10

11 Scaling limits in photonics Wavelength multiplexed payload Variable optical attenuation for penalty measure Multi-stage interconnect network Variable optical attenuation for dynamic range Receiver model Numerical study into scaling Mixed time and frequency domain modelling allowing a mapping of low signal degradation Technique scanned to map large connectivity networks at 100Gb/s Williams et al., NuSOD Post Deadline, 2008 Bias current [ma] 16x16 photonic switch Power penalty [db] 10x10Gb/s db db Input power [dbm/channel] Slide 11

12 Scaling connectivity Input power per channel [dbm] Total number of power splitters per stage Number of input ports for 3 stage network 3 stage network with 2dB power penalty for 64x64 at 100Gb/s/path Motivation for further study into bandwidth versus number of stages BUT WDM complexity becoming considerable - of interest to also scale serial line rate (as in telco) 1dB power penalty 2dB power penalty Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Stage 3 Williams, K.A. et al, NUSOD, Postdeadline ThPD5 (2008) White I.H. et al., Journal of Optical Networking, 8 (2) (2009) Slide 12

13 Scaling capacity Power efficiency in photonics derived primarily from intrinsic massive bandwidth (tens of Terahertz) Optical multiplexing techniques allowing aggregation of electronic lanes but... Dense wavelength multiplexing carries a management overhead: Strict wavelength registration across the photonic network Strict thermal management Multiple power consuming transmitters Serial transmission for reduced hardware and management complexity High serial line rates so far unproven for integrated photonics Slide 13

14 Outline Nanosecond-timescale reconfigurable interconnection State of the art using III-V technology Scaling optoelectronic circuits Experiment Circuit fabrication Optical multiplexing Ultrahigh speed serial routing Conclusions and prospects Slide 14

15 Monolithic optoelectronic circuit Circuit fabricated at TU Eindhoven through the JePPIX Multi Project Wafer platform Active passive regrown wafer process on InGaAsP/InP Slide 15

16 Monolithic optoelectronic circuit active layer stack l passive layer stack Active epitaxial layer stack for switch elements Passive epitaxial layer stack for waveguide routing Slide 16

17 Active-passive regrowth: I To be retained as active To be regrown as passive Optical confinement layers Quantum well active layer stack Subtrate Starting wafer includes InP substrate and InGaAsP active layer Active islands defined photolithographically Mask layers not shown for clarity Slide 17

18 Active-passive regrowth: II Active layer stack selectively removed Slide 18

19 Active-passive regrowth: III Confinement layer infilled with no active quantum wells Slide 19

20 Active-passive regrowth: IV Cladding layers and electrical contact grown across full wafer Passive wiring area Active area Passive wiring area Arrays of active fingers of area 30 microns by 1000 microns formed across a regrown 2" wafer Technique commercially deployed for high end transceivers Slide 20

21 Active-passive crossbar Top view Orthoganol waveguide crossings for low crosstalk Full circuit comprised of six crossbars Two gates per active island for increased circuit density Planar waveguide splitters for fabrication resilience 1mm 2 circuit area per crossbar in current generation Circuit area reduced for a given wafer topology by co-locating gates Slide 21

22 Waveguide design Waveguide top view 1 2 Waveguide cross-sections 1' 2' Bar state 1 1' 2 2' Cross state 1 2' 2 1' Deep passive Shallow active Shallow passive Deep etch waveguides for tight bend radius (0.1mm) photonic wiring Shallow etch waveguides for amplifiers gates and waveguide crossings Two amplifiers per electrode Slide 22

23 Circuit 1 1 st stage 2 nd stage 3 rd stage 4 th stage input 4 output crossbar switch network implemented in four stages Network readily scalable to higher connectivity Input to output combination determines number of crossbars in path Exploits repeatable cell design Slide 23

24 Folded circuit k l Constraints from first generation regrown wafer required folding of circuit On-chip gain readily achieved - deduced from oscillations from uncoated facets - biased below oscillation point in this work 10 of 16 paths functional (mask error and short circuit restricts full function) Shortest and longest paths through two stages of crossbar and four stages of crossbar Slide 24

25 160Gb/s experimental testbed 40GHz optical pulse source Mach Zehnder modulator 40 Gb/s BERT PRBS x4 Fibre amp. 5nm optical filter Transmitter Polarisation control implemented but not drawn for clarity 50m SMF 12m DCF +7dBm aggregate power in fibre Circuit under test in separate lab Optical receiver 4 5nm optical filter Fibre amp. 5nm optical filter 50m SMF 8m DCF Receiver Fibre to chip coupling loss estimated at 6dB Slide 25

26 Time division multiplexing x 4 Optical data at 40Gb/s input coupler fine adjust monitor coupler coupler fine adjust monitor Optical data at 160Gb/s to switch output coupler 1.6 ns 0.8 ns 40GHz clock 80GHz clock 160GHz clock 3.2ns pattern length 1.6ns pattern lengths 0.8ns pattern lengths Pseudo random sequence generated directly at 40Gb/s Time interleaved with half sequence delays to generate true PRBS at 160Gb/s Slide 26

27 Time division demultiplexing 4 Serial data from switch circuit 160GHz line rate data 40GHz clock Electroabsorption modulator Variable delay to select time multiplex Opto electronic conversion Error rate measurement Test approach deployed sequencially tests interleaved tributary channels Full test schemes for both multiplexing and demultiplexing feasible through parallel optoelectronics at 40Gb/s Slide 27

28 Bit error rate: 40Gb/s Bit error rate at 40Gb/s 10-3 Input Two stages Four stages Mean received power [dbm] Power penalty used as a metric of system degradation Logarithmic relation indicates noise limited Crossbars Operating 2 stages currents 0.15dB 120 & 120 ma 4 stages 1.0 db 95 & 100 & 120 & 130mA Slide 28

29 Bit error rate: 160 Gb/s Gb/s Back to back Two stages Four stages Mean received power [dbm] Crossbars Operating 2 stages currents 0.9 db 120 & 120 ma 4 stages 1.3 db 95 & 100 & 120 & 130mA Increase in penalty with stage number attributable to noise build up Increase in penalty with line rate attributable to increased aggregate power Both may be reduced though circuit loss reduction Slide 29

30 160Gb/s time averaged time traces Input signal Two stage output signal Four stage output signal Optical power [linear units] Relative time [ps] Relative time [ps] Relative time [ps] Eye diagrams observed through an optical sampling front end to an electronic oscilloscope (Agilent Terascope) Clear eye opening for input signal and signals after two and four stages Slide 30

31 160Gb/s time averaged spectra Power spectral density [dbm/0.1nm] Input signal Two stage output signal Four stage output signal Wavelength [nm] Wavelength [nm] Wavelength [nm] Time averaged spectra with limited spectral evolution 5nm spectral width not yet exploiting the tens of nanometres bandwidth potentially available 160Gb/s x 4 paths = 3pJ/bit for crossbars 0.3W x 6 crossbars Slide 31

32 Outline Nanosecond-timescale reconfigurable interconnection State of the art using III-V technology Scaling optoelectronic circuits Experiment Circuit fabrication Optical multiplexing Ultrahigh speed serial routing Conclusions and prospects Slide 32

33 Conclusions and prospects Demonstration of monolithically integrated four stage photonic integrated circuit Scalable architecture additional connections feasible through additional crossbars route to lossless switching additional unused bandwidth for no additional energy cost First demonstration of 160Gb/s serial routing through optoelectronic crossbars 1.3dB power penalty for 4 stages Route towards massive bandwidth density integrated photonic signal processing Financial support through the Dutch STW program and the European Commission funded research frameworks Slide 33