Specifications GAL22V10

Transcription

1 Specifications GALV GALV High Performance E CMOS PLD Generic Array Logic FEATURES HGH PERFORMANCE E CMOS TECHNOLOGY ns Maximum Propagation Delay Fmax = 5 MHz 35 ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology ACTVE PULL-UPS ON ALL PNS COMPATBLE WTH STANDARD V DEVCES Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS V Devices 5% to 75% REDUCTON N POWER VERSUS BPOLAR 9mA Typical cc on Low Power Device 5mA Typical cc on Quarter Power Device E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) Year Data Retention TEN OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs PRELOAD AND POWER-ON RESET OF REGSTERS % Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON DESCRPTON FUNCTONAL BLOCK DAGRAM /CLK PROGRAMMABLE AND-ARRAY (3X) PN CONFGURATON RESET 6 6 PRESET /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q The GALV, at ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E ) floating gate technology to provide the highest performance available of any V device on the market CMOS circuitry allows the GALV to consume much less power when compared to bipolar V devices E technology offers high speed (<ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user The GALV is fully function/fuse map/parametric compatible with standard bipolar and CMOS V devices Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products n addition, erase/write cycles and data retention in excess of years are specified NC PLCC /CLK NC GALV Top View GND NC Vcc 6 /O/Q /O/Q /O/Q /O/Q 3 9 /O/Q /O/Q /O/Q NC /O/Q /O/Q /O/Q /CLK GND 6 DP GAL V 3 Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q Copyright 997 Lattice Semiconductor Corp All brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice LATTCE SEMCONDUCTOR CORP, 5555 Northeast Moore Ct, Hillsboro, Oregon 97, USA July 997 Tel (53) 6-; --SP-PLDS; FAX (53) 6-337; v_

2 Specifications GALV GALV ORDERNG NFORMATON Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALVD-LJ GALVC-5LJ GALVC-7LP 5 5 GALVC-7LJ 65 5 GALVB-7LP GALVB-7LJ GALVD-QP 55 GALVD-QJ 3 GALVD-LP, GALVC-LP or GALVB-LP 3 GALVD-LJ, GALVC-LJ or GALVB-LJ 5 55 GALVD-5QP or GALVB-5QP 55 GALVD-5QJ or GALVB-5QJ 3 GALVD-5LP or GALVB-5LP 3 GALVD-5LJ or GALVB-5LJ GALVD-5QP or GALVB-5QP 55 GALVD-5QJ or GALVB-5QJ 9 GALVD-5LP or GALVB-5LP 9 GALVD-5LJ or GALVB-5LJ Package -Lead PLCC -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic Dip -Pin PLCC ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALVC-7LP GALVC-7LJ GALVC-LP 6 GALVC-LJ 5 5 GALVD-5LP or G ALVB-5LP 5 GALVD-5LJ or GALVB-5LJ 5 GALVD-LP or G ALVB-LP 5 GALVD-LJ or GALVB-LJ GALVD-5LP or G ALVB-5LP 5 GALVD-5LJ or GALVB-5LJ Package -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC PART NUMBER DESCRPTON XXXXXXXX _ XX X X X GALVD GALVC GALVB Device Name Speed (ns) Grade Blank = Commercial = ndustrial L = Low Power Q = Quarter Power Power Package P = Plastic DP J = PLCC

3 Specifications GALV OUTPUT LOGC MACROCELL () The GALV has a variable number of product terms per Of the ten available s, two s have access to eight product terms (pins and 3, DP pinout), two have ten product terms (pins 5 and ), two have twelve product terms (pins 6 and ), two have fourteen product terms (pins 7 and ), and two s have sixteen product terms (pins and 9) n addition to the product terms available for logic, each has an additional product-term dedicated to output enable control The output polarity of each can be individually programmed to be true or inverting, in either combinatorial or registered mode This allows each output to be individually configured as either active high or active low The GALV has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP) These two product terms are common to all registered s The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen AR CLK D Q Q TO MUX SP TO MUX GALV OUTPUT LOGC MACROCELL () OUTPUT LOGC MACROCELL CONFGURATONS Each of the Macrocells of the GALV has two primary functional modes: registered, and combinatorial /O The modes and the output polarity are set by two bits (SO and S), which are normally controlled by the logic compiler Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page REGSTERED n registered mode the output pin associated with an individual is driven by the Q output of that s D-type flip-flop Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each, and can therefore be defined by a logic equation The D flip-flop s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array NOTE: n registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic /O, as can the combinatorial pins COMBNATORAL /O n combinatorial mode the pin associated with an individual is driven by the output of the sum term gate Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or productterm driven (dynamic /O) Feedback into the AND array is from the pin side of the output enable buffer Both polarities (true and inverted) of the pin are fed back into the AND array 3

4 Specifications GALV REGSTERED MODE AR AR D Q D Q CLK Q CLK Q SP SP ACTVE LOW ACTVE HGH S = S = S = S = COMBNATORAL MODE ACTVE LOW ACTVE HGH S = S = S = S =

5 Specifications GALV GALV LOGC DAGRAM / JEDEC FUSE MAP () 396 DP (PLCC) Package Pinouts ASYNCHRONOUS RESET (TO ALL REGSTERS) S 5 S 59 3 (7) (3) 3 () (5) 5 (6) 6 (7) 7 (9) () 9 () () S 5 S 5 S 5 S 53 S 5 S 55 S 56 S 57 S 5 S 59 S 5 S 5 S 5 S 53 S 5 S 55 S 56 S 57 SYNCHRONOUS PRESET (TO ALL REGSTERS) (6) (5) () 9 (3) () 7 () 6 (9) 5 () (7) (3) 3 (6) 6 6 5, 59 Electronic Signature 59, 59 Byte 7 Byte 6 Byte 5 Byte Byte 3 Byte Byte Byte M L SB S B 5

6 Specifications GALVD ABSOLUTE MAXMUM RATNGS () Supply voltage V CC -5 to +7V nput voltage applied -5 to V CC +V Off-state output voltage applied -5 to V CC +V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 5 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) RECOMMENDED OPERATNG COND Commercial Devices: Ambient Temperature (T A ) to +75 C Supply voltage (V CC ) with Respect to Ground +75 to +55V ndustrial Devices: Ambient Temperature (T A ) - to 5 C Supply voltage (V CC ) with Respect to Ground +5 to +55V DC ELECTRCAL CHARACTERSTCS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 3 MAX UNTS VL nput Low Voltage Vss 5 V VH nput High Voltage Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX) µa H nput or /O High Leakage Current 35V VN VCC µa VOL Output Low Voltage OL = MAX Vin = VL or VH 5 V VOH Output High Voltage OH = MAX Vin = VL or VH V OL Low Level Output Current 6 ma OH High Level Output Current 3 ma OS Output Short Circuit Current VCC = 5V VOUT = 5V T A = 5 C 3 3 ma COMMERCAL CC Operating Power VL = 5V VH = 3V L- 9 ma Supply Current ftoggle = 5MHz Outputs Open L ma L ma Q-/-5/ ma NDUSTRAL CC Operating Power VL = 5V VH = 3V L-5/-/ ma Supply Current ftoggle = 5MHz Outputs Open ) The leakage current is due to the internal pull-up on all pins See nput Buffer section for more information ) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems caused by tester ground degradation Characterized but not % tested 3) Typical values are at Vcc = 5V and TA = 5 C 6

7 Specifications GALVD AC SWTCHNG CHARACTERSTCS Over Recommended Operating Conditions TEST PARAM DESCRPTON UNTS COND MN MAX MN MAX MN MAX MN MAX MN MAX tpd A nput or /O to Comb Output ns tco A Clock to Output Delay ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 3 ns twl Clock Pulse Duration, Low 6 3 ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration ns tarr Asynch Reset to Clk Recovery Time 3 5 ns tspr Synch Preset to Clk Recovery Time 3 5 ns ) Refer to Switching Test Conditions section ) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section CAPACTANCE (T A = 5 C, f = MHz) COM COM COM / ND ND COM / ND SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5V, V = V C /O /O Capacitance pf V CC = 5V, V /O = V *Characterized but not % tested 7

8 Specifications GALVC ABSOLUTE MAXMUM RATNGS () Supply voltage V CC -5 to +7V nput voltage applied -5 to V CC +V Off-state output voltage applied -5 to V CC +V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 5 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) RECOMMENDED OPERATNG COND Commercial Devices: Ambient Temperature (T A ) to +75 C Supply voltage (V CC ) with Respect to Ground +75 to +55V ndustrial Devices: Ambient Temperature (T A ) - to 5 C Supply voltage (V CC ) with Respect to Ground +5 to +55V DC ELECTRCAL CHARACTERSTCS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 3 MAX UNTS VL nput Low Voltage Vss 5 V VH nput High Voltage Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX) µa H nput or /O High Leakage Current 35V VN VCC µa VOL Output Low Voltage OL = MAX Vin = VL or VH 5 V VOH Output High Voltage OH = MAX Vin = VL or VH V OL Low Level Output Current 6 ma OH High Level Output Current 3 ma OS Output Short Circuit Current VCC = 5V VOUT = 5V T A = 5 C 3 3 ma COMMERCAL CC Operating Power Supply Current VL = 5V VH = 3V L ma ftoggle = 5MHz Outputs Open L-7 9 ma L- 9 3 ma NDUSTRAL CC Operating Power Supply Current VL = 5V VH = 3V L-7/- 9 6 ma ftoggle = 5MHz Outputs Open ) The leakage current is due to the internal pull-up on all pins See nput Buffer section for more information ) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems caused by tester ground degradation Characterized but not % tested 3) Typical values are at Vcc = 5V and TA = 5 C

9 Specifications GALVC AC SWTCHNG CHARACTERSTCS PARAM TEST COND DESCRPTON Over Recommended Operating Conditions - UNTS MN MAX tpd A nput or /O to Combinatorial Output ns tco A Clock to Output Delay ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High ns twl Clock Pulse Duration, Low ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration ns tarr Asynch Reset to Clk Recovery Time 5 5 ns tspr Synch Preset to Clk Recovery Time 5 5 ns ) Refer to Switching Test Conditions section ) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section Characterized initially and after any design or process changes that may affect these parameters CAPACTANCE (T A = 5 C, f = MHz) COM COM/ND COM/ND -5-7 (PLCC) -7 (PDP) MN MAX MN MAX MN MAX COM - MN MAX ND SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5V, V = V C /O /O Capacitance pf V CC = 5V, V /O = V *Characterized but not % tested 9

10 Specifications GALVB ABSOLUTE MAXMUM RATNGS () Supply voltage V CC -5 to +7V nput voltage applied -5 to V CC +V Off-state output voltage applied -5 to V CC +V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 5 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) RECOMMENDED OPERATNG COND Commercial Devices: Ambient Temperature (T A ) to +75 C Supply voltage (V CC ) with Respect to Ground +75 to +55V ndustrial Devices: Ambient Temperature (T A ) - to 5 C Supply voltage (V CC ) with Respect to Ground +5 to +55V DC ELECTRCAL CHARACTERSTCS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 3 MAX UNTS VL nput Low Voltage Vss 5 V VH nput High Voltage Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX) µa H nput or /O High Leakage Current 35V VN VCC µa VOL Output Low Voltage OL = MAX Vin = VL or VH 5 V VOH Output High Voltage OH = MAX Vin = VL or VH V OL Low Level Output Current 6 ma OH High Level Output Current 3 ma OS Output Short Circuit Current VCC = 5V VOUT = 5V T A = 5 C 3 3 ma COMMERCAL CC Operating Power VL = 5V VH = 3V L-7 9 ma Supply Current ftoggle = 5MHz Outputs Open L-/ ma L ma Q-5/ ma NDUSTRAL CC Operating Power VL = 5V VH = 3V L-5/-/ ma Supply Current ftoggle = 5MHz Outputs Open ) The leakage current is due to the internal pull-up on all pins See nput Buffer section for more information ) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems caused by tester ground degradation Characterized but not % tested 3) Typical values are at Vcc = 5V and TA = 5 C

11 Specifications GALVB AC SWTCHNG CHARACTERSTCS PARAM TEST COND DESCRPTON Over Recommended Operating Conditions -7 MN MAX UNTS MN MAX MN MAX MN MAX MN MAX tpd A nput or /O to Comb Output ns tco A Clock to Output Delay ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns tsu Setup Time, SP before Clock 5 ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 3 ns twl Clock Pulse Duration, Low 6 3 ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration 5 5 ns tarr Asynch Reset to Clk Recovery Time 5 ns tspr Synch Preset to Clk Recovery Time 5 ns ) Refer to Switching Test Conditions section ) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section CAPACTANCE (T A = 5 C, f = MHz) COM COM COM / ND ND COM / ND SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5V, V = V C /O /O Capacitance pf V CC = 5V, V /O = V *Characterized but not % tested

12 Specifications GALV SWTCHNG WAVEFORMS NPUT or /O FEEDBACK COMBNATORAL OUTPUT Combinatorial Output VALD NPUT tpd NPUT or /O FEEDBACK CLK REGSTERED OUTPUT VALD NPUT tsu th tco / fmax (external fdbk) Registered Output NPUT or /O FEEDBACK t dis ten OUTPUT CLK nput or /O to Output Enable/Disable REGSTERED FEEDBACK / fmax (internal fdbk) tcf tsu fmax with Feedback tw h twl CLK / fmax (w/o fdbk) Clock Width NPUT or /O FEEDBACK DRVNG SP tsu th tspr NPUT or /O FEEDBACK DRVNG AR tarw CLK REGSTERED OUTPUT tco CLK REGSTERED OUTPUT tar tarr Synchronous Preset Asynchronous Reset

13 Specifications GALV fmax DESCRPTONS CLK CLK LOGC ARRAY REGSTER LOGC ARRAY REGSTER tsu tco fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco LOGC ARRAY tsu + th CLK REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl) This is to allow for a clock duty cycle of other than 5% tcf tpd fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu) The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above For example, the timing from clock to a combinatorial output is equal to tcf + tpd 3

14 Specifications GALV SWTCHNG TEST CONDTONS nput Pulse Levels GND to 3V nput Rise and D-, C-5 5ns % 9% Fall Times D-/-5/-/-5 ns % 9% B & C-7/- B-5/-/-5 3ns % 9% nput Timing Reference Levels 5V Output Timing Reference Levels 5V Output Load See Figure 3-state levels are measured 5V from steady-state active level GALVD- Output Load Conditions (see figure below) Test Condition R CL A 5Ω 5pF B Active High 5Ω 5pF Active Low 5Ω 5pF C Active High 5Ω 5pF Active Low 5Ω 5pF +5V Output Load Conditions (except D-) (see figure below) Test Condition R R CL TEST PONT R A 3Ω 39Ω 5pF B Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF C Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF FROM OUTPUT (O/Q) UNDER TEST Z = 5Ω, CL* +5V R FROM OUTPUT (O/Q) UNDER TEST TEST PONT R C * L *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE

15 Specifications GALV ELECTRONC SGNATURE An electronic signature (ES) is provided in every GALV device t contains 6 bits of reprogrammable memory that can contain user-defined data Some uses include user D codes, revision numbers, or inventory control The signature data is always available to the user independent of the state of the security cell The electronic signature is an additional feature not present in other manufacturers' V devices To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor V device type when compiling a set of logic equations n addition, many device programmers have two separate selections for the device, typically a GALV and a GALV-UES (UES = User Electronic Signature) or GALV-ES This allows users to maintain compatibility with existing V designs, while still having the option to use the GAL device's extra feature The JEDEC map for the GALV contains the 6 extra fuses for the electronic signature, for a total of 59 fuses However, the GALV device can still be programmed with a standard V JEDEC map (5 fuses) with any qualified device programmer SECURTY CELL A security cell is provided in every GALV device to prevent unauthorized copying of the array patterns Once programmed, this cell prevents further read access to the functional bits in the device This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed The Electronic Signature is always available to the user, regardless of the state of this control cell LATCH-UP PROTECTON GALV devices are designed with an on-board charge pump to negatively bias the substrate The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching DEVCE PROGRAMMNG OUTPUT REGSTER PRELOAD When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc) To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (ie, illegal) state into the registers Then the machine can be sequenced and the outputs tested for correct next state conditions The GALV device includes circuitry that allows each registered output to be synchronously set either high or low Thus, any present state condition can be forced for test sequencing f necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically NPUT BUFFERS GALV devices are designed with TTL level compatible input buffers These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices The input and /O pins also have built-in active pull-ups As a result, floating inputs will float to a TTL high (logic ) However, Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to an adjacent active input, Vcc, or ground Doing so will tend to improve noise immunity and reduce cc for the device (See equivalent input and /O schematics on the following page) nput Current (ua) Typical nput Current 3 5 nput Voltage (Volts) GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section) Complete programming of the device takes only a few seconds Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle 5

16 Specifications GALV POWER-UP RESET Vcc Vcc (min) tsu CLK twl NTERNAL REGSTER Q - OUTPUT tpr nternal Register Reset to Logic "" ACTVE LOW OUTPUT REGSTER Device Pin Reset to Logic "" ACTVE HGH OUTPUT REGSTER Device Pin Reset to Logic "" Circuitry within the GALV provides a reset signal to all registers during power-up All internal registers will have their Q outputs set low after a specified time (tpr, µs MAX) As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins This feature can greatly simplify state machine design by providing a known state on power-up The timing diagram for power-up is shown below Because of the asynchronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GALV First, the Vcc rise must be monotonic Second, the clock input must be at static TTL level as shown in the diagram during power up The registers will reset within a maximum of tpr time As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met The clock must also meet the minimum pulse width requirements NPUT/OUTPUT EQUVALENT SCHEMATCS PN PN Feedback (Vref Typical = 3V) Active Pull-up Circuit Vcc Active Pull-up Circuit (Vref Typical = 3V) Vcc ESD Protection Circuit Vref Vcc Tri-State Control Vcc Vref PN Data Output PN ESD Protection Circuit Feedback (To nput Buffer) Typical nput Typical Output 6

17 Specifications GALV GALVD-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp Normalized Tco Normalized Tco 5 95 Normalized T Normalized T su Temperature (deg C) Temperature (deg C) Temperature (deg C) 5 Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) - - Delta Tco (ns) Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) Delta Tco (ns) Output Loading (pf) Output Loading (pf) 3 7

18 Specifications GALV GALVD-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V) Voh (V) 3 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq 3 Normalized cc 9 Normalized cc 9 Normalized cc Temperature (deg C) Frequency (MHz) 6 Delta cc vs Vin ( input) nput Clamp (Vik) 5 Delta cc (ma) Vin (V) ik (ma) Vik (V)

19 Specifications GALV GALVD- AND SLOWER: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc 5 Normalized Tpd 5 95 Normalized Tco 5 95 Normalized Tsu Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp Normalized Tpd Temperature (deg C) Normalized Tco Temperature (deg C) Normalized Tsu Temperature (deg C) Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) - - Delta Tco (ns) Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) 6 - Delta Tco (ns) Output Loading (pf) Output Loading (pf) 9

20 Specifications GALV GALVD- AND SLOWER: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol (V) 6 Vol vs ol ol (ma) Voh (V) Voh vs oh 6 oh (ma) Voh (V) Voh vs oh 3 5 oh (ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq 35 Normalized cc 9 Normalized cc Normalized cc Temperature (deg C) Frequency (MHz) Delta cc (ma) Delta cc vs Vin ( input) Vin (V) ik (ma) nput Clamp (Vik) Vik (V)

21 Specifications GALV GALVC-5/-7/-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd 9 PT H->L PT L->H Normalized Tco 9 Normalized Tsu 9 PT H->L PT L->H Normalized Tpd vs Temp 3 Normalized Tco vs Temp Normalized Tsu vs Temp Normalized Tpd 9 PT H->L PT L->H Normalized Tco 9 Normalized Tsu 3 9 PT H->L PT L->H Temperature (deg C) Temperature (deg C) Temperature (deg C) Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tco (ns) Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) Output Loading (pf) Delta Tco (ns) Output Loading (pf)

22 Specifications GALV GALVC-5/-7/-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh 3 5 Vol (V) Voh (V) 3 Voh (V) ol (ma) oh(ma) 3 3 oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq 3 Normalized cc 9 Normalized cc 9 Normalized cc Temperature (deg C) Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) 6 ik (ma) Vin (V) Vik (V)

23 Specifications GALV GALVB-7/-/-5/-5L: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd 9 PT H->L PT L->H Normalized Tco 9 Normalized Tsu 9 PT H->L PT L->H Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp 3 3 Normalized Tpd 9 PT H->L PT L->H Normalized Tco 9 Normalized Tsu 3 9 PT H->L PT L->H Temperature (deg C) Temperature (deg C) Temperature (deg C) 5 Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tco (ns) Number of Outputs Switching Number of Outputs Switching Delta Tpd (ns) 6 - Delta Tpd vs Output Loading Output Loading (pf) Delta Tco (ns) 6 - Delta Tco vs Output Loading Output Loading (pf) 3

24 Specifications GALV GALVB-7/-/-5/-5L: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V) Voh (V) 3 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq Normalized cc 9 Normalized cc 9 Normalized cc Temperature (deg C) Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) Vin (V) ik (ma) Vik (V)

25 Specifications GALV GALVB-5/-5Q: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd 9 Normalized Tco 9 Normalized Tsu Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp 3 3 Normalized Tpd 9 Normalized Tco 9 Normalized Tsu Temperature (deg C) Temperature (deg C) Temperature (deg C) 5 Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tco (ns) Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) 6 Delta Tco (ns) Output Loading (pf) Output Loading (pf) 5

26 Specifications GALV GALVB-5/-5Q: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V) 6 Voh (V) 3 Voh (V) ol (ma) oh(ma) 3 3 oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq 3 Normalized cc 9 Normalized cc 9 Normalized cc Temperature (deg C) Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) Vin (V) ik (ma) Vik (V) 6

27 Copyright 997 Lattice Semiconductor Corporation E CMOS, GAL, ispgal, ispls, pls, pds, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp, L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation Generic Array Logic, SP, ispate, ispcode, ispdownload, ispds, ispds+, ispgds, ispgdx, isphdl, ispjtag, ispstarter, ispstream, isptest, ispturbo, ispvector, ispverilog, ispvhdl, Latch-Lock, LHDL, pds+, RFT, Total SP and Twin GLB are trademarks of Lattice Semiconductor Corporation SP is a service mark of Lattice Semiconductor Corporation All brand names or product names mentioned are trademarks or registered trademarks of their respective holders Lattice Semiconductor Corporation (LSC) products are made under one or more of the following US and international patents:,76,76 US,,766,569 US,,33,66 US,,5, US,,55,95 US,,79,6 US,,7,39 US,,96,96 US, 5,3,57 US, 5,3,9 US, 5,6,679 US, 5,9,3 US, 5,,556 US, 5,3,35 US, 5,3,36 US, 5,37, US, 5,5,6 US, 5,5,69 US, 5,7,666 US, 5,,96 US, 5,95,95 US, 5,39,79 US, 5,33,59 US, 5,336,95 US, 5,353,6 US, 5,357,56 US, 5,359,573 US, 5,39,33 US, 5,39,37 US, 5,,55 US, 5,,39 US, 5,93,5 US, 99 EP, 9677B EP, 677 EP, 9677 UK, 99 GB, 9677 WG, P3667- WG LSC does not represent that products described herein are free from patent infringement or from any third-party right The specifications and information herein are subject to change without notice Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current LSC warrants performance of its products to current and applicable specifications in accordance with LSC s standard warranty Testing and other quality control procedures are performed to the extent LSC deems necessary Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements LSC assumes no liability for applications assistance, customer s product design, software performance, or infringements of patents or services arising from the use of the products and services described herein LSC products are not authorized for use in life-support applications, devices or systems nclusion of LSC products in such applications is prohibited LATTCE SEMCONDUCTOR CORPORATON 5555 Northeast Moore Court Hillsboro, Oregon 97 USA Tel: (53) 6- FAX: (53) July 997