Corporate presentation. CNES Décembre

Transcription

1 Corporate presentation

2 The SERMA group 2008 SERMA Group Turnover : 45 M SERMA Group 446 p 2008 ID MOS Turnover : 5.65 M NEW Subsidiary since 2009 august AXENEON Nuremberg 75 p ID MOS R & D + Production 16 p (2009) SERMA «Ingénierie» 200 p SERMA «Technologies» 230 p Integrated circuits Project management Boards & equipements Semiconductor and Material expertise German ID MOS sales office Stuttgart USA distributor sales office Framingham 2

3 ID MOS at a glance Fabless Semiconductor company Headquartered in Bordeaux (France) Subsidiary of SERMA Group Turnover K Euro in 2008 (13p) 9 Millions of pcs sold in 2008 ( through 53 customers) Core busines : Mixed-signal microelectronics Embedded microelectronics (High temp ASIC tech available 225 C) Obsolescence management Supply-chain (wafer purchase, probing, packaging, test & packing) Pan-European company High-level engineering expertise 3

4 ID MOS Offer : Integrated Circuits Integrated Custom circuits Development of mixed-signal ICs Supply-Chain (production management in fabless mode) Integrated circuits ASSP products (1) Radio-frequency (ISM band) and RFID (125 Khz & Mhz) Integrated circuits ASSP & ASIC products (2) Obsolete components Analog, Mixed & digital Target Applications Aeronautic, Railway & Industry Quantities / year 200 p to 10 Kp / y 100 Kp / y Design Schedule 6 months < DS < 16 months DO 254 Design Assurance Level a, b or c ITAR free (foundry in EU) Engineering services IP Development and supply, extreme environment Specific technical engineering, test & qualification 4

5 Example 1 : TMS % Compatible Digital functions : 16 Bits Micro-controller Embedded ROM : 2048 Bytes Embedded Ram : 128 Bytes 4 MHz Internal Oscillator Package : PDIL40 Techno : CMOS 0,6µm Surface : 13mm² (1P2M) 5

6 Example 2 : VME CONTROLLER CYPRESS VIC068 : IM313 ID MOS ref 100% compatible with the obsolete VIC068A circuit (cypress) Complete VMEbus interface Controller and Arbiter Complete Master/slave capability Interleave Block transfers support Interrupt support Arbitration support Techno : CMOS 0,6µm Surface gates : 36mm² (Pad Limited) Package: Plastic : PQFP160 TQFP144 Céramic : CQFP160 - PGA144 Temperature range mil, ind MILSTD883 reliability level available 6

7 Example 3 : Mixed-signal example / ASIC Analogue functions : Laser Power Driver. Photodiode amplifier. Integrated quartz oscillator (40Mhz) Driver of 2D µmirrors. Level Shifter (3,3/5 5/3,3) Integrated flash 8bits ADC. Digital functions : Supervisor 20KGates RAM 24K*8, Techno : CMOS 0.6µm 2P3M HR Surface : 43mm² Package : QFP64 - µbga90 7

8 CIRCUIT CLONING Context summary Circuit development process Circuit validation process Synthesis / Conclusion 8

9 Context summary REDESIGN = Ultimate Solution The components are not manufactured anymore The manufacturers/suppliers do not ensure any follow-up and do not want to invest any more on this project. The components do not exist any more on the various supplying market The components stored over a long period present a drift in time Prohibitive board redesign and qualification costs. 9

10 YOUR NEEDS IM % COMPATIBLE ELECTRICALLY FUNCTIONALLY PACKAGING PIN TO PIN 10

11 REDESIGN PROCESS Refence samples Data-Sheet Databook STEP1 (option) Refence samples Characterisation OK OK! "# $ "%& &' ( $ " ) *"+,+$ "# - $! &. ( - * "+,+$ & "# & "#- STEP2 Development: VHDL description Gate level Netlist VHDL Patterns Tabular formats MA_en<='0'; B_en<='0'; ALU_oper<=ALU_inactive; RAZ<='0'; if ( IR(15 downto 12) = "1010" ) then if ST2="0000" then case ST1 is when "00001" => MA_en<='1'; ALU_oper<=ALU_WP_Gs ;.. end case; Layout VIC068A TMS9940 STEP3 STEP4 INTERMEDIATE SYSTEM VALIDATION with FPGA(application) VIC068A TMS9940 STEP5 FABRICATION CYCLE OK OK OK (Mandatory) FINAL SYSTEM VALIDATION with Cloned circuit 100% compatible STEP6 (option) Wafer sort Assembly Final Test 11

12 COMPONENT REDESIGN Context summary Component development process Component validation process Synthesis / Conclusion 12

13 OBJECTIVES To design a certified copy has seen from the electronic system To reproduce qualities and functional defects of the component State of the art desgin method (VHDL), and modern technologies To ensure the technological independence of the circuit (wide durability) 13

14 INTEGRATED CIRCUIT STRUCTURE 1 Circuit = 2 components Periphery Core 14

15 INTEGRATED CIRCUIT STRUCTURE Expected critical points Bugs (behaviour different from the datasheet) Code program (availability of the source code) Core Cycle-to-Cycle functional compatibility 15

16 INTEGRATED CIRCUIT STRUCTURE Expected critical points Output dynamic transitions Input/Output Levels Periphery Input structure Input/Output Impedance Oscillator characteristic 16

17 TECHNOLOGY INTERFACING Periphery Functional interactions Core Electrical Interactions 17

18 DESIGN FLOW TMS 99xx Environment analysis Datasheet Dynamic characterization of the standards Technological analysis of the standards FPGA TMS99xx VHDL FPGA PROM Specific design of the circuit periphery Biblio Kick-off meeting => Deliverables : TPS PDP QP Dynamic Characterization : (OPTION) Consumption, I/O levels, Drive, functional Technological analysis: (MANDATORY) Dynamic, static, functional Electronic Environment Analysis (MANDATORY) Ground layer, tracks(topology), Supply, Drive,.. Development : Modelisation and simulation VHDL : Very high speed integrated circuit Hardware Description Language => Deliverables : DSR, TEST, Functional Validation FPGA : Field Programmable Gate Array ASIC 99xx Production : Final component ASIC : Application Specific Integrated Circuit 18

19 COMPONENT REDESIGN COMPONENT VALIDATION Context summary Component development process Component validation process Synthesis / Conclusion 19

20 VALIDATION PROCESS Functional development (VHDL) SIMULATOR FPGA Validation FPGA IC Prototype Validation Serie Final Validation APPLICATION TESTS : Functional tests Electrical (signal measurement), Environmental (thermal, EMC) APPLICATION ENVIRONMENT TEST ASIC Validation 20

21 8 6 VALIDATION PROCESS : FPGA STEP?? FPGA?? CARTE *#/*/ DIAGNOSIS Baby board : FPGA Functionality check before production Check on the real application Simulation Bench Pattern Test Procedures Simulation Bench Pattern TESTS ON ALL BOARDS : Checking the IC functions Checking the interactions between components (electrical parameters) FPGA SYSTEME OPERATIONNEL COMMUNICATIONS INTERNES (BUS) FPGA FPGA SYSTEM TEST PLATFORM : to put in operational situation the components to check compatibilities of the technology mixed E/S COMMUNICATIONS EXTERNES DIAGNOSTIC 21

22 COMPONENT REDESIGN Context summary ASIC development process ASIC validation process Synthesis / Conclusion 22

23 Obsolete components available, redesigned & produced by ID MOS Cypress family : VIC068 Texas family : TMS9940 / TMS9901 / TMS9981 Motorola family : MC6802 DO254 dal-a, EF4442 DO254 dal-b, MC68HCXXX under development MHS family : 80C51 / 82C54 / 82C55 / 82C51 / 82C59 / 85C30 ACTEL & XILINX FPGA : 10X0-12XX, 30XX ASICs & other standard products : 23

24 SYNTHESIS / CONCLUSION The process of a digital circuit involves by a double approach TECHNOLOGY analysis (system level) IC/ASIC DEVELOPMENT : Digital design Analog Design : Technology independent (VHDL ) : Technology dependent. ASIC approach for std products makes it possible to consider the double problem of interfacing : TECHNOLOGY INTERFACE (analog periphery measurement: current drive, noise, propagation delay, ) PHYSICAL INTERFACE (pin-to-pin compatible) The Re-design introduces better performances in term of THERMAL BEHAVIOUR CEM, CONSUMPTION and RELIABILITY (ageing of the circuits) 24