IDT7133SA/LA IDT7143SA/LA

Transcription

1 HIGH PEED 2K X 16 DUA-PORT RAM IDT7133A/A IDT7143A/A Features High-speed access Military: 3//7/9 (max.) Industrial: / (max.) Commercial: //3/4//7/9 (max.) ow-power operation IDT7133/43A Active: 1mW (typ.) tandby: mw (typ.) IDT7133/43A Active: mw (typ.) tandby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port MATER IDT7133 easily expands data bus width to 32 bits or more using AVE IDT7143 On-chip port arbitration logic (IDT7133 only) BUY output flag on IDT7133; BUY input on IDT7143 Fully asynchronous operation from either port Battery backup operation 2V data retention TT-compatible; single V (±1%) power supply Available in 68-pin ceramic PGA, Flatpack, PCC and 1- pin TQFP Military product compliant to MI-PRF-383 QM Industrial temperature range ( 4 C to +8 C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WUB CE R/WRUB CER R/WB R/WRB OE OER I/O8 -I/O I/O - I/O7 I/O CONTRO I/O CONTRO I/O8R -I/OR I/OR -I/O7R BUY (1) BUYR (1) A1 A ADDRE DECODER MEMORY ARRAY ADDRE DECODER A1R AR CE ARBITRATION OGIC (IDT7133 ONY) CER 2746 drw 1 NOTE: 1. IDT7133 (MATER): BUY is open drain output and requires pull-up resistor. IDT7143 (AVE): BUY is input. 13 Integrated Device Technology, Inc. 1 JANUARY 12 DC 2746/14

2 High-peed 2K x 16 Dual-Port RAM Description The IDT7133/7143 are high-speed 2K x 16 Dual-Port tatic RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a MATER Dual-Port RAM together with the IDT7143 AVE Dual-Port in 32-bit-or-more word width systems. Using the IDT MATER/AVE Dual-Port RAM approach in 32-bit-or-wider memory system applicatio results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, Pin Configuratio (1,2,3) address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMO high-performance technology. ow-power (A) versio offer battery backup data retention capability, with each port typically couming µw for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PCC and 1-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MI-PRF-383 QM, making it ideally suited to military temperature applicatio demanding the highest level of performance and reliability. INDEX I/O8 I/O7 I/O6 I/O I/O4 I/O3 I/O2 I/O1 I/O VCC (1) R/WUB R/WB OE A1 A9 A8 A7 I/O9 I/O1 I/O11 I/O12 I/O13 I/O14 I/O VCC (1) GND (2) I/OR I/O1R I/O2R I/O3R I/O4R I/OR I/O6R I/O7R IDT7133/43 J68-1 / F68-1 (4) 68-Pin PCC/Flatpack Top View () A6 A A4 A3 A2 A1 A BUY CE CER BUYR AR A1R A2R A3R A4R AR I/O8R I/O9R I/O1R I/O11R I/O12R I/O13R I/O14R I/OR GND (2) R/WRUB R/WRB OER A1R A9R A8R A7R A6R 2746 drw 2 Index I/O9 I/O8 I/O7 I/O6 I/O I/O4 I/O3 I/O2 GND I/O1 I/O OE VCC R/WB CE R/WUB A1 A9 A8 A7 A6 1. Both VCC pi must be connected to the power supply to eure reliable operation. 2. Both GND pi must be connected to the ground supply to eure reliable operation. 3. J68-Package body is approximately.9 in x.9 in x.17 in. F68-Package body is approximately 1.18 in x 1.18 in x.16 in. PN1-Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram.. This text does not indicate orientation of the actual part-marking. I/O1 I/O11 I/O12 I/O13 GND I/O14 I/O VCC GND I/OR I/O1R I/O2R VCC I/O3R I/O4R I/OR I/O6R IDT7133/43PF PN1-1 (4) 1-Pin TQFP Top View () A A4 A3 A2 A1 A BUY GND BUYR AR A1R A2R A3R A4R , 2746 drw 3 I/O7R I/O8R I/O9R I/O1R I/O11R I/O12R I/O13R I/O14R GND I/OR OER R/WRB GND CER R/WRUB A1R A9R A8R A7R A6R AR

3 High-peed 2K x 16 Dual-Port RAM Pin Configuratio (1,2,3) (con't.) 11 1 A A A3 A1 BUY CER AR A2R A4R A8 A7 A4 A2 A CE BUYR A1R A3R AR A6R 9 A1 4 A A8R A7R 8 7 R/WB 6 OE 3 31 A1R A9R VCC (1) 61 I/O1 63 I/O3 8 R/WUB 6 I/O 62 I/O2 IDT7133/43G GU68-1 (4) 68-Pin PGA Top View () R/WRB OER GND (2) R/WRUB 24 I/O14R I/OR 4 6 I/O 64 I/O I/O12R I/O13R 3 67 I/O7 66 I/O6 21 I/O1R I/O11R 2 68 I/O8 1 I/O9 3 I/O11 I/O13 7 I/O 9 GND (2) 11 I/O1R 13 I/O3R I/OR 18 I/O8R 19 I/O9R 1 2 I/O1 4 I/O12 6 I/O14 8 VCC (1) 1 I/OR 12 I/O2R 14 I/O4R 16 I/O6R 17 I/O7R Pin 1 Designator A B C D E F G H J K 1. Both VCC pi must be connected to the power supply to eure reliable operation. 2. Both GND pi must be connected to the ground supply to eure reliable operation. 3. Package body is approximately 1.18 in x 1.18 in x.16 in. 4. This package code is used to reference the package diagram.. This text does not indicate orientation of the actual part-marking drw 4 Pin Names eft Port Right Port Names CE CER Chip Enable R/WUB R/WRUB Upper Byte Read/Write Enable R/WB R/WRB ower Byte Read/Write Enable OE OER Output Enable A - A1 AR - A1R Address I/O - I/O I/OR - I/OR Data Input/Output BUY BUYR Busy Flag VCC GND Power Ground 2746 tbl

4 High-peed 2K x 16 Dual-Port RAM Absolute Maximum Ratings (1) ymbol Rating Commercial & Industrial VTERM (2) TBIA TTG PT IOUT Terminal Voltage with Respect to GND Temperature Under Bias torage Temperature Power Dissipation DC Output Current Military Unit -. to to +7. V - to +1-6 to +13 o C -6 to + -6 to + o C W ma 2746 tbl 2 1. tresses greater than those listed under ABOUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 1% for more than % of the cycle time or 1 maximum, and is limited to < ma for the period of VTERM > Vcc + 1%. Maximum Operating Temperature and upply Voltage (1,2) Grade Ambient Temperature GND 1. This is the parameter TA. This is the "itant on" case temperature. Recommended DC Operating Conditio Vcc Military - O C to +1 O C V.V + 1% Commercial O C to +7 O C V.V + 1% Industrial -4 O C to +8 O C V.V + 1% 2746 tbl 4 ymbol Parameter Min. Typ. Max. Unit VCC upply Voltage 4... V GND Ground V VIH Input High Voltage (2) V VI Input ow Voltage -. (1).8 V Capacitance (TA = + C, f = 1.mhz) ymbol Parameter (1) Conditio (2) Max. Unit CIN Input Capacitance VIN = 3dV 11 pf COUT Output Capacitance VOUT = 3dV 11 pf 2746 tbl 3 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from V to 3V or from 3V to V. 1. VI (min.) = -1.V for pulse width less than VTERM must not exceed Vcc + 1% tbl DC Electrical Characteristics Over the Operating Temperature and upply Voltage Range (Either port, VCC =.V ± 1%) 7133A 7143A 7133A 7143A ymbol Parameter Test Conditio Min. Max. Min. Max. Unit II Input eakage Current (1) VCC =.V, VIN = V to VCC IO Output eakage Current CE = VIH, VOUT = V to VCC 1 µa 1 µa VO Output ow Voltage (I/O-I/O) IO = 4mA.4.4 V VO Open Drain Output ow Voltage (BUY) IO = 16mA.. V VOH Output High Voltage IOH = -4mA V NOTE: 1. At Vcc < 2.V, input leakages are undefined tbl

5 High-peed 2K x 16 Dual-Port RAM DC Electrical Characteristics Operating Temperature and upply Voltage Range (2) (VCC =.V ± 1%) 7133X 7143X Com'l Only 7133X 7143X Com'l & Ind 7133X3 7143X3 Com'l & Military ymbol Parameter Test Condition Version Typ. (1) Max. Typ. (1) Max. Typ. (1) Max. Unit ICC Dynamic Operating CE = VI, Outputs Disabled COM' ma Current (Both Ports Active) f = fmax (3) MI & IND IB1 IB2 IB3 IB4 tandby Current (Both Ports - TT evel Inputs) tandby Current (One Port - TT evel Inputs) Full tandby Current (Both Ports - CMO evel Inputs) Full tandby Current (One Port - CMO evel Inputs) CE and CER = VIH f = fmax (3) CE"A" = VI and CE"B" = VIH (4) f=fmax (3) Active Port Outputs Disabled Both Ports CE and CER > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = (4) CE"A" <.2V and CE"B" > VCC -.2V () VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled f = fmax (3) COM' MI & IND COM' MI & IND COM' MI & IND COM' MI & IND ma ma ma ma 2746 tbl 7a 7133X4 7143X4 Com'l Only 7133X 7143X Com'l, Ind & Military 7133X7/9 7143X7/9 Com'l & Military ymbol Parameter Test Condition Version Typ. (1) Max. Typ. (1) Max. Typ. (1) Max. Unit ICC Dynamic Operating CE = VI, Outputs Disabled COM' ma Current (Both Ports Active) f = fmax (3) MI & IND IB1 IB2 IB3 IB4 tandby Current (Both Ports - TT evel Inputs) tandby Current (One Port - TT evel Inputs) Full tandby Current (Both Ports - CMO evel Inputs) Full tandby Current (One Port - CMO evel Inputs) CE and CER = VIH f = fmax (3) CE"A" = VI and CE"B" = VIH (4) f=fmax (3) Active Port Outputs Disabled Both Ports CE and CER > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = (4) CE"A" <.2V and CE"B" > VCC -.2V () VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled f = fmax (3) COM' MI & IND COM' MI & IND COM' MI & IND COM' MI & IND ma ma ma ma 2746 tbl 7b 1. VCC = V, TA = + C for Typ., and are not production tested. ICCDC = 18mA (typ.) 2. 'X' in part number indicates power rating (A or A) 3. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ trc, and using AC Test Conditio" of input levels of GND to 3V. 4. f = mea no address or control lines change. Applies only to inputs at CMO level standby.. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.42

6 High-peed 2K x 16 Dual-Port RAM Data Retention Characteristics (A Version Only) VC =.2V, VHC = VCC -.2V 7133A/7143A ymbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention VCC = 2V 2. V ICCDR Data Retention Current CE > VHC MI. & IND. 1 4 µa VIN > VHC or < VC COM'. 1 tcdr (3) Chip Deselect to Data Retention Time V tr (3) Operation Recovery Time trc (2) V 1. Vcc = 2V, TA = + C, and are not production tested. 2. trc = Read Cycle Time 3. This parameter is guaranteed by device characterization but is not production tested tbl 8 Data Retention Waveform DATA RETENTION MODE VCC 4.V VDR > 2V 4.V CE tcdr VIH VDR VIH tr 2746 drw AC Test Conditio Input Pulse evels GND to 3.V V Input Rise/Fall Times Max. 1Ω Input Timing Reference evels 1.V DATAOUT Output Reference evels Output oad 1.V Figures 1, 2 and 3 77Ω 3pF 2746 tbl 9 Figure 1. AC Output Test oad V V 1Ω 27Ω DATAOUT BUY 77Ω pf* 3pF 2746 drw 6 Figure 2. Output oad (for tz, thz, twz, tow) *Including scope and jig Figure 3. BUY Output oad (IDT7133 only)

7 High-peed 2K x 16 Dual-Port RAM AC Electrical Characteristics Over the Operating Temperature and upply Voltage (3) 7133X 7143X Com'l Only 7133X 7143X Com'l & Ind 7133X3 7143X3 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCE trc Read Cycle Time 3 taa Address Access Time 3 tace Chip Enable Access Time 3 taoe Output Enable Access Time 12 toh Output Hold from Address Change tz Output ow-z Time (1,2) thz Output High-Z Time (1,2) 12 tpu Chip Enable to Power Up Time (2) tpd Chip Disable to Power Down Time (2) 2746 tbl 1a 7133X4 7143X4 Com'l Only 7133X 7143X Com'l, Ind & Military 7133X7/9 7143X7/9 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. READ CYCE Unit trc Read Cycle Time 4 7/9 taa Address Access Time 4 7/9 tace Chip Enable Access Time 4 7/9 taoe Output Enable Access Time 3 4/4 toh Output Hold from Address Change / tz Output ow-z Time (1,2) / thz Output High-Z Time (1,2) / tpu Chip Enable to Power Up Time (2) / tpd Chip Disable to Power Down Time (2) / 1. Traition is measured mv fromow or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (A or A) tbl 1b

8 High-peed 2K x 16 Dual-Port RAM TIMING WAVEFORM OF READ CYCE NO. 1, EITHER IDE () ADDRE taa trc DATAOUT toh PREVIOU DATA VAID toh DATA VAID BUYOUT tbdd (3,4) 2746 drw 7 TIMING WAVEFORM OF READ CYCE NO. 2, EITHER IDE () (4) tace CE OE (4) taoe (1) tz (2) thz (2) thz CURRENT DATAOUT ICC IB tpu % (1) tz VAID DATA 2746 drw 8 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deasserted first, OE or CE. 3. tbdd delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operatio, BUY has no relatiohip to valid output data. 4. tart of valid data depends on which timing becomes effective last, taoe, tace, taa, or tbdd.. R/W = VIH, and the address is valid prior to or coincidental with CE traition OW. tpd %

9 High-peed 2K x 16 Dual-Port RAM AC Electrical Characteristics Over the Operating Temperature and upply Voltage () 7133X 7143X Com'l Only 7133X 7143X Com'l & Ind 7133X3 7143X3 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCE twc Write Cycle Time (3) 3 tew Chip Enable to End-of-Write taw Address Valid to End-of-Write ta Address et-up Time twp Write Pulse Width twr Write Recovery Time tdw Data Valid to End-of-Write thz Output High-Z Time (1,2) 12 tdh Data Hold Time (4) twz Write Enable to Output in High-Z (1,2) 12 tow Output Active from End-of-Write (1,2,4) 2746 tbl 11a 7133X4 7143X4 Com'l Only 7133X 7143X Com'l, Ind & Military 7133X7/9 7143X7/9 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCE twc Write Cycle Time (3) 4 7/9 tew Chip Enable to End-of-Write 3 4 / taw Address Valid to End-of-Write 3 4 / ta Address et-up Time / twp Write Pulse Width 3 4 / twr Write Recovery Time / tdw Data Valid to End-of-Write 3/3 thz Output High-Z Time (1,2) / tdh Data Hold Time (4) / twz Write Enable to Output in High-Z (1,2) / tow Output Active from End-of-Write (1,2,4) / 2746 tbl 11b 1. Traition is measured mv from ow or High-impedance voltage from the Output Test oad (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. For MATER/AVE combination, twc = tbaa + twr + twp, since R/W = VI must occur after tbaa. 4. The specification for tdh must be met by the device supplying write data to the RAM under all operation conditio. Although tdh and tow values will vary over voltage and temperature, the actual tdh will always be smaller than the actual tow.. 'X' in part number indicates power rating (A or A)

10 High-peed 2K x 16 Dual-Port RAM AC Electrical Characteristics Over the Operating Temperature and upply Voltage (6) 7133X 7143X Com'l Only 7133X 7143X Com'l & Ind 7133X3 7143X3 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. Unit BUY TIMING (For MATER 71V33) tbaa BUY Access Time from Address 3 tbda BUY Disable Time from Address 3 tbac BUY Access Time from Chip Enable tbdc BUY Disable Time from Chip Enable 17 twdd Write Pulse to Data Delay (1) 4 6 tddd Write Data Valid to Read Data Delay (1) tbdd BUY Disable to Valid Data (2) 3 3 tap Arbitration Priority et-up Time (3) twh Write Hold After BUY () BUY INPUT TIMING (For AVE 71V43) twb BUY Input to Write (4) twh Write Hold After BUY () twdd Write Pulse to Data Delay (1) 4 6 tddd Write Data Valid to Read Data Delay (1) tbl 12a 7133X4 7143X4 Com'l Only 7133X 7143X Com'l, Ind & Military 1. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read and Busy". 2. tbdd is calculated parameter and is greater of, twdd - twp (actual) or tddd - tdw (actual). 3. To eure that the earlier of the two ports wi. 4. To eure that the write cycle is inhibited on port "B" during contention on port "A".. To eure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (A or A). 7133X7/9 7143X7/9 Com'l & Military ymbol Parameter Min. Max. Min. Max. Min. Max. Unit BUY TIMING (For MATER 71V33) tbaa BUY Access Time from Address 4 4 4/4 tbda BUY Disable Time from Address 4 4 4/4 tbac BUY Access Time from Chip Enable 3 3 3/3 tbdc BUY Disable Time from Chip Enable 3 3/3 twdd Write Pulse to Data Delay (1) 8 8 9/9 tddd Write Data Valid to Read Data Delay (1) 7/7 tbdd BUY Disable to Valid Data (2) 4 4 4/4 tap Arbitration Priority et-up Time (3) / twh Write Hold After BUY () 3 3 3/3 BUY INPUT TIMING (For AVE 71V43) twb BUY Input to Write (4) / twh Write Hold After BUY () 3 3 3/3 twdd Write Pulse to Data Delay (1) 8 8 9/9 tddd Write Data Valid to Read Data Delay (1) 7/ tbl 12b

11 High-peed 2K x 16 Dual-Port RAM Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing) (1,,8) ADDRE twc OE (6) ta taw (3) twr CE (2) twp (7) thz R/W (9) tz twz (7) tow (7) thz DATAOUT (4) (4) tdw tdh DATAIN 2746 drw 9 Write Cycle No. 2 (CE Controlled Timing) (1,) twc ADDRE taw CE (6) (2) ta tew twr R/W (9) tdw tdh DATAIN 2746 drw 1 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of a CE = VI and a R/W = VI. 3. twr is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pi are in the output state, and input signals must not be applied.. If the CE OW traition occurs simultaneously with or after the R/W OW traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. Timing depends on which enable signal is de-asserted first, CE or OE. 8. If OE is OW during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 9. R/W for either upper or lower byte

12 High-peed 2K x 16 Dual-Port RAM Timing Waveform of Write with Port-to-Port Read and BUY (1,2,3) twc ADDR"A" MATCH twp R/W"A" tdw tdh DATAIN"A" ADDR"B" (1) tap MATCH VAID tbda tbdd BUY"B" twdd DATAOUT "B" 1. To eure that the earlier of the two ports wi, tap is ignored for lave (IDT7143). 2. CE = CER = VI 3. OE = VI for the reading port. 4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". tddd (4) VAID 2746 drw 11 Timing Waveform of Write with BUY (3) twp R/W"A" twb BUY"B" twh (1) R/W"B" (2) 2746 drw twh must be met for both BUY input (IDT7143, slave) and output (IDT7133, master). 2. BUY is asserted on port "B" blocking R/W"B", until BUY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".,

13 High-peed 2K x 16 Dual-Port RAM Timing Waveform of BUY Arbitration Controlled by CE Timing (1) ADDR"A" AND "B" ADDREE MATCH CE"A" tap (2) CE"B" tbac tbdc BUY"B" 2746 drw 13 Timing Waveform of BUY Arbitration Controlled by Addresses (1) trc OR twc ADDR "A" ADDR "B" ADDREE MATCH (2) tap tbaa ADDREE DO NOT MATCH tbda BUY "B" 2746 drw All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tap is not satisfied, the BUY will be asserted on one side or the other, but there is no guarantee on which side BUY will be asserted (IDT7133 only)

14 High-peed 2K x 16 Dual-Port RAM Functional Description The IDT7133/43 provides two ports with separate control, address and I/O pi that permit independent access for reads or writes to any location in memory. The IDT7133/43 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Non-contention READ/WRITE conditio are illustrated in Truth Table 1. Busy ogic Busy ogic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is busy. The BUY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUY logic is not required or desirable for all applicatio. In some cases it may be useful to logically OR the BUY outputs together and use any BUY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUY logic is not desirable, the BUY logic can be disabled by using the IDT7143 (AVE). In the IDT7143, the BUY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUY pi HIGH. If desired, unintended write operatio can be prevented to a port by tying the BUY pin for that port OW. The BUY outputs on the IDT 7133 RAM are open drain and require pullup resistors. Width Expaion with Busy ogic Master/lave Arrays When expanding an IDT7133/43 RAM array in width while using BUY logic, one master part is used to decide which side of the RAM array will receive a BUY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUY signal as a write inhibit signal. Thus on the IDT7133 RAM the BUY pin is an output and on the IDT7143 RAM, the BUY pin is an input (see Figure 3). R/W BUY EFT 27Ω R/W BUY VCC R/W BUY IDT7133 MATER IDT7143 AVE R/W BUY VCC R/W BUY 27Ω RIGHT R/W BUY 2746 drw Figure 4. Busy and chip enable routing for both width and depth expaion with the IDT7133 (MATER) and the IDT7143 (AVE). Expanding the data bus width to 32 bits or more in a Dual-Port RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUY while another activates its BUYR signal. Both sides are now BUY and the CPUs will await indefinitely for their port to become free. To avoid the Busy ock-out problem, IDT has developed a MATER/AVE approach where only one hardware arbitrator, in the MATER, is used. The AVE has BUY inputs which allow an interface to the MATER with no external components and with a speed advantage over other systems. When expanding Dual-Port RAMs in width, the writing of the AVE RAMs must be delayed until after the BUY input has settled. Otherwise, the AVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUY to eure that a write cycle takes place after the contention is resolved. This timing is inherent in all Dual-Port memory systems where more than one chip is active at the same time. The write pulse to the AVE should be delayed by the maximum arbitration time of the MATER. If, then, a contention occurs, the write to the AVE will be inhibited due to BUY from the MATER

15 High-peed 2K x 16 Dual-Port RAM Truth Table I Non-Contention Read/Write Control (4) EFT OR RIGHT PORT (1) R/WB R/WUB CE OE I/O-7 I/O8- Function X X H X Z Z Port Disabled and in Power Down Mode, IB2, IB4 X X H X Z Z CER = CE = VIH, Power Down Mode, IB1 or IB3 X DATAIN DATAIN Data on ower Byte and Upper Byte Written into Memory (2) H DATAIN DATAOUT Data on ower Byte Written into Memory (2), Data in Memory Output on Upper Byte (3) H DATAOUT DATAIN Data in Memory Output on ower Byte (3), Data on Upper Byte Written into Memory (2) H H DATAIN Z Data on ower Byte Written into Memory (2) H H Z DATAIN Data on Upper Byte Written into Memory (2) H H DATAOUT DATAOUT Data in Memory Output on ower Byte and Upper Byte H H H Z Z High Impedance Outputs 1. A - A1 AR - A1R 2. If BUY = OW, data is not written. 3. If BUY = OW, data may not be valid, see twdd and tddd timing. 4. "H" = HIGH, "" = OW, "X" = Don t Care, "Z" = High-Impedance, "B" = ower Byte, "UB" = Upper Byte 2746 tbl 13 Truth Table II Address BUY Arbitration CE CER Inputs Outputs A-A1 AR-A1R BUY (1) BUYR (1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal MATCH (2) (2) Write Inhibit (3) 2746 tbl Pi BUY and BUYR are both outputs on the IDT7133 (MATER). Both are inputs on the IDT7143 (AVE). On laves the BUY input internally inhibits writes. 2. "" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. If tap is not met, either BUY or BUYR = VI will result BUY and BUYR outputs can not be OW simultaneously. 3. Writes to the left port are internally ignored when BUY outputs are driving OW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUYR outputs are driving OW regardless of actual logic level on the pin. 6.42

16 High-peed 2K x 16 Dual-Port RAM Ordering Information XXXX XX XX X X X X Device Type Power peed Package Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I (1) B G (2) Commercial ( C to +7 C) Industrial (-4 C to +8 C) Military (- C to +1 C) Compliant to MI-PRF-383 QM Green J G F PF 68-pin PCC (J68-1) 68-pin PGA (GU68-1) 68-pin Flatplack (F68-1) 1-pin TQFP (PN1-1) A A Commercial Only Commercial & Industrial Commercial & Military Commercial Only Commercial, Industrial & Military Commercial & Military Commercial & Military ow Power tandard Power peed in nanoseconds K (2K x 16-Bit) MATER Dual-Port RAM 32K (2K x 16-Bit) AVE Dual-Port RAM 2746 drw 16a 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 12/18/98: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Added additional notes to pin configuratio Page 2 Corrected PN1 pinout 2/17/99: Corrected PF ordering code 3/9/99: Cosmetic and typographical correctio 6/9/99: Changed drawing format 1/1/99: Added Industrial Temperature Ranges and removed corresponding notes 11/1/99: Replaced IDT logo 4/1/: Changed ±mv to mv in notes Page 2 Fixed overbar in pinout 6/26/: Page 4 Increased storage temperature parameters Clarified TA parameter Page DC Electrical parameters changed wording from "open" to "disabled" 1/31/6: Page 1 Added green availability to features Page 16 Added green indicator for ordering information 1/21/8: Page 16 Removed "IDT" from orderable part number 1/16/13: Page 1,, 7, 9 &1 Removed Military & 4 & Industrial 3 speed grades from Features and from the headers of the MI & IND of the DC Chars and AC Chars tables to indicate this change Page Removed the Typ & Max values for the MI & IND temp range from the 7133x4 and 7143x4 speed grade offering from the DC Chars tables to indicate this change, see table 7b

17 High-peed 2K x 16 Dual-Port RAM Datasheet Document History (con't.). Page 4 Page 8 & 9 Page 16 Removed annotation for footnote 3 in the Absolute Maximum Ratings table Typo/correction Added T& R indicator to and removed Military & 4 & Industrial 3 speed grades from the ordering information CORPORATE HEADQUARTER for AE: for Tech upport: 624 ilver Creek Valley Road or an Jose, CA 9138 fax: DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc