Effect of Interrupt Logic on Delay Balancing Circuit

Transcription

1 Intrntionl Journl of Computr Applictions ( ) Volum 27 No.4, Auu 2011 Effct of Intrrupt Loc on Dly Blncin Circuit N. Sursh Kumr GIT, GITAM Univrsity Viskhptnm, Indi Dr. D.V. m Koti ddy Coll of Ennrin, Andhr Univrsity, Viskhptnm, Indi ABSTACT Dly lmnts r ddd in wv-piplind circuit to improv th prformnc of th circuit by rducin th dly diffrnc of th lon nd th short pths. But it is vry difficult to obtin xct dly ndd in th circuit. Ind in th prsnt sym Intrrupt loc is usd for dly blncin, thrby providin mor fsibl nd ccurt circuit pth. Gnrl Trms Ditl Syms, Clock Schm. Ky words Piplin, Clock Skw, Intrrupt controllr, dly blncin. 1. INTODUCTION As th smplin frquncis incrss byond 100MHz, th dsin of low jittr, non-ovrlppin clock nrtor bcoms criticl tsk to nsur stisfctory prformnc of hih spd syms [10].A Pip lin tchnoloy is usd in ditl sym to prform multipl tsks simultnously nd torduc th dt losss in dt trnsctions. Th convntionl piplin sym fcin sviour problms du to impropr synchroniztion of clock pulss. This is n univrsl problm in ll th ditl syms moly clld jittr or skw. Th dt trnsfr rts mo importntly dpnd on th ffctiv clock mnmnt. In mo of th ditl syms th proption of informtion minly controlld on th bsis of clock pulss. Th piplinin includs mny of ltchs/flip-flops. Th clock is fd to vry loc t du to which th lods on clock ntwork r unblncd nd clock skw is hihr. This furthr rducs th ffctiv tim vilbl to comput loc in clock priod. Th pnlty du to clock skw bcoms wors s piplin dpths r rducd to chiv hihr clock frquncis. Thus, n fficint clockin mthod is vry criticl to chiv hih prformnc. Hr nw sym is implmntd in th pth of th clock to rmov or rduc th clock skw. In th prsnt work nw wy of clock sym is proposd in th pth of th clock to rmov or rduc th clock skw. Thr r lrdy fw mthods ffctivly workin on clock skw such smsychronous piplin [1] nd wv-piplinin [6] mthods. Th id of wv-piplinin [6] ws orinlly introducd by Cottn [7], who nmd it mximum rt piplinin.cotton obsrvd tht th rt t which loc cn propt throuh th circuit dpnds not on th lon pth dly but on th diffrnc btwn th lon nd th short pth dlys. As rsult, svrl computtion wvs, i.., loc sinls rltd to diffrnt clock cycls, cn propt throuh th loc simultnously. Th sym clockin mu b such tht th output dt is clockd ftr th lt dt hs rrivd t th outputs nd bfor th rli dt rrivs t th outputs from th nxt clock cycl. Criticl spd-limitin fctors in wvpiplinin [6] r th uncontrolld clock-skw, th smplin tim of rrs, nd th wor cs trnsition tim t th loc outputs. Whil th minimiztion of ths fctors hs bn mjor chlln in th dsin of convntionl hih-spd piplind syms s wll, th quliztion of pth dlys coms s nw chlln for th dsin of wv-piplind syms. Diffrnt clock sinl pths cn hv diffrnt dlys for vrity of rsons [8]. Diffrncs in dlys of ny ctiv buffrs within th clock diribution ntwork my cus unsynchroniztion of dt nd clock in wv piplin mthod. 2. EXISTING METHODS A numbr of clockin tchniqus r proposd [11],[12] to improv th tolrnc towrds clock skw nd tovoid ltchin ovrhds. In multi-phs clockin schm[12] diffrnt phss of th clock r diributd to diffrnts of loc. This voids th nd of piplinltchs nd provids hihr skw tolrnc t th coof hihr clock powr nd incrsd wirin complxity.th dlyd clockin schm [11] chivs th smby diributin dlyd pr-chr clock to th locts. Th dlyd clockin schm is sir to implmntnd is sclbl. Skw tolrnc in dlyd clockinschm dpnds on th timin rltion btwn thdlyd clocks nd th lobl clock. In convntionl piplin sym sinl clock puls is pplid to mn th dt trnsmission throuh th Dt pth Clock Puls r Fiur 1 Convntionl Piplin Sym rrs in th piplin s shown in fiur 1. But it will crt clock skw in th piplin which will dcrs th dt spd from on to othr. Th dt pulss r fd into th fir rr whn clock puls is pplid to th fir of th piplin. Th puls will b pssd to th nxt ftr pplyin th clock puls to th nxt. Th clock puls pth is dirctly vn to th rrs whr th dt pulss r psss from on to nothr. This my crt problm of ovrlppin of pulss in th fir bfor it ntrs into th nxt or it will incrs th dly in dt trnsmission. In convntionl piplin syms th clock sinl is drivd s T clkconv Dmx Dr T. s clk r And on of th bi chllns in mny of th clock bsd syms is clock puls width. Smllr clock priods r chivd in wv piplinin [2][6] by rducin th mximum proption dly (Dmx) by splittin th s into numbr of s. 26

2 Intrntionl Journl of Computr Applictions ( ) Volum 27 No.4, Auu Timin Conrints For wv-piplind sym to oprt corrctly, th symclockin mu b such tht th output dt is clockd ftrthlt dt hs rrivd t th outputs nd bforth rlidt from th nxt clock cycl rrivs t th outputs. Itshll fir driv th conditions for clockin of th ltnd th rli dt proptin in th circuit, which is rprsntin th rr conrints. So introducin prmtr N, whichrprsnts th numbr of clock cycls ndd for sinl topropt throuh th loc block bfor bin ltchd by thoutput rr. This prmtr srvs s n intuitiv msurof th dr of wv-piplinin. Th dt should b clockdt tim T L by th risin d of th output rr N clockcycls ftr it hs bn clockd by th input rr. Du topossibl conructiv skw (of rbitrry vlu) btwn thoutput nd th input rrs, this tim cn b xprssd s T N L T (1) clk 2.2 r Conrints ) Clockin of th lt dt: This conrint rquirht th lt possibl sinl rrivs rly nouh to bclockd by th output rr durin Nth clock cycl.thrfor, th lowr bound ont L, which dnots th tim twhich th output wv is cpturd, is vn by T L Dr Dmx T s clk (2) b) Clockin of th rli dt:this condition rquirht th rrivl of th nxt wv i+1 mu not intrfr with thclockin of th currnt wv. Tht is, th rli possiblsinl of wv mu rriv ltr thn th clockin of thwv t th output rr. This condition is similr to thrc-throuh conrint in convntionl piplinin. Notic thtth rli rrivl of wv i+1 is vn by T clk Dr D. min Aftr th clock puls hs bn pplid to th output rr,dditionl hold timt h mu b llowd for th dt to rmindy. In ddition, on mu ccount for n uncontrolldclock-skw clk t th output rr. As rsult, this boundd bov s follows: T T D Dmin ( T ) L clk r clk h (3) Combinin conrints (2) nd (3) vs us th wllknownmximum rt piplinin condition of Cottn T ( D D ) T T (4) clk mx min s h clk Th minimum clock priod is limitd by th diffrnc inpth dlys(d mx - D min ), plus th clockin ovrhd(ts + T h + 2 clk ) rsultin from th insrtion of clockdrrs.so th clock sinl is drivd in th wv piplinin is ( D ) 2 T D T T clk. w mx min h s clk Th wv piplinin is shown in fiur 2. Th mximum prformnc of wv-piplind circuit is limitd by th dly diffrncs of th lon nd shortpths in th circuit, th up(ts) nd hold tim(th) of th or lmnts btwn th piplin s, th clock skw, nd procss vritions. On obvious wy to improv cycl tim io ttck th dly blncinproblm, i.. rduc th dlydiffrnc btwn th lon nd short pths. Bttr blnc prmits fr clocks nd mor simultnously ctivwv in th circuit. r Fiur 2 Wv Piplinin Andfurthr th proption dly is rducd nd th clock synchroniztion is controlld by introducin dly lmnt in th pth of clock sinl of M-synchronous piplinin [1] s shown in fiur 3. This dly will b qul to th dly crtd by th puls pssd from on to othr of th piplin. Th sym is clockd such tht piplin is oprtin on mor thn on dt wv simultnously. At ny vn tim, multipl wvs cn b prsnt in nd th wvs r sprtd bsd on physicl proprtis of intrnl nods in th loc. Th clock sinl is drivd in th Msynchronous piplinin is T ( D D T T 2 ( f ) ( f )) mx clk. m min h s clk Dt pth Clock Puls r r b Dly Fiur 3 Msynchronous piplinin Clock r Mo of th dly blncin tchniqus us dly lmnts ithr s pddin in th dt pth of th circuit or to insrt skw in som clock diribution lins of th circuit. But, it is not sy to dsin n xct dly ndd [9]. Furthrmor, for circuit with lr dly diffrncs, sris of dly lmntsndd to insrt to blnc th pths. It is vn hrdr to chiv th xct dly vlu dsird. In th prsnt mthod Intrrupt loc is usd to control dly which is mor ccurt thn usin lon chins of dly lmnts bcus th clock lins which control ltchs, in contr to dt sinls, hv smllr nd mor sily controllbl skws. 2.3Clock Eds quirmnts Th inputs r dfind ithr t risin or fllin ds of th smplin clock. So th clockin ds dirctly imply th inccurcy would b rltd to timin jittr. So it is hihly ssntil to chiv non ovrlp timin sinls to t ccurt sinls. On th othr hnd in mo of th pplictions with hihr ccurcy th risin d of pr-phs could b plcd slihtly rlir thn tht of po phss to furthr supprss th chr injction rrors. r c r d r 27

3 Intrntionl Journl of Computr Applictions ( ) Volum 27 No.4, Auu ENHANCED METHOD In multipl s piplin sym diffrnt dly lmnts nd to b insrtin in th clock pth. Bcus th fir dly insrtd in th clock pth is qul to th dt proptd from fir to scond. And th scond dly lmnt is such tht th sum of dly1 nd dly2 mu b qul to dly nrtd in dt proptin from 1 to 3. Althouh th dt propts immditly from 2 to 3, th 2 dt will b fd to 3 only whn th 1 dt ntr into 2. Th 2 dt is pushd into 3 whn 1 dt ntrs into 2. In th prsnt work nw mthod is proposd by introducin controllr to supply th clock pulss to thpiplin s ind of usin xtrnl clock circuitry s shown in fiur 4. Th individul in th piplin intrrupts th intrrupt controllr to nbl th nxt clock puls for th piplin[14]. r Dl y r Dl y r Dl y incrss with insrtd dly lmnts. Th dly obtind t ch clock which is pplid t ch of th circuit qul to th proption dly of th wv from on to nxt throuh rr in th prsnt nd fixd frctionl dly lmnt insrtd btwn two s. 3.1 Frctionl Dly Du to th dynmiclly chnn ntur of th dlys, typicllysmoothly chnn from 10 ms to bout 50 ms, w nd to implmntfrctionl dly lins. If w wr to us nonfrctionl dlys, w wouldonly b bl to implmnt p-wis dlys dicttd by th smplin rtfs nd intr K s sn in Eq. (3.1.1). This mns tht ch dly incrmntor dcrmnt would b confind to intr units of T = 1/fs sconds. Dly Non. frct K. 1 f s (3.1.1) Linr intrpoltion of dly is quit rihtforwrd to implmnt ndis shown in Eq. (2) whr τ is th frctionl dly mount, y fd [n τ] ih dlyd output smpl vlu, frc(τ) is th frctionl prt (mntiss),nd int(τ) is th intr prt of th frctionl dly τ. Clock pth y n Dly Elmnt yn-1 Procs sor Intrrupt Loc Fiur 5 Sinl Block Dly Unit y [ ]. [ int( )]. [ int( ) 1] n y n y n fd int( ) int( ) 1 Fiur 4 Block dirm of Enhncd clock sym in pip lin sym Th sym is clockd such tht piplin is oprtin on mor thn on puls simultnously. Th prsntsym t ny vn tim, multipl pulss cn b prsnt in similr to th msychronous piplinin.as on puls ntrs into th fir flip-flop it s th nxt flip-flop in th prsnt. Whil th fir puls ntrin into th nxt FF nxt puls simultnously oprts th fir FF. Th clock sinl in th prsnt mthod is qul to ( D ) 2 T D T T clk. i mx min h s clk whr, T h = holdin tim of th rr T s = tin tim of th rr D mx = mximum proption dly D min = minimum proption dly clk = Clock Uncrtinty So th proption dly will b lss thn th totl clock priodof th piplin s. For blncin th minimum nd mximum dlys of circuit pth, intrrupt locs r prfrrd ovr dly lmnts. Sinc dly lmnts with Min/Mx dlys do not rduc th dly diffrnc of such pth. If th Min/Mx dly rtio of dly lmnt is lss thn 1, th dly diffrnc of such pth lwys 1 frc( ) int( ) (3.1.2) frc() (3.1.3) int( ) 1 int( ) (3.1.4) int( ) 1 Not tht th rsultin frctionl dly in ssnc is ju linr wihtinof two djcnt dlyd smpls. For xmpl, if th frctionl dly wwnt is 6.5, th wihts int (τ) nd int (τ) 1 will b both qul to 0.5, whilth intr dlys qul to 6 nd 7 rspctivly: y [ n ] y [ n 6] 0.5. y [ n 7] fd dynmic frctionl dly lin. y [ ]. [ ]. [ 1] (5) n y n y n fd frc( ) (6) 0 frc() (7) Clock Schm A ky lmnt of mo ditl syms is th clock. Its priod dtrmins th rt t which dt r procssd, nd so should b md s smll s possibl, consint with rlibl oprtion. 28

4 Intrntionl Journl of Computr Applictions ( ) Volum 27 No.4, Auu 2011 Bsd on wor cs nlysis, clockin schms for hih prformnc syms r nlysd. Ths r 1- nd 2-phs syms usin simpl clockd ltchs. Whn trditionl rrs r usd, sinl-phs clockin is nithr sf nor f [13] nd multi-phs clock is rquird. This is du to lowr bound conrint on th minimum short pth dly of th combintionl circuits tht could rsult in dt rcthrouh problm. In th prsnt work microcontrollr usd to nrt clock puls from th lobl clock. Th clock priod cn b vrid dpnds on th sinl rrivd from Intrrupt loc. And th clock puls coms T µcf ftr th risin d on th lobl clock. This clock puls is thn diributd to diffrnt s of piplin. Aftr rrivin of fir vlid dt t intrrupt controllr th intrrupt controllr intrrupts microcontrollr. In rspons to this intrrupt th microcontrollr snd clock sinl to th nxt rr. Similrly ftr rcivin vlid sinl from scond rr th intrrupt controllr n intrrupts th microcontrollr. Th microcontrollr in th sm wy ctivts th nxt in diffrnt pth. Th min ol in th mo of th ditl syms to dsin clockin schm is to mk th priod s smll s possibl,this is to mximizin th spd of th sym. It is obvious tht minimizin D mx is bsic to minimizin thclock priod. But, s pointd out bov, it-is lso importnt tokp th smll pth dly D min s lr s possibl. But it is not tht much sy to mk th loc pth dlys uniform in vlu.for this rson, sym dsin is proposd hr to control th clock skw t multiphs throuh prormmbl controllr. And it is vry difficult to mn th clock sym btwn th piplin s nd dly lmnts by stisfyin ll th 2-phs conrints [13]. 4. HADWAE Th hrdwr circuit dscription is shown in fiur 6.Initilly th dt pulss r fd to th fir of th piplin. In th fir th fir bit ntrs into fir position.whn th dt puls fds th nxt puls th fir bit pushd to th nxt position nd th fir position will brplcd with th nw bit. Th bit positions will chn in quu. Whn th l bit ovrflowd from th fir rrnd it will ntr into th nxt. At th sm tim th ovrflow bit from th fir rr snd to intrrupt rqupin (IQ) of th Prormmbl Intrrupt Controllr (PIC). Th PIC will nrt n intrrupt rqu tomicrocontrollr (8051) on on of th Port pin. Whn th fir bit of Intrrupt qu rr is ftr IQ0 rcivs rqu, sinl willb nrtd throuh Portpin s clock puls to th scond. Immditly ftr clock sinl rrivd t scond,th ovrflowd bit from fir ntrs into scond throuh dly lmnt. An individul port pin is usd for clock sinl for fir. Thsclock sinls r controlld nd chn it ts throuh microcontrollr prormmin. Th PIC is intrfcd ndcontrolld throuh prormmin in microcontrollr. Th initiliztion commnd word of PIC is to Ed Trir Mod in ordr to chiv fr rspons from piplin s. As th ovrflow occurs from scond th ovrflow bit willtry to ntr into nxt. At th sm tim thr my b chnc of ovrflow from fir to scond. Soin th cs individul clock pulss nd to b in Port 1. So p1.1 nd p1.2 will nrt clock sinls for scondnd third. Hr th width of th puls nrtd from th port pins(t µpcw.i ) mu b rtr thn th proption dly of dt from on rr to othr rr. Th proption dly (D prop_dly = D min D mx )btwn ny two rrs dpnds on holdin nd tin tim of th intrnl wv throuh n individul rr nd smll frctionl dly lmnt (Y fd ). i.,., D D T T min mx h s 2 clk fd T pcw. i D prop _ dly Th mount of Y fd indirctly dpnds on th ddition of IQ rspons ( IQ ) nd INT rspons (T INT ) t microcontrollr IQ T INT. Bcus this sum crts n ddition dly in th clock pth nrtd by ports. This dditionl ddd dly blncd nd cnclld by ttchin smll frctionl dly btwn two s. So hr th dly producd by IQ T is blncd by Y INT fd. Fiur 6 Circuit Dirm In th sm wy th pulss will b supplid whn ovrflow occur t hihr s. Th sym is clockd such tht piplin is oprtin on mor thn on puls simultnously. 5. EXPEIMENTAL ESULTS Th dt trnsmission throuh diffrnt s is controlld by smll intrrupt loc in fixd priority mod. Th rspctiv intrrupt rqus will control th clock pulss of rspctiv s of piplin. Th rqus for th nxt s ord in PIC r procssd by microcontrollr nd hnc individul clock sinls r mnd. Th pip lin oprtions r simultd nd undrnd by CAD tools. Th hold tim of th rrs is rducd so it rsons hih prformnc. Th tim priod in obtinin Q ftr clock is scrtind is minimizd. Fiur 7 Anlysis of Pip Lin usin Timin Dirm Th widths of individul clock pulss to diffrnt s r indpndnt nd hnc cn b mintind t short width. Thrfor hihr prformnc is chivd in trms of dt trnsfr rts. Th rltiv rror t Q output is minimizd to lmo zro. Piplin conructd with fwr flip flops nd hnc fw rrs r involvd in th dsin. Hihr dt rts r obsrvd in th currnt piplin sym. Smllr clock priods r chivd usin intrrupt loc. Hihr prformnc y 29

5 Intrntionl Journl of Computr Applictions ( ) Volum 27 No.4, Auu 2011 cn b chivd usin simpl control of clock diribution. Ftchin wvs nd procssin th output r simultnously prformd t diffrnt spds by vryin th input clock frquncy. 6. CONCLUSION Th clock diribution bcoms simplr by controllin clock sinls by intrnl ports of controllr. Simplsoftwr loc is usd to control th ports of controllr to nrt th clock sinls. Hihr prformnc cn bchivd usin intrrupt bsd dly blncd mod. Th proposd piplin schm voids wv collision nd supports hih ccurcy in dt trnsmission. In th proposd sym th clock spd minly ffctd by intrrupt controllr. It voids prdictin th dly lmnts in th clock pth. On intrruptcontrollr mu b ddictin for nrtin intrrupts. Controllin of Initilizin Commnd Words nd OprtionlCommnd Words incrss th complxity in th cod. 7. EFEENCES 1.[1] Surynryn B. Ttpudi, udnt Mmbr, IEEE nd José G. Dldo-Fris, Snior Mmbr, IEEE,A Msychronous hih prformncditl syms, VOL. 53, NO. 5, MAY [2] C.Thoms y, Timin conrints for wv piplindsyms IEEE trnsctions on Computr idd dsin of intrtd circuits, vol13,no.8, uu [3] Jbulni Nythi, A hih prformnc hybrid wv piplind linr fdbck shift rr with skw tolrnt clocks, IEEE, , [4] Mohmmd Mymndi, A ditl prormmbl dly lmnt: Dsin nd nlysis, IEEE trnsction VLSI syms, Vol.11, no.5,octobr [5] Dvid E. Durt, A Clock Powr Modl to Evlut Impct of Architcturl nd Tchnoloy Optimiztions, IEEE trnsctions on vry lr scl intrtion (VLSI) syms, vol. 10, no. 6, Dcmbr [6] Wyn P. Burlson, Wv-Piplinin: A Tutoril nd srch Survy, IEEE trnsctions on vry lr scl intrtion (VLSI) syms, vol. 6, no. 3, Sptmbr [7] L. Cottn, Mximum rt piplind syms, in Proc. AFIPS Sprin Joint Comput. Conf., [8] EBY G. Fridmn, Clock Diribution Ntworks in Synchronous Ditl Intrtd Circuits, Invitd ppr,procdins of th IEEE, VOL. 89, NO. 5, My [9] S. H. Unr, C. J. Tn, Clockin schms for hihspdditl syms, IEEE Trns. on Computrs, vol. C- 35,No. 10, Oct. 1986, pp [10] Si.Wn Sin, Novl Timin skw insnsitiv, Multiphs clock nrtion schm for prlll DAC nd N-pth filtr, IUPEEEC 2006, pp [11] Silbrmn t l., A 1.0-GHz Sinl-Issu 64-Bit PowrPCIntr procssor, IEEE Journl of Solid t Circuits,vol. 33, Nov. 1998, pp [12] D. Hrris t l., Skw-Tolrnt Domino circuits ISSCCDi of Tchnicl Pprs, Fb 1997, pp [13] phn h. unr, Clockin Schms for Hih-Spd Ditl Syms, IEEE Trnsctions on computrs, vol. c- 35, no. 10, Octobr 1986, pp [14] Nndim.S, A Nw Mthod to Enhnc Prformnc of Ditl Frquncy Msurmnt nd Minimiz th Clock Skw, ccptd to publish in th futur issu of IEEE Snsor J. 6.[15] T.N. Prbkr, Dsin nd implmnttion of n Asynchronous Controllr for FPGA Bsd Asynchronous Syms, 2010Intrntionl Journl of Computr Applictions ( ) Volum 1 No. 21, pp