Clocking Solutions. Wired Communications / Networking Wireless Communications Industrial Automotive Consumer Computing. ti.

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1 ing Solutions Wired Communications / Networking Wireless Communications Industrial Automotive Consumer Computing ti.com/clocks 2014

2 Accelerate Time-to-Market with Easy-to-Use ing Solutions Texas Instruments is the world s #1 supplier of analog semiconductor ICs, and offers a complete clock and timing IC portfolio from clock buffers and generators to jitter attenuators and RF PLLs/synthesizers targeting a broad spectrum of endequipment. These easy-to-use, high performance clocking products are supported by a number of innovative, robust online tools that ease design and reduce time-to-market. ing Solutions from TI Offer: Flexible frequency planning Universal input and output formats Best-in-class jitter and phase noise performance Low power consumption In-system programming Sophisticated clock design tools that automate selection, configuration and simulation of TI clocking devices Addressing Broad Applications: Wired communications / networking Wireless communications Industrial Automotive Consumer Computing Design Resources and References WEBENCH Architect The industry s only timing tool that recommends a system clock tree solution with device selection from an exhaustive database, with all the necessary features to enable system designers to quickly achieve a complete, optimized clock tree solution. PLL loop filter design capability Simulate phase noise of the output clocks Cascade noise from a device upstream in the clock tree solution to a downstream device Generate a configuration file for each of the devices in the recommended solution which can be used to program the individual device EVMs ti.com/clockarchitect E2E s & Timing Forum ti.com/e2eclocks TM 2 ing Solutions Texas Instruments

3 ing Applications Wired Communications Line Card Example Switch Example GPS Master OCXO Generator 1588 Protocol Synch (DPLL) Generator Buffer OSC GbE 10GbE 8Gb FC FPGA GbE 25GbE ASIC FPGA Wireless Communications Wireless RRU Example ADC ADC Antenna Antenna RF RF Synth/PLL DAC DAC RF RF Synth/PLL JITTER CLEANER DIGITAL Wireless BBU Example Backplane Backplane JITTER CLEANER CLOCK CLOCK GENERATOR CLOCK BUFFER CLOCK BUFFER CLOCK BUFFER CLOCK BUFFER DSP ASIC CPRI CPRI GbE GbE FPGA MCU MCU Industrial Test and Measurement Example Automotive Automotive Radar Example ADC10D040Q ADC DSP / Input Frequency 24GHz to 77GHz LNA Amp ADC DSP Buffer / N SoC / FPGA X Generator RF PLL x2 DIGITAL PLL PLL PLL Dist Texas Instruments ing Solutions 3

4 ing for Communications Wired Communications/Networking s With increasing data rates in networking and wired communication applications, clock jitter has become a major bottleneck for maintaining high signal integrity. TI s ultra-low jitter clock jitter cleaners and clock generators enable designers to improve system performance while reducing the BOM by consolidating expensive high frequency oscillators. Equipped with a flexible architecture and advanced features such as hold-over, TI s clocking ICs increase system performance, flexibility and robustness. Wireless Communications s jitter and local oscillator (LO) phase noise are key elements in the radio signal path and can directly impact the quality of the RF signal being received and transmitted. Likewise, in the baseband boards, clocks can impact the signal integrity of the high speed link to and from radio. With industry-leading performance, TI s clock jitter cleaners, clock generators, buffers and RF frequency synthesizers enable designers to maximize the quality and robustness of wireless links. Featured Generators CDCM6208 LMK03806 CDCE62005 CDCM6100x CDCM9102 CDCE(L)913 CDCE(L)949 CDCE706 Any frequency, 2 inputs, 8 outputs with integer and fractional dividers 1 input, 14 outputs, ultra-low jitter with integer dividers 3 inputs, 5 outputs with integrated dual VCOs 1 input, 1-4 outputs, crystal oscillator replacement Low jitter, 2-channel, 100 MHz PCIe Gen-1/-2/-3 1 PLL, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 4 PLLs, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 3 PLLs, spread spectrum clocking, ultra flexible output switching matrix Featured RF PLLs and Synthesizers 2:8 1:14 3:5 1:1 (CDCM61001) 1:2 (CDCM61002) 1:4 (CDCM61004) 1:2 1:3* 1:9* 1:6 ended, Crystal or external clock ended, ended ended ended, option for on-chip VCXO ended, option for on-chip VCXO ended, CML, LVDS, HCSL, LVDS, LMX2522 Ultra-low power, dual RF synthesizer, integrated GPS/RF VCOs, IF PLL 1:1 Single ended Sinewave Frequency ps 0.15 ps 0.35 ps 0.5 ps 0.5 ps 65 ps cycle-tocycle Normalized PLL Phase Noise (dbc/hz) SPI, I2C, pin 224 µwire (SPI) 227 SPI, EEPROM 218 Pin 218 Pin 218 SMBus, EEPROM Frequency 1619 to & 440 Normalized PLL Phase Noise (dbc/hz) 0.4 ps SPI LMX2531 LMX2541 LMX2581 LMX248x LMX243x Low power, low spur, fractional-n synthesizer with integrated VCO Low noise, excellent spurs, fractional-n, integrated VCO, optional external VCO Ultra-low noise, wideband, fractional-n synthesizer, integrated wideband VCOs Ultra-low power, wideband, dual fractional-n PLLs, available auto grade versions Ultra-low power, low noise, dual integer PLLs 1:1 Single ended Sinewave 553 to ps SPI 212 1:1 Sinewave 32 to 4000 (integrated VCO), 6000 (external VCO) 0.12 ps SPI 225 1:2 Differential Sinewave 50 to ps SPI 229 1:2 Single ended Sinewave 50 to ps SPI 210 1:2 Single ended Sinewave 250 to ps SPI 219 * 2 PLL / 5 output and 3 PLL / 7 output also available ** As measured form 12 khz to 20 MHz 4 ing Solutions Texas Instruments

5 ing for Communications XXXXXXXXXX Featured Distributors / Fanout Buffers LMK0033x LMK00725 LMK0030x Industry s lowest jitter PCIe 3.0 compliant 1-to-4 HSCL fanout buffers Low jitter, low skew, 1-to-5, -to-3.3v LVPECL fanout buffer Ultra-low jitter, configurable buffer/level translators, crystal oscillator 1:4 1:5 3:4 (LMK00304) 3:6 (LMK00306) 3:8 (LMK00308) 3:10 (LMK00301) CML, SSTL, HSTL, HCSL or single ended HCSL, SSTL, LVHSTL or single ended ended, HSCL 400 LVPECL 650 HCSL + 1 CDCLVPxxxx LVPECL buffers from 1:2 to 2:16 Differential LVPECL 2000 / 3500 CDCLVDxxxx LVDS buffers from 2:4 to 2:16 Differential LVDS 800 / 1100 LMK0010x Ultra-low jitter, configurable buffer/level translators, crystal oscillator 3:5 (LMK00105) 3:10 (LMK00101) ended, Frequency CDCLVCxxxx buffers from 1:2 to 1: CDCM1802 Programmable divider 1:2 CDCM1804 Programmable divider 1:4 LMK01801 Dual clock divider buffers, digital and analog delay programming Featured Jitter Cleaners from 2:14 to 2:20 CDCM7005 LMK0480x LMK0482x LMK04906 LMK04816 Low phase noise with frequency holdover, available in BGA package 2 selectable inputs, 14 outputs, frequency holdover mode, programming delay Dual PLLs, lowest phase noise, JESD204B compliant, frequency holdover mode, programming delay 3 selectable inputs, 7 outputs, frequency holdover mode, programming delay 3 selectable inputs, 13 outputs, frequency holdover mode, programming delay 2:5 2:12+2 3:14+1 3:6+1 3:12+1 CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal LVDS, LVDS, HSDS, LCPECL LVDS, LVDS, 800 LVPECL LVPECL fs typ at 100 MHz (PCIe 3.0 filter) 43 fs typ at MHz (12 k to 20 MHz) 64 fs, RMS 68 fs, RMS 300 fs, RMS 30 fs, RMS 100 fs, RMS 150 fs, RMS 150 fs, RMS 50 fs, RMS Normalized PLL Phase Noise (dbc/hz) 156 dbc/hz at 100 MHz >10 MHz offset 158 dbc/hz at MHz >1 MHz offset Pin Pin Pin Pin Pin, µwire (SPI) Frequency fs, RMS Normalized PLL Phase Noise (dbc/hz) SPI SPI SPI SPI SPI 227 Texas Instruments ing Solutions 5

6 ing for Industrial Low jitter and low phase noise clocking solutions from TI are ideal for industrial applications, including test and measurement, military, medical, smart grid, and industrial computing. Additional requirements may be imposed depending on the nature of the equipment, such as: Multi-channel medical instruments process a lot of data received over multiple channels of ADCs, so the clocking solution must support JESD204B. In some instances, the input reference clock has to be cleaned using a jitter cleaner before it is distributed to the rest of the system using clock buffers. Likewise, low skew simplifies layout and preserves phase relationship across multiple clock domains. Test and measurement and radar products rely on the widest tuning spectrum TI s ultra-low jitter clock generators and zero-delay clock buffers are ideal replacement solutions for industrial designs that rely on several crystals, multiple clock trees at different frequencies and that require clock distribution to different sub-systems on the same hardware. TI s clock jitter cleaners produce the cleanest clocks, deliver the lowest phase noise and in a wide range of output frequencies. Featured Generators CDCM6208 LMK03806 CDCE62005 CDCM6100x CDCM9102 CDCE(L)913 CDCE(L)949 CDCE706 Any frequency, 2 inputs, 8 outputs with integer and fractional dividers 1 input, 14 outputs, ultra-low jitter with integer dividers 3 inputs, 5 outputs with integrated dual VCOs 1 input, 1-4 outputs, crystal oscillator replacement Low jitter, 2-channel, 100 MHz PCIe Gen-1/-2/-3 1 PLL, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 4 PLLs, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 3 PLLs, spread spectrum clocking, ultra flexible output switching matrix Featured Jitter Cleaners 2:8 1:14 Crystal or external clock 3:5 1:1 (CDCM61001) 1:2 (CDCM61002) 1:4 (CDCM61004) ended 1:2 ended 1:3* 1:9* 1:6 CML, LVDS, HCSL, LVDS, LMK0480x LMK0482x LMK04906 LMK selectable inputs, x outputs, frequency holdover mode, programming delay Dual PLLs, lowest phase noise, JESD204B compliant, frequency holdover mode, programming delay 3 selectable inputs, 7 outputs, frequency holdover mode, programming delay 3 selectable inputs, 13 outputs, frequency holdover mode, programming delay * 2 PLL / 5 output and 3 PLL / 7 output also available ** As measured from 12 khz to 20 MHz 2:12+2 3:14+1 3:6+1 3:12+1 CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal CLKin (PLL1): single ended, ; OSCin (PLL2): can use crystal Frequency HSDS, LCPECL ps 0.15 ps 0.35 ps SPI, I2C, pin µwire (SPI) SPI, EEPROM ps Pin ps Pin 65 ps cycleto-cycle SMBus, EEPROM Frequency SPI SPI SPI SPI 6 ing Solutions Texas Instruments

7 ing for Industrial Featured Distributors / Fanout Buffers LMK00725 LMK0030x Low jitter, low skew, 1-to-5, -to-3.3v LVPECL fanout buffer Ultra-low jitter, configurable buffer/level translators, crystal oscillator 1:5 3:4 (LMK00304) 3:6 (LMK00306) 3:8 (LMK00308) 3:10 (LMK00301) LVDS, HCSL, SSTL, LVHSTL or single ended Crystal, single ended, LVPECL 650 HCSL + 1 Frequency 43 fs typ at MHz (12 k to 20 MHz) Normalized PLL Phase Noise (dbc/hz) 158 dbc/hz at MHz >1 MHz offset fs, RMS Pin CDCLVPxxxx LVPECL buffers from 1:2 to 2:16 Differential LVPECL 2000 / fs, RMS CDCLVDxxxx LVDS buffers from 2:4 to 2:16 Differential LVDS 800 / fs, RMS LMK0010x Ultra-low jitter, configurable LVC- MOS buffer/level translators, crystal oscillator 3:5 (LMK00105) 3:10 (LMK00101) Crystal, single ended, fs, RMS Pin CDCLVCxxxx buffers from 1:2 to 1: fs, RMS CDCM1802 Programmable divider 1:2 Differential CDCM1804 Programmable divider 1:4 Differential LMK01801 Dual clock divider buffers, digital and analog delay programming from 2:14 to 2:20 Differential 800 LVPECL LVPECL 200 CDCVF V zero delay buffer 1:4 Single ended 200 CDCVF2510A 3.3V zero delay buffer 1:10 Single ended 175 CDCVF85x 2.5V zero delay buffers 1:4 (CDCVF855) 1:10 (CDCVF857) Differential Differential 220 CDCU877x 1.8V zero delay buffers 1:10 Differential Differential 340 CDCUA V zero delay buffer 1:10 Differential Differential 410 Featured RF PLLs and Synthesizers LMX2522 LMX2531 Ultra-low power, dual RF synthesizer, integrated GPS/RF VCOs, IF PLL Low power, low spur, fractional-n synthesizer with integrated VCO 1:1 Single ended Sinewave 150 fs, RMS Pin 150 fs, RMS Pin fs, RMS Pin, µwire (SPI) 150 ps peak-topeak cycle-to-cycle 125 ps peak-topeak cycle-to-cycle 30 ps peak-peak 30 ps peak-to-peak 30 ps peak-to-peak Frequency 1619 to & 440 Normalized PLL Phase Noise (dbc/hz) 0.4 ps SPI 210 1:1 Single ended Sinewave 553 to ps SPI 212 LMX2541 Low noise, excellent spurs, fractional-n, integrated VCO, optional external VCO 1:1 Sinewave 32 to 4000 (integrated VCO), 6000 (external VCO) 0.12 ps SPI 226 LMX2581 LMX248x LMX243x Ultra-low noise, wideband, fractional- N synthesizer, integrated wideband VCOs Ultra-low power, wideband, dual fractional-n PLLs, available auto grade versions Ultra-low power, low noise, dual integer PLLs 1:2 Differential Sinewave 50 to ps SPI 229 1:2 Single ended Sinewave 50 to ps SPI 210 1:2 Single ended Sinewave 250 to ps SPI 219 Texas Instruments ing Solutions 7

8 ing for Automotive CDCE(L)913-Q1 CDCE949-Q1 CDCE(L)937-Q1 ing for Consumer Featured Generators CDCM9102 CDCE(L)913 CDCE(L)949 CDCE706 ing for Computing Frequency (MHz) Jitter CDCVF V zero delay buffer 1:4 Single ended ps peak-to-peak cycle-to-cycle CDCVF2510A 3.3V zero delay buffer 1:10 Single ended ps peak-to-peak cycle-to-cycle CDCVF85x Low jitter, 2 channel, 100 MHz PCIe Gen-1/-2/-3 1 PLL, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 4 PLLs, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 3 PLLs, spread spectrum clocking, ultra flexible output switching matrix 2.5V zero delay buffer 1:4 (CDCVF855) 1:10 (CDCVF857) 1:2 ended 1:3* 1:9* 1: CDCS50x Spread spectrum clock generators 1:1 ended 108 Featured Distributors / Fanout Buffers CDCVF V zero delay buffer 1:4 Single ended 200 CDCVF2510A 3.3V zero delay buffer 1:10 Single ended 175 CDCVF85x 1 PLL, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 4 PLLs, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs 3 PLLs, integrated VCXO, spread spectrum clocking, 1.8/2.5/3.3V outputs CDCS503-Q1 Spread spectrum clock generator 1:1 CDCVF2505-Q1 3.3V zero delay buffer with input clock detector, 3.3V output, integrated series resistors 2.5V zero delay buffers 1:4 (CDCVF855) 1:10 (CDCVF857) Differential Differential 220 CDCVF85x 1.8V zero delay buffers 1:10 Differential Differential 340 CDCUA V zero delay buffer 1:10 Differential Differential 410 * 2 PLLs / 5 output and 3 PLL / 7 output also available ** As measured from 12 khz to 20 MHz 1:3* 1:9* : 7 ended 230 ended 108 1: 4 Single ended 200 Frequency 110 ps cycleto-cycle 150 ps cycleto-cycle Frequency ps Pin 60 ps peak-topeak 60 ps peak-topeak 65 ps cycle-tocycle 110 ps cycle-tocycle 150 ps peak-topeak cycle-tocycle 125 ps peak-topeak cycle-tocycle 30 ps peak-topeak 30 ps peak-topeak 30 ps peak-topeak LMX2485Q-Q1 Ultra-low power, wideband, dual fractional-n PLLs 1:2 Single ended Sinewave ps SPI LMX2492Q-Q1 Low noise, fractional-n PLL with ramp generation 1:1 Sinewave ps SPI * 2 PLL/5 output and 3 PLL/7output also available ** as measured from 12 khz to 20 MHz Preview products are listed in bold teal. SMBus, EEPROM Differential Differential ps peak-to-peak CDCU877x 1.8V zero delay buffer 1:10 Differential Differential ps peak-to-peak CDCUA V zero delay buffer 1:10 Differential Differential ps peak-to-peak Pin Pin Get more information on TI s entire family of clocking products at ti.com/clocks The platform bar and WEBENCH are trademarks of Texas Instruments. All other trademarks are the property of their respective owners Texas Instruments Incorporated SLYT565