PECL and LVDS Low Phase Noise VCXO (for MHz Fund Xtal) XIN XOUT N/C N/C CTRL VCON (0,0) OESEL (Pad #25) 1 (default)

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1 Reserved BUF BUF 62 mil OESEL^ Reserved Reserved PL FEATURES 65MHz to 130MHz Fundamental Mode Crystals. Output range (no PLL): 65MHz 130MHz (3.3V). 65MHz 105MHz (2.5V). Low Injection Power for crystal 50uW. Complementary outputs: PECL or LVDS. Selectable OE Logic Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Thickness 10 mil. DESCRIPTION The PL is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs and OE logic (enable high or enable low). Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. BLOCK DIAGRAM VCON XIN X Oscillator Amplifier w/ integrated varicaps PL OE Q Q DIE CONFIGURATION Y XIN X OE CTRL VCON X (0,0) DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 62 x 65 m il 80 m icron x 80 micron 10 m il PUT SELECTION AND ENABLE OESEL (Pad #25) (default) 25 SEL (Pad #9) Die ID: A B C502A LVDS 65 mil 1 PECL (default) OE_CTRL (Pad #30) 0 Tri-state 6 Selected Output State 1 Output enabled (default) 0 Output enabled (default) 1 Tri-state 7 8 (1550,1475) BUF LVDSB PECLB BUF BUF PECL LVDS SEL^ Pad # 9, # 25: Bond to to set to 0. Internal pull up. Pad # 30: Logical states defined by PECL levels if OESEL is 1 Logical states defined by CMOS levels if OESEL is 0 Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 1

2 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage 4.6 V Input Voltage, dc VI V Output Voltage, dc VO V Storage Temperature TS C Ambient Operating Temperature* TA C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2 kv Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade on ly. 2. Crystal Specifications Built-in Capacitance 3. Voltage Control Crystal Oscillator (3.3V) CX+ 2 65MHz to 130MHz CX- 2 (at ) Inter-electrode capacitance C0 2.6 C0/C1 ratio (gamma) Fund., 3.3V Supplies Oscillation Frequency OF MHz Fund., 2.5V Supplies VCXO Stabilization Time * T VC XOS TB From power valid 10 ms VCXO Tuning Range * XTAL C 0/C 1 < 250 0V VCON 200 ppm VCXO pullability * VCON=1.65V, 1.65V 100 ppm VCON = 0 to On-chip Varicaps control range * 3.3V Supplies 4 18 pf 2.5V Supplies 7 18 Linearity * 10 % VCXO Tuning Characteristic 65 ppm/v VCON input impedance 60 k VCON modulation BW 0V VCON, -3dB 25 khz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. pf Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 2

3 4. General Electrical Specifications Supply Current (Loaded IDD PECL/LVDS 70/40 ma Outputs) 3.3V Supplies Operating Voltage V 2.5V Supplies V (LVDS), 3.3V Supply V (PECL), 3.3V Supply Output Clock Duty 1.25V (LVDS), 2.5V Supply V (PECL), 2.5V Supply Short Circuit Current 50 ma 5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS 77.76MHz 2.5 ps Period jitter peak-to-peak 77.76MHz 18.5 ps Integrated jitter RMS Integrated 12 khz to 20 MHz at 77.76MHz 0.5 ps 6. Phase Noise Specifications @100kHz UNITS Phase Noise relative to carrier Note: Phase Noise at VCON = 0V 77.76MHz dbc/hz Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 3

4 7. LVDS Electrical Characteristics Output Differential Voltage VOD mv Magnitude Change V OD mv Output High Voltage VOH RL = V Output Low Voltage VOL (see figure) V Offset Voltage VOS V Offset Magnitude Change V OS mv Power-off Leakage IOXD Vout = or = 0V 1 10 ua Output Short Circuit Current IOSD ma 8. LVDS Switching Characteristics Differential Clock Rise Time tr RL = ns CL = 10 pf Differential Clock Fall Time tf (see figure) ns LVDS Levels Test Circuit LVDS Switching Test Circuit 50 C L = 10pF V OD V OS V DIFF R L = C L = 10pF LVDS Transistion Time Waveform 0V (Differential) 80% 80% V DIFF 0V 20% 20% t R t F Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 4

5 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH RL = 50 to ( 2V) V Output Low Voltage VOL (see figure) V 10. PECL Switching Characteristics Clock Rise Time - PECL ns Clock Fall Time - PECL ns PECL Levels Test Circuit PECL Output Skew V 50% 50 t SKEW PECL Transistion Time Waveform DUTY CYCLE 45-55% 55-45% 80% 50% 20% t R t F Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 5

6 PAD ASSIGNMENT Pad # Name X (m) Y (m) Description 1 Optional Optional Ground. 2 Optional Optional Ground. 3 Optional Optional Ground. 4 Optional Optional Ground Ground. 6 Reserved Reserved for future use. 7 Optional BUF Optional Ground, buffer circuitry. 8 BUF Ground, buffer circuitry. 9 SEL Output type selector. Internal pull up. See Output Selection and Enable table on page 1. Internal pull up. 10 LVDS LVDS output. 11 PECL PECL output. 12 BUF V power supply, buffer circuitry. 13 Optional BUF Optional 3.3V power supply, buffer circuitry. 14 PECLB Complementary PECL output. 15 LVDSB Complementary LVDS output. 16 Not connected Not Connected. 17 BUF Ground, buffer circuitry. 18 Reserved Reserved for future use. 19 Reserved Reserved for future use. 20 Not connected Not Connected. 21 Optional Optional 3.3V power supply. 22 Optional Optional 3.3V power supply V power supply. 24 Optional Optional 3.3V power supply. 25 OESEL Used to choose between PECL and CMOS OE logic levels. See Output Selection and Enable table on page 1. Internal pull up 26 XIN Crystal input. See Crystal Specifications on page X Crystal output. See Crystal Specifications on page Not connected Not Connected. 29 Not connected Not Connected. 30 OE_CTRL Used to enable/disable the output(s). See Output Selection and Enable table on page VCON Voltage control input. Note: for optimal Phase Noise performance, it is recommended to bond all optional and pads. Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 6

7 ORDERING INFORMATION For part ordering, please contact our Sales Departm ent: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) Fax: (408) PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PL520-30DC P520-30DC Die Waffle Pack Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warr anty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc Fortune Drive San Jose, CA USA tel +1(408) fax +1(408) Rev 2/9/09 Page 7

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