Eastern Mediterranean University School of Computing and Technology CSIT 255 Computer Organization & Architecture SYSTEM BUSES 1 Introduction A computer consists of CPU (central processing unit) memory I/O components. These components are interconnected in some fashion to achieve basic function of computer. 2 Introduction At a top level, we can describe a computer system by 1. Describing external behavior of each component, that is, data and control signals that it exchanges with other components 2. Describing interconnection structure and controls required to manage use of interconnection structure. 3 Computer Components Von Neumann architecture is based on three key concepts: Data and instructions are stored in a single read-write memory. Contents of this memory are addressable by location, without regard to the type of data contained there. Execution occurs in a sequential fashion from one instruction to the next. 4
Computer Components We can think of process of connecting various components in desired configuration as a form of programming. Two approaches to programming: Hardwired programming. Constructing a configuration of hardware logical components to perform a particular set of arithmetic and logic operations on a set of data. 5 Computer Components Software. A sequence of codes or instructions, each of which supply necessary control signals to a general-purpose configuration of control and logical functions. Form CPU 6 Computer Components Several other components are needed to yield a functioning computer: I/O Components. A means to Accept data and instructions in some form and convert to an internal form of signals usable by system in form of an input module. Report results in form of an output module. 7 Computer Components Main memory Distinguished from external storage/peripherals. A place to temporarily store both: o Instructions. Data interpreted as codes for generating control signals. o Data. Data upon which components are performed. 8
Computer Components CPU exchanges data with memory. For this purpose, it typically makes use of: address register (MAR). Specifies address for next read or write. buffer register (MBR). Contains data to be written into or receives data read from memory. I/O address register (I/OAR). Specifies a particular I/O device. I/O buffer register (I/OBR). Used for exchange of data between an I/O module and CPU (or memory). module. A set of locations defined by sequentially numbered addresses. each location holds a binary number that can be either an instruction or data. 9 Computer Components 10 Basic function performed by a computer is execution of a program, which consists of a set of instructions stored in memory. Processor does actual work by executing instructions specified in program. Processing required for a single instruction is called an instruction cycle. 11 Instruction processing consists of two steps: Fetch. CPU reads an instruction from a location in memory. Program counter (PC) register keeps track of which instruction executes next. Normally, CPU increments PC after each fetch. Fetched instructions is loaded into instruction register (IR). 12
Execute. CPU executes instruction. Instruction execution may involve several operations. Instruction in instruction register (IR) specifies action, processor is to take. In general, these actions are: o CPU-. Data may be transferred from CPU to memory or vice-versa. o CPU-I/O. Data may be transferred between CPU and I/O module. o Data processing. CPU may perform some arithmetic or logical operation on data. o Control. An instruction may specify that sequence of execution be altered. 13 14 Consider a simple example using hypothetical machine where processor contains a single data register called an accumulator (AC). Both instruction and data are 16 bit long. 15 Next figure illustrates a partial program execution, showing relevant portions of memory and processor register where hexadecimal notation is used, in which each digit represents 4 bits. Program fragment shown adds contents of memory word at address 940 to content of memory word at address 941 and stores result at address 941. 16
1. PC contains 300, address of first instruction. This instruction (value 1940 in hexadecimal) is loaded into instruction register IR and PC is incremented. 2. First 4 bits (first hexadecimal digit (1)) in IR indicates that AC is to be loaded. Remaining 12 bits (3 hexadecimal digits) specify the address (940) from which data are to be used. 3. Next instruction (5941) is fetched from location 301 and PC is incremented. 4. Old contents of AC and content of location 941 are added and result is stored in AC. 5. Next instruction (2941) is fetched from location 302 and PC is incremented. 6. Content of AC are stored in location 941. 17 18 In this example, three instruction cycles, each consisting of a fetch cycle and an execute cycle, are needed to add content of location 940 to content of 941. With a more complex set of instructions, fewer cycles would be needed since Instructions may combine these categories. Execution cycle may perform more than one reference to memory. An instruction may specify I/O operation instead of memory reference. An instruction may specify an operation to be performed on a vector of numbers or a string of characters. 19 Expanded execution cycle includes: Instruction address calculation (iac). Determine address of next instruction. Instruction fetch (if). Read instruction from its memory location into processor. Instruction operation decoding (iod). Analyze instruction to determine operation type and operands. Operand address calculation (oac). If operation involves reference to an operand in memory or available via I/O, then determine address of operand. Operand fetch (of). Fetch operand from memory or read it in from I/O. Data operation (do). Perform indicated operation. Operand store (os). Write result into memory or out to I/O. 20
Interrupts Virtually all computers provide mechanism by which other modules (I/O, memory) may interrupt normal processing of processor. Interrupts are provided primarily as a way to improve processing efficiency. The most common classes of interrupts: Program. As a result of program execution. Timer. Generated by hardware timer within processor. I/O. To signal completion of I/O or error. Hardware failure. Generated by a failure such as power failure or memory parity error. 21 Interrupts Most external devices are much slower than processor. Suppose that processor is transferring data to a printer using instruction cycle. After each write operation, processor must pause and remain idle until printer catches up. Length of this pause may be order of many hundreds or even thousands of instruction cycles that do not involve memory. This is a very wasteful use of processor. 22 Without Interrupts Figure illustrates this state of affairs. Code segments 1, 2 and 3 refer to sequence of instructions that do not involve I/O. WRITE calls are to an I/O program that is a system utility and that will perform actual I/O operation. I/O program consists of 3 sections: A sequence of instructions (4) to prepare for actual I/O operation. Actual I/O programming. A sequence of instructions (5) to complete operation. Because I/O operation may take a relatively long time to complete, I/O program is hung up waiting for operation to complete; hence user program is stopped at point of WRITE call for some considerable period of time. 23 Interrupts With interrupts, processor can be engaged in executing other instructions while an I/O operation is in operation. I/O program that is invoked in this case consists only of preparation code and actual I/O command. After these few instructions have been executed, control returns to user program. Meanwhile external device is busy accepting data from computer memory and printing it. This I/O operation is conducted concurrently with execution of instructions in user program. When external device is ready to accept more data from processor, I/O module sends an interrupt request signal to processor. Processor responds by suspending operation of current program, branching off to a program to service that particular I/O device, known as interrupt handler. 24
Interrupts From point of view of user program, an interrupt is just that: an interruption of normal sequence of execution. When interrupt processing is completed, execution resumes at the same point. 25 Interrupts To accommodate interrupts, an interrupt cycle is added to instruction cycle. In interrupt cycle, processor checks to see if any interrupts have occurred, indicated by presence of an interrupt signal. 26 Interrupts When an interrupt signal is generated, processor: Suspends execution of current program and saves its context (such as PC and other registers). Sets PC to starting address on an interrupt handler routine. Processor now proceeds to fetch cycle and fetches first instruction in interrupt handler program. Processor can be employed much more efficiently with use of interrupts. 27 Interrupts Timing diagram based on flow of control without interrupts: 28
Interrupts Timing diagram based on flow of control with interrupts: 29 Interrupts Timing diagram based on flow of control with interrupts: 30 Multiple Interrupts Multiple interrupts can also occur. Two approaches can be taken to deal with multiple interrupts: Disable interrupts Processor will ignore further interrupts at same time as processing one interrupt. Interrupts remain pending and are checked after first interrupt has been processed. Interrupts handled in sequence as they occur. Define priorities Low priority interrupts can be interrupted by higher priority interrupts. When higher priority interrupt has been processed, processor returns to previous interrupt. 31 Multiple Interrupts (a) Sequential interrupt processing (Disabled interrupt). (b) Nested interrupt processing (Define priorities). 32
Example Time Sequence of Multiple Interrupts: Define Priorities Consider a system with 3 I/O devices: a printer (priority:2), a disk (priority:4), a communications line (priority:5). A user program begins at t=0. At t=10, a printer interrupt occurs. While printer interrupt at t=15, a communications line interrupt occurs. While communications line interrupt at t=20, a disk interrupt occurs. At t=40 after completing all of interrupts, control returns to user program. 33 Interconnection Structures Collection of paths connecting various modules of a computer (CPU, memory, I/O) is called the interconnection structure. Interconnection structure must support following types of transfers: to CPU. Processor reads an instruction or a unit of data from memory. CPU to memory. Processor writes a unit of data to memory. I/O to CPU. Processor reads data from an I/O device. CPU to I/O. Processor sends data to an I/O device. I/O to or from memory. An I/O module is allowed to exchange directly with memory, without going through processor, using Direct Access (DMA). 34 Bus Interconnection A bus is a shared transmission medium that connects two or more devices. A bus Must only be used by one device at a time. When used to connect major computer components (CPU, memory, I/O) is called a system bus. A system bus consists of from about 50 to hundreds of separate lines. Each line is assigned a particular meaning or function. 35 Bus Interconnection On any bus, lines can be classified into three functional groups: Data lines (data bus). Move data between system modules. Width (number of lines: 8, 16, 32, 64) is a key factor in determining overall system performance. Address lines. Designate source or destination of data on data bus. Width determines maximum possible memory capacity of system. Also used to address I/O ports. Typically: o High-order bits are used to select a particular module on bus. o Lower-order bits select a memory location or I/O port within module. 36
Bus Interconnection Control lines. Control access to and use of data and address lines. Typical control lines include: write. Causes data on bus to be written into addressed location. read. Causes data from addressed location to be placed on bus. I/O write. Causes data on bus to be output to addressed I/O port. I/O read. Causes data from addressed I/O port to be placed on bus. Transfer ACK. Indicates that data have been accepted from or placed on bus. 37 Bus Interconnection Bus request. Indicates that a module needs to gain control of bus. Bus grant. Indicates that a requesting module has been granted control of bus. Interrupt request. Indicates that an interrupt is pending. Interrupt ACK. Acknowledges that pending interrupt has been recognized. Clock. Used to synchronize operations. Reset. Initializes all modules. 38 Bus Interconnection Schemes 39 Bus Interconnection Operation of bus is as follows: If one module wishes to send data to another, it must: Obtain use of bus. Transfer data via bus. If one module wishes to request data from another, it must: Obtain use of bus. Transfer a request to other module over control and address lines. Wait for second module to send data. 40
Bus Interconnection Typical physical arrangement of a system bus: A system bus is a number of parallel electrical conductors. Each system component taps into some or all of bus lines (usually with a slotted conductor). A small system can be expanded by adding more boards. If a component on a board fails, that board can be removed and replaced. 41 Multiple-Bus Hierarchies If a great number of devices are connected to bus, performance will suffer. There are two main causes: Propagation delay. Time it takes for devices to coordinate use of bus. Bus may become a bottleneck as total data transfer demand approaches capacity of bus. Most computers systems use multiple buses, generally laid out in a hierarchy. 42 Multiple-Bus Hierarchies Traditional hierarchical bus architecture: There is a local bus that connects processor to a cache memory and that may support one or more local devices. Use of a cache structure insulates CPU from frequent accesses to main memory. Main memory can be moved off local bus onto a system bus. It is possible to connect I/O controllers directly onto system bus. A more efficient solution is to make use one or more expansion buses for this purpose. An expansion bus interface buffers data transfers between system bus and I/O controllers on expansion bus. An expansion bus interface insulates memory-toprocessor traffic from I/O traffic. 43 Traditional Hierarchical Bus Architecture Example 44
Multiple-Bus Hierarchies: High-performance Hierarchical Bus Architecture Traditional hierarchical bus breaks down as higher and higher performance is seen in I/O devices. Solution to this is to incorporate a high-speed bus Specifically designed to support high-capacity I/O devices. Brings high-demand devices into closer integration with processor and at the same time is independent of processor. Changes in processor architecture do not affect highspeed bus and vice-versa. This arrangement is sometimes known as a mezzanine architecture. 45 High-performance Hierarchical Bus Architecture Example 46 Elements of Bus Design There are a few basic parameters or design elements that serve to classify and differentiate buses: Bus type. Bus lines can be separated into two types: Dedicated. A line is permanently assigned either to one function or to a physical subset of computer components. Time multiplexing. Using same lines for multiple purposes (different purposes at different times). o Uses fewer lines, saving space and cost. o But more complex circuitry require in each module. o But potential reduction in performance since certain events that share lines cannot take place in parallel. 47 Elements of Bus Design Method of arbitration. Determining who can use bus at a particular time. Centralized. A single hardware device called bus controller or arbiter allocates time on bus. Distributed. Each module contains access control logic and modules act together to share bus. Both methods designate one device (either CPU or an I/O module) as master, which may initiate a data transfer with some other device which acts as a slave. 48
Elements of Bus Design Timing. Refers to way in which events are coordinated on bus. Synchronous timing. Occurrence of events on bus is determined by a clock. o Bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration. o A single 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot. o All other devices on bus can read clock line and all events start at beginning of a clock cycle. 49 Timing Diagram for Synchronous Read and Write Operations Processor places a memory address on address lines during first cycle and may declare various status lines. Once address line have stabilized, processor issues an address enable signal. For a read operation, processor issues a read command at start of second cycle. A memory module recognizes address and after a delay of a one cycle, places data on data lines. For a write operation, processor puts data on data lines at start of second cycle and issues a write command after data lines have stabilized. module copies information from data lines during third clock cycle. 50 Timing Diagrams There are two different signal levels representing binary 0 and binary 1. A signal transition on one line may trigger an attached device to make signal changes on other lines. Arrows are used on timing diagrams to show these dependencies. Overbar over signal name indicates that signal is active low. Signals are sometimes represented in groups. For example, if data are transmitted a byte at a time then eight lines are required. It is not important to know exactly value being transferred on such a group, but rather whether signals are present or not. A clock line is often part of a system bus. An electronic clock is connected to clock line and provides a repetitive, regular sequence of transitions. 51 Elements of Bus Design Asynchronous timing. Occurrence of one event on a bus follows and depends on occurrence of a previous event. o Allows system to take advantage of advance in device performance by having a mixture of slow and fast devices, using older and newer technology, sharing same bus. o But harder to implement and test than synchronous timing. 52
Timing Diagram for Asynchronous Read Operations Processor places address and status signals on the bus. After pausing for these signals to stabilize, it issues a read command, indicating presence of valid address and control signals. Appropriate memory decodes address and responds by placing data on data line. Once data lines have stabilized, memory module asserts acknowledged line to signal processor that data are available. 53 Timing Diagram for Asynchronous Write Operations Master places data on data line at same time that is puts signals on status and address lines. module responds to write command by copying data from data lines and then asserting acknowledge line. 54 Elements of Bus Design Bus width. Width of data bus has an impact on system performance. Wider data bus, the greater the number of bits transferred at one time. Wider address bus, the greater the range of locations that can be referenced. 55 Elements of Bus Design Data transfer type. All buses support both write (master to slave) and read (slave to master) transfers. Data (2nd cycle) 56
Elements of Bus Design Combination operations o Read-modify-write A read followed immediately by a write to same address. Address is only broadcast once, at beginning of operation. Indivisible, to prevent access to data element by other potential bus masters. Principle purpose is to protect shared memory in a multiprogramming system. o Read-after-write. Indivisible operation consisting of a write followed immediately by a read from same address (for error checking purposes). 57 Elements of Bus Design o Block data transfer. Some bus systems also support a block data transfer. In this case, One address cycle followed by n data cycles. First data item is transferred to or from specified address. Remaining data items are transferred to or from subsequent addresses. 58 Peripheral component interconnect (PCI) Peripheral component interconnection (PCI) Is a high-bandwidth Is processor independent Can function as a mezzanine or peripheral bus PCI delivers better system performance for high-speed I/O subsystems. Current standard Allows use of up 64 data lines at 66 MHZ. Requires very few chips to implement. Supports other buses attached to PCI bus. Public domain, initially developed by Intel to support Pentiumbased systems. Supports a variety of microprocessor-based configurations, including multiple-processors. Uses synchronous timing and centralized arbitration. 59 Peripheral component interconnect (PCI) Typical desktop system (a single processor system) Note: Bridge acts as a data buffer so that speed of PCI bus may differ from that of processor s I/O capability. 60
Peripheral component interconnect (PCI) Typical server system (a multiprocessor system) Note: In a multiprocessor system, one or more PCI configurations may be connected by bridges to processor s system bus. 61 Peripheral component interconnect (PCI) There are 51 optional signal lines for PCI, divided into following groups: Interrupt pins. Not shared, each PCI device has its own interrupt line or lines to an interrupt controller. Cache support pins. Support a memory on PCI that can be cached in processor or another device. 64-bit bus extension pins. 32 additional time-multiplexed lines for addresses and data, plus lines to interpret and validate these and to provide agreement between two PCI devices on use of these. JTAG/boundary scan pins. Support testing produces from IEEE Standard 1149.1. 62 Peripheral component interconnect (PCI) Every data transfer on PCI bus is a single transaction of one address phase and one or more data phases. 63 System Bus The old Architecture In original PC design CPU, RAM and I/O devices were connected on one and the same bus, and everything ran synchronously (at a common speed). In original PC architecture, there was only one bus with one speed. 64
First Division of System Bus System bus is seperated from I/O bus, so that two buses could work at different clock frequencies. By letting CPU and RAM work on their own bus, independent of I/O devices, their speeds could be increased. With this architecture, I/O bus is separate from system bus (80386). 65 System Bus Clock Doubling With introduction of 80486, CPU clock frequency could be increased so much that RAM could no longer keep up. Intel therefore began to use clock doubling in 80486 processor. RAM available at time couldn t keep up with 66 MHz speed at which an 80486 could work. Solution was to give CPU two working speeds. An external clock frequency An internal clock frequency 66 System Bus Clock Doubling Inside processor, clock frequency of system bus is multiplied by a factor of 2, doubling working speed. Since RAM only works half as fast as CPU, 486 was given a built-in cache, to reduce imbalance between slow RAM and fast processor. Cache ensures greater efficiency in transfer of data to CPU. Bus system for an 80486 processor. 67 System Bus Clock Doubling Clock doubling made it possible to develop processors with higher clock frequencies. At time Pentium was introduced, new RAM modules became available, and system bus was increased to 66 MHz. 68
System Bus Clock Doubling In case of Pentium II and III, system bus was increased to 100 and 133 MHz, with internal clock frequency set to a multiple of these. Bus system for a Pentium III processor. 69 Review Questions 70 Exercise Review Question 1 1 Suppose the hypothetical machine of Figure 1.1. Show the program execution using Figure 1.2 for the following program: 1. Load AC from memory location 550. 2. Subtract content of memory location 551 from AC. 3. Store AC to memory location. Assume that the values retrieved from memory location 550 is 9 and the values retrieved from memory location 551 is 6. 0 3 4 15 Opcode Address (a) Instruction format Program counter (PC) = Address of instruction Instruction register (IR) = Instruction being executed Accumulator (AC) = Temporary storage (c) Internal 0 1 15 S Magnitude (b) Integer format Figure 1.1 Characteristics of a hypothetical machine 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory 0110 = Subtract memory from AC (d) Partial list of opcodes 71 Review Question 1 Figure 1.2 Program execution 300 301 302 300 301 302 300 301 302 300 PC AC IR Step 1 PC AC IR Step 3 PC AC IR Step 5 300 301 302 300 301 302 300 301 302 300 PC AC IR Step 2 PC AC IR Step 4 PC AC IR Step 6 72
Solution Review Question 1 Figure 1.2 Program execution 300 1550 301 6551 302 2 300 1550 301 6551 302 2 300 1550 301 6551 302 2 300 PC AC 1550 IR Step 1 301 PC 0009 AC 6551 IR Step 3 302 PC 0003 AC 2 IR Step 5 300 1550 301 6551 302 2 300 1550 301 6551 302 2 300 301 302 1550 6551 2 0003 300 PC 0009 AC 1550 IR Step 2 301 PC 0003 AC 6551 IR Step 4 302 PC 0003 AC 2 IR Step 6 73 Review Question 2 Consider a system with three I/O devices as A printer: Priority = 2 A disk: Priority = 4 A communication line: Priority = 5 Suppose that a user program begins and a disk interrupt occurs. While disk interrupt carries on, a communication line interrupt occurs. Then while communication interrupt carries on, a printer interrupt occurs. After completing all of interrupts, control returns to user program. i. Assume a sequential interrupt processing and draw the sequence diagrams showing transfer of control. ii. Assume a nested interrupt processing and draw the sequence diagrams showing transfer of control. 74 A printer: Priority = 2 A disk: Priority = 4 A communication line: Priority = 5 Suppose that a user program begins and a disk interrupt occurs. While disk interrupt carries on, a communication line interrupt occurs. Then while communication interrupt carries on, a printer interrupt occurs. After completing all of interrupts, control returns to user program. i. Assume a sequential interrupt processing and draw the sequence diagrams showing transfer of control. Solution Review Question 2 User Program Disk Interrupt Communication Interrupt Printer Interrupt 75 A printer: Priority = 2 A disk: Priority = 4 A communication line: Priority = 5 Suppose that a user program begins and a disk interrupt occurs. While disk interrupt carries on, a communication line interrupt occurs. Then while communication interrupt carries on, a printer interrupt occurs. After completing all of interrupts, control returns to user program. ii. Assume a nested interrupt processing and draw the sequence diagrams showing transfer of control. Solution Review Question 2 User Program Disk Interrupt Communication Interrupt Printer Interrupt 76