PD -93992A AUTOMOTIVE MOSFET IRF1405S IRF1405L Typical Applications Electric Power Steering (EPS) Anti-lock Braking System (ABS) Wiper Control Climate Control Power Door Benefits Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Description Stripe Planar design of HEXFET Power MOSFETs utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings HEXFET Power MOSFET Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 10V 131 I D @ T C = C Continuous Drain Current, V GS @ 10V 93 A I DM Pulsed Drain Current 680 P D @T C = 25 C Power Dissipation 200 W Linear Derating Factor 1.3 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 590 mj I AR Avalanche Current See Fig.12a, 12b, 15, 16 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting Torque, 6-32 or M3 screw 10 lbf in (1.1N m) Thermal Resistance G D S D 2 Pak IRF1405S V DSS = 55V R DS(on) = 5.3mΩ I D = 131A TO-262 IRF1405L Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θja Junction-to-Ambient (PCB mount)ˆ 40 www.irf.com 1 12/07/04
IRF1405S/L Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.057 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 4.6 5.3 mω V GS = 10V, I D = 101A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = 10V, I D = 250µA g fs Forward Transconductance 69 S V DS = 25V, I D = 110A I DSS Drain-to-Source Leakage Current 20 V µa DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 200 V GS = 20V na Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge 170 260 I D = 101A Q gs Gate-to-Source Charge 44 66 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 62 93 V GS = 10V t d(on) Turn-On Delay Time 13 V DD = 38V t r Rise Time 190 I D = 101A ns t d(off) Turn-Off Delay Time 130 R G = 1.1Ω t f Fall Time 110 V GS = 10V Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 5480 V GS = 0V C oss Output Capacitance 1210 pf V DS = 25V C rss Reverse Transfer Capacitance 280 ƒ = 1.0MHz, See Fig. 5 C oss Output Capacitance 5210 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 900 V GS = 0V, V DS = 44V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 1500 V GS = 0V, V DS = 0V to 44V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 131 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 680 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 101A, V GS = 0V t rr Reverse Recovery Time 88 130 ns T J = 25 C, I F = 101A Q rr Reverse RecoveryCharge 250 380 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
IRF1405S/L I D, Drain-to-Source Current (A) 0 10 VGS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 0 VGS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 1 T J = 25 C 0.1 1 10 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 10 T J = 175 C 0.1 1 10 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 0 10 T J = 25 C T J = 175 C V DS = 25V 20µs PULSE WIDTH 1 4 6 8 10 12 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 169A 2.5 2.0 1.5 1.0 0.5 V GS = 10V 0.0-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance(pF) IRF1405S/L 000 00 0 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 1 10 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 16 12 8 4 I = D 101A V DS = 44V V DS = 27V FOR TEST CIRCUIT SEE FIGURE 13 0 0 60 120 180 240 300 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 0 10 T J = 175 C T J = 25 C V GS = 0 V 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V SD,Source-to-Drain Voltage (V) 00 I D, Drain Current (A) 0 10 OPERATION IN THIS AREA LIMITED BY R DS(on) 10us us 1ms 10ms TC = 25 C TJ = 175 C Single Pulse 1 1 10 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
IRF1405S/L 160 LIMITED BY PACKAGE V DS R D I D, Drain Current (A) 120 80 40 R G V GS 10V Pulse Width 1 µs Duty Factor 0.1 % D.U.T. Fig 10a. Switching Time Test Circuit - V DD V DS 90% 0 25 50 75 125 150 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% V GS t d(on) t r t d(off) t f Fig 10b. Switching Time Waveforms 1 Thermal Response (Z thjc ) 0.1 0.01 D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J= P DM x Z thjc TC 0.001 0.00001 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th), Variace ( V ) IRF1405S/L 15V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 1400 1200 0 800 600 400 200 I D TOP 41A 71A BOTTOM 101A 0 25 50 75 125 150 175 Starting T, Junction Temperature( J C) I AS Fig 12b. Unclamped Inductive Waveforms Q G Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V Q GS Q GD 4.0 V G 3.5 Current Regulator Same Type as D.U.T. Charge Fig 13a. Basic Gate Charge Waveform 3.0 2.5 I D = 250µA 50KΩ 12V.2µF.3µF 2.0 V GS D.U.T. V - DS 1.5-75 -50-25 0 25 50 75 125 150 175 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) IRF1405S/L 0 Duty Cycle = Single Pulse 10 0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses 1 0.1 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E00 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 600 500 400 300 200 0 TOP Single Pulse BOTTOM 10% Duty Cycle I D = 101A 25 50 75 125 150 175 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 15, 16: (For further info, see AN-5 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure 11) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc Fig 16. Maximum Avalanche Energy I av = 2DT/ [1.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRF1405S/L Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =10V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 17. For N-channel HEXFET power MOSFETs 8 www.irf.com
D 2 Pak Package Outline (Dimensions are shown in millimeters (inches)) IRF1405S/L D 2 Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 0 = 2000 WEEK 02 A = AS S E MB LY S IT E CODE www.irf.com 9 F530S F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L
IRF1405S/L TO-262 Package Outline (Dimensions are shown in millimeters (inches)) IGBT 1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" OR INTERNATIONAL RECTIFIER LOGO INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE AS S EMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE 10 www.irf.com
IRF1405S/L D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065) 10.90 (.429) 10.70 (.421) 11.60 (.457) 11.40 (.449) 16.10 (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Starting T J = 25 C, L = 0.11mH R G = 25Ω, I AS = 101A. (See Figure 12). ƒ I SD 101A, di/dt 210A/µs, V DD V (BR)DSS, T J 175 C Pulse width 400µs; duty cycle 2%. 26.40 (1.039) 24.40 (.961) 3 C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. ˆ This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. 30.40 (1.197) MAX. 4 Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com 11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/