CRYSTAL DEFECTS: Point defects

CRYSTAL DEFECTS: Point defects Figure 10.15. Point defects. (a) Substitutional impurity. (b) Interstitial impurity. (c) Lattice vacancy. (d) Frenkeltype defect. 9 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 1 CRYSTAL DEFECTS: LINE DEFECTS or DISLOCATIONS Edge dislocation: there is an extra plane of atoms AB inserted into the lattice Screw dislocation: produced by cutting the crystal partway and pushing the upper part one lattice spacing over Agiscono da siti per precipitazioni da per impurezze metalliche Edge dislocation in a cubic lattice Screw dislocation in a cubic lattice 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII

CRYSTAL DEFECTS: AREA DEFECTS Twins: a change in the crystal orientation across a plane Grain boundary: a transition between crystals having no particular orientational relationship to one another Appear during the crystal growth Stacking fault: the stacking sequence of atomic layer is interrupted Intrinsic stacking fault Extrinsic stacking fault 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 3 CRYSTAL DEFECTS: VOLUME DEFECTS Semiconductor Devices, /E by S. M. S Copyright 00 John Wiley & Sons. Inc. All righ reserve Precipitates of impurities or dopant atoms because of the inherent solubility of the impurity in the host lattice. The solubility of most impurities decreases with decreasing temperature. If an impurity is introduced to the maximum concentration allowed by its solubility and the crystal is then cooled, an equilibrium state is achieved by precipitating the impurity atoms in excess of the solubility level. The volume mismatch between the host lattice and the precipitates results in dislocations. Figure 10.18. Solid solubilities of impurity elements in silicon. 11 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 4

MATERIAL PROPERTIES: Property Czochralski Float zone Requirements for ULSI ρ (P) n-type (Ω cm) 1-50 1-300 and up 4-40 and up ρ(b) p-type (Ω cm) 0.005-50 1-300 and up 4-40 and up ρ gradient (%) 5-10 0 <1 τ(µs) 30-300 50-500 300-1000 Oxygen (ppma) 5-5 not detected Carbon (ppma) 1-5 0.1-1 <0.1 Dislocation (per cm ) <500 <500 <1 Diameter (mm) up to 00 up to 100 up to 300 Slice bow (µm) <5 <5 <5 Slice taper (µm) <15 <15 <5 Surface flatness (µm) <5 <5 <1 Heavy metal impurity (ppma) <1 <0.01 <0.001 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 5 1. Dissolution of oxygen from the silica crucible and transport of carbon to the melt from the graphite susceptor during crystal growth.. Carbon atoms in silicon occupy substitutional lattice sites. Formation of defects 3. Oxygen act as donor, distorting the resistivity -> unintentional doping 4. Oxygen in an interstitial lattice site can increase the yield strength of silicon 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 6

Figure 10.19. Denuded zone width for two sets of processing conditions. Inset shows a schematic of the denuded zone and gettering sites in a wafer cross section. 1 Gettering thermal treatment oxygen evolution lowers the oxygen content at the surface (denuded zone). Further thermal cycles to promote the formation of oxygen precipitates in the interior of the wafer for gettering impurities. Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 7 Figure 10.0. Three common susceptors (graphite) for chemical vapor disposition CVD (APCVD, LPCVD) Mechanism of CVD: The reactants are transported to the substrate region Transfer to the substrate surface where they are absorbed A chemical reaction occurs, catalyzed at the surface, followed by growth of the epitaxial layer The gaseous products are desorbed into the main gas stream The reaction products are transported out of the reaction chamber Pancake susceptor Horizontal susceptor Barrel susceptor 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 8

Epitaxial growth The substrate wafer acts as the seed crystal Epitaxial layers can be grown at a temperature substantially below the melting point 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 9 Sources used for silicon CVD (or VPE) growth: Silicon tetrachloride SiCl 4 ; dichlorosilane SiH Cl ; trichlorosilane SiHCl 3 ; silane SiH 4. Main reaction (temperature SiCl Additional competing SiCl 4 4 (gas) + H (gas) + (gas) Si(solid) Si(solid) + 4HCl(gas) reaction : SiCl If the SiCl 4 concentration is too high, etching rather than growth of silicon will take part. 100 C) : (gas) Figure 10.1. Effect of SiCl 4 concentration on silicon epitaxial growth. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 10

Sources used for silicon doping: 1. P-type: diborane (B H 6 ). N-type: phosphine (PH 3 ) and arsine (AsH 3 ) 3. Diluent gas: hydrogen 4. High temperature are needed to give sufficient mobility to adsorbed atoms for finding their proper position Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 11 Figure 10.5. Schematic illustration of (a) lattice-matched, (b) strained, and (c) related heteroepitaxial structures. 19 Homoepitaxy is structurally identical to the lattice-matched heteroepitaxy. Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 1

Figure 11.1. Schematic cross section of a metal-oxide-semiconductor fieldeffect transistor (MOSFET). 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 13 Figure 11.. Schematic cross section of a resistance-heated oxidation furnace. Oxidation temperature : 900-100 C; gas flow rate = 1000 sccm 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 14

Si(solid) Si(solid) + + O H O (gas) SiO SiO (solid) (solid) + H (gas) Figure 11.3. Growth of silicon dioxide by thermal oxidation. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 15 For SiO thickness = 100 nm what is the Si thickness being consumed A Si =8.9 g/mole ; ρ Si =.33 g/cm 3 ; A SiO =60.8 g/mole ; ρ Si =.1 g/cm3 ; Molar volume: V si =8.9/.33 cm 3 /mole =1.06 cm 3 /mole; V sio =60.8/.1 cm 3 /mole =7.18 cm 3 /mole; 1 mole of Si is converted in 1 mole of SiO (Si thickness) x area (SiO thickness) x area = (Si thickness) (SiO thickness) = (Si molar volume) (SiO molar volume) = 1. 06 7. 18 = 0. 44 A 44 nm thick silicon layer is consumed 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 16

Basic structural unit of silicon dioxide Two-dimensional representation of a quartz crystal lattice. Two-dimensional representation of the amorphous structure of SiO (silica). ρ silica =.1 g/cm 3 ;ρ quartz =.65 g/cm 3 The silica structure is quite open because only 43% of the space is occupied by SiO molecules; this accounts for the lower density and allows impurities (e.g. Na) to enter and diffuse 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 17 Oxide thickness : x D C 0 k (t + τ) = 1+ 1 k D C1 C 0 =surface conc. of oxidants F 1 =flux of oxidants through SiO F =flux of oxidants through Si C 1 =conc. Of oxidants in the oxide Early stages: x varies linearly with time; surface reaction is rate limiting B x = (t + τ) A As the oxide layer becomes thicker, the reaction becomes diffusion limited x = B (t + τ) x = B (t + τ) A Figure 11.5. Basic model for the thermal oxidation of silicon. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 18

Figure 11.6. Linear rate constant versus temperature. Dependence on crystal orientation Figure 11.7. Parabolic rate constant versus temperature. YES NO Thin oxide (gate oxide) dry oxidation Thick oxide (field oxide) wet oxidation 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 19 Figure 11.8. Experimental results of silicon dioxide thickness as a function of reaction time and temperature for two substrate orientations. (a) Growth in dry oxygen. (b) Growth in steam. 3 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 0

Dielectric Deposition Used mainly for insulation and passivation of discrete devices. Hot-wall, reduced-pressure reactor. (LPCVD) Parallel-plate plasma deposition reactor. 4 rf, radio frequency. (PECVD) Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. Low deposition temperature Limited capacity 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 1 The best dielectric properties are obtained with thermally grown films CVD oxides are used instead to complement the thermal oxides. To insulate multilever metallisation A layer of undoped silicon dioxide is used To mask ion implant or diffusion To increase the thickness of thermally grown field oxides. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII

SiO Low temperature deposition (300-500 C) SiH + 450 C 4 + O SiO H Both at atmospheric pressure or at low pressure (LPCVD) The low temperature allows the deposition of SiO on Al Intermediate temperature deposition (500-800 C) 700 C Si(OC H5 ) 4 + O SiO + by - products Low pressure (LPCVD) decomposition of TEOS (tetraethylorthosilicate) vaporized from a liquid source. No suitable to cover Al. Suitable for polysilicon gates requiring a uniform insulating layer due to an enhance surface mobility at high temperature 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 3 SiO Properties of SiO films Property Thermally grown SiH 4 +O TEOS @1000 C @450 C @700 C Composition SiO SiO (H) SiO Density (g/cm 3 )..1. Refractive index(68 nm)1.46 1.44 1.46 Dielectric strength >10 7 V/cm 8 10 6 V/cm 10 7 V/cm Etch rate (100:1 H 0:HF)3 nm/min 6 nm/min 3 nm/min Low density films deposited below 500 C 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 4

SiO Figure 11.1. Step coverage of deposited films. (a) Conformal step coverage. (b) Nonconformal step coverage. 4 The uniformity of the film thickness, regardless to the topography is due to the rapid micgration of reactants after adsorption on the step surface. TEOS gives a nearly conformal coverage. Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 5 Silicon Nitride LPCVD High temperature (750 C) Stoichiometric composition Si 3 N 4, High density (.9-3.1 g/cm 3 ) Are used to passivate devices because they serve as a good barrier to the diffusion of water or sodium. Used as masks for selective oxidation of Si because oxidation is very slow. Because of the low pressure good film uniformity 3 SiCl + 750 C H + 4NH3 Si3N4 + 6HCl 6H Silicon Nitride deposited by LPCVD is an amorphous dielectric containing up to 8 atomic percent of H. Etch rate is less than 1 nm/min Resistiviy 10 16 Ω cm; ε=7; dielectric strength = 10 7 V/cm 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 6

Silicon Nitride PECVD Low temperature (300 C) Non stoichiometric composition Low density (.4-.8 g/cm 3 ) Because of the low temperature deposition,is used over fabricated devices for final passivation. Excellent scratch protection, moisture barrier and prevents sodium diffusion. SiH 4 SiH + 4 NH + N 3 300 C in Ar plasma SiNH 3H 300 C in N discharge SiNH + The products are strongly dependent on deposition conditions. + 3H Large H concentration (0-5%), film resistivities from 10 5 to 10 1 Ω cm, dielectric strength from 10 6 to 6x10 6 V/cm. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 7 Low dielectric constant materials As devices continue to scale down to the deep submicron region, they require multilevel interconnection architecture to minimize the time delay due to parasitic resistance and capacitance. Long interconnections-propagation delay due to RC To reduce RC time constant of ULSI circuitis,inteconnection materials with low resistivity and interlayer films with low capacitance are required To reduce parasitic capacitance Increasing thickness of interlayer dielectric gap filling difficult Decreasing wiring height and area increase of interconnect resistance Materials with low dielectric constant 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 8

Estimate the intrinsic RC value of two parallel Al wires A=0.5 µm x0.5 µm, L=1mm and separated by a dielectric layer 0.5 µm thick. Al resistivity is.7 µω cm. 5 L y L 6 0.1 14 5 10 0.1 RC = ρ ε ε0 =.7 10 8.85 10 ε 10 5 x y t 5 10 5 10 = 0.96 ε (ps) = Dielectric ε Si 3 N 4 7 Black diamond.7-3 Teflon 1.93 Fluorosilicate glass 3.5-4.0 y= 0.5 µm L=1 mm x=0.5 µm t=0.5 µm 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 9 Figure 11.14. Calculated gate and interconnect delay versus technology generation. The dielectric constant for the low-k material is.0. Both Al and Cu are 0.8 µm thick and 43 µm long. Semiconductor Devices, /E by S. M. Sze Copyright 00 John Wiley & Sons. Inc. All rights reserved. 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 30

High dielectric constant materials Required for dynamic random access memory (DRAM). The storage capacitor in a DRAM has to maintain a certain value of capacitance for proper operation (40 ff). C = ε ε 0 A/d The dielectric constant of the film must be increased. Barium strontium titanate (BST) ε =300-500 Lead zirconium titanate (PZT) ε >1000 Tantalum oxide (Ta O 5 ) ε =5 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 31 Polysilicon deposition Why polysilicon? Electrode reliability: the inferior time to breakdown of Al electrode is due to the migration of Al into the Thin oxide under the electrical field Polysilicon is used as a diffusion source to create shallow junctions Polysilicon is used to ensure ohmic contact to crystalline silicon Figure 11.15. Maximum time to breakdown versus oxide thickness for a polysilicon electrode and an aluminum electrode. 10 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 3

Polysilicon deposition SiH + 600 C 4 Si H LPCVD 5-50 Pa A columnar structure results when polysilicon is deposited at a temperature of 600-650 C. Grain size 0.03-0.3 µm. The initially deposited film appears amorphous when deposition occurs below 600 C Figure 11.16. Effect of silane concentration on the polysilicon deposition rate. 4 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 33 Metallization Physical vapor deposition: evaporations occus when a source of meaterial is heated above its melting point in an evacuated chamber. The source can be molten by resistance heating, by rf heating or with a focused electron beam. In ion beam sputtering a source of ions is accelerated toward the target and impinged on its surface. The sputtered material deposits on a wafer that is placed facing the target. To increase the sputter deposition rate, a third electrode is used which provides more electrons for ionisation or to use a magnetic field (ECR) to capture and spiral electrons, increasing their ionising efficiency in vicinity of the sputterd target (MAGNETON SPUTTERING: for Al 1 µm/h) 10/11/004 Ettore Vittone- Fisica dei Semiconduttori - Lectio XIII 34