ELG4139: DC to AC Coverters Coverts DC to AC power by switchig the DC iput voltage (or curret) i a pre-determied sequece so as to geerate AC voltage (or curret) output. I DC I ac + + V DC V ac
Square Wave Coverter SQUARE-WAVE INVERTER S1,S ON; S3,S4 OFF for t 1 < t < t v O T1 D1 T3 D3 S1 S3 V DC V DC I O + V O - V DC + v O t 1 t t T4 D T D4 S4 S EQUIVALENT CIRCUIT S3,S4 ON ; S1,S OFF for t < t < t 3 v O S1 S3 S1 S3 S4 S V DC S4 + v O S t t 3 t -V DC
Harmoics Filterig DC SUPPLY INVERTER (LOW PASS) FILTER LOAD L + v O 1 C + v O BEFORE FILTERING AFTER FILTERING v O 1 v O Output of the iverter is chopped AC voltage with zero DC compoet. It cotai harmoics. A LC sectio low-pass filter is ormally fitted at the iverter output to reduce the high frequecy harmoics. I some applicatios such as UPS, high purity sie wave output is required. Good filterig is a must. I some applicatios such as AC motor drive, filterig may ot required.
Fourier Series for Harmoics Aalysis t b a a v f d v f b d v f a d v f a o o where si cos 1 ) ( Fourier Iverse ("si" term) )si ( 1 ("cos" term) )cos ( 1 ("DC" term) ) ( 1 Fourier Series 1 0 0 0 V dc -V dc =t 0 0 0 si si 0 cos cos 0 1 d d V b d d V a d V d V a dc dc dc dc o Harmoics of Square Wave
Half-Bridge Iverter V dc + V C1 - V C + - G V o R L S 1 + S Vdc 0 Vdc S1 ON S OFF S1 OFF S ON t Also kow as the Iverter Leg! Both capacitors have the same value. Thus the DC lik is equally spilt ito two. The top ad bottom switch has to be complemetary. Meaig, If the top switch is closed (ON), the bottom must be OFF, ad vice-versa.
Sigle Phase Full Bridge V RG + LEG R LEG R' V dc t + V dc - V dc - G S1 R V o - S3 R' V R ' G V dc V dc t + V dc - S4 S V dc V o V dc Vo V V RG R ' G G is "virtual groumd" t V dc Sigle phase full bridge is built from two half-bridge leg. The switchig i the secod leg is delayed by 180 degrees from the first leg.
Three Phase Iverter +V dc + V dc / S1 S3 S5 G R Y B + i R i Y i B V dc / S4 S6 S Each leg is delayed by 10 degrees i a i b Z R Z Y Z B N
Pulse Width Modulatio h( x) if( k( x) c( x) 1if( k( x) c( x) 10) ) 1 1 M 1 0 Modulatig Waveform Carrier waveform t 1 t Siusoidal modulatig waveform, v m (t) Carrier, v c (t) t 1 V dc t' 1 t' Regular samplig waveform, v s (t) 0 V dc t t 0 1 t t 3 t t 4 5 v pwm t Regular samplig PWM Triagulatio method (Natural samplig). Amplitudes of the triagular wave (carrier) ad sie wave (modulatig) are compared to obtai PWM waveform. Aalogue comparator may be used. Basically a aalogue method. Its digital versio, kow as REGULAR samplig is widely used i idustry.
Typical Cofiguratio with 3-Wire DC Source Load curret may ot reverse at the same istats as does the load voltage. Curret may lead or lag the output voltage due to the presece of capacitace ad/or iductace i the load circuit. Diodes D 1 ad D i atiparallel with each trasistors permit load curret to flow if ecessary. For positive voltage we should tur o the trasistor coected to the positive half, ad for egative voltage we should tur o the trasistor coected to the egative half.
I the leadig curret case, the output curret reverses its directio at t x. Output voltage reverses its directio at T/. Therefore, from t x to T/ the output curret will flow through D 1. I the laggig curret case, the output curret reverses its directio at t Y. Output voltage reverses its directio at T/. Therefore, from T/ to t Y the output curret will flow through D.
From the curves, it may be see that the thyristors may start to coduct at differet istats i the half cycle, depedig o the ature of the load. To esure that the thyristors will begi to coduct whe required, each must be gated cotiuously throughout the half cycle.
Sigle-Phase Half-Bridge Iverter (Rashid, Pretice Hall) 3-wire DC source Cosists of choppers, 3-wire DC source Trasistors switched o ad off alterately Need to isolate the gate sigal for Q 1 (upper device) Each provides opposite polarity of V s / across the load
Q 1 o, Q off, v o = V s / Peak Reverse Voltage of Q = V s
Q 1 off, Q o, v o = -V s /
Waveforms with Resistive Load
Output Voltage rms value of the output voltage, V o V o T o T o 0 1 Vs Vs dt 4
Fourier Series of the Istataeous Output Voltage 1 0 0 1,3,5,.. cos( ) si( ), 0 1 si( ) ( ) si( ) ( ) 1,3,5,... si( ) o o o s s s s o a v a t b t a a V V b t d t t d t V b V v t
Load Curret for a Highly Iductive Load Trasistors are oly switched o for a quarter-cycle, or 90
Performace Parameters Harmoic factor of the th harmoic (HF ) HF V o for >1 V o1 V o = rms value of the th harmoic compoet V 01 = rms value of the fudametal compoet Total Harmoic Distortio (THD): Measures the closeess i shape betwee a waveform ad its fudametal compoet THD 1 ( V ) V o1,3,... 1 o
Performace Parameters Distortio Factor (DF): Idicates the amout of HD that remais i a particular waveform after the harmoics have bee subjected to secod-order atteuatio. 1 1 Vo DF V o1,3,... V DF V o o1 for >1 Lowest order harmoic (LOH): The harmoic compoet whose frequecy is closest to the fudametal, ad its amplitude is greater tha or equal to 3% of the amplitude of the fudametal compoet.
Sigle-Phase Full-Bridge Iverter Cosists of 4 choppers ad a 3-wire DC source Q 1 -Q ad Q 3 -Q 4 switched o ad off alterately Need to isolate the gate sigal for Q 1 ad Q 3 (upper) Each pair provide opposite polarity of V s across the load
Q 1 -Q o, Q 3 -Q 4 off, v o = V s + V s -
Q 3 -Q 4 o, Q 1 -Q off, v o = -V s - V s +
Whe the Load is Highly Iductive Tur Q 1 -Q off Q 3 -Q 4 off
Tur Q 3 -Q 4 off Q 1 -Q Off
Load Curret for a Highly Iductive Load
Three-Phase Iverter
Desig Costraits of a Pure Sie wave Iverter Quatity Voltage Details Covert 1VDC to 10 VAC Power Provide 300 W cotiuous Efficiecy Waveform Total Harmoic Distortio > 90% efficiecy Pure 60 Hz siusoidal < 5% THD Physical Dimesios 8 x 4.75 x.5 Cost $175.00
Required Compoets for Desig 1 V DC Iput from vehicle battery) PWM Cotrol Circuit Half-bridge Coverter Trasformer Low-pass Filter 10 VAC, 60 Hz, 300 W Output Full-bridge Iverter Siusoidal PWM Cotroller
PWM Cotroller Produces two complemetary pulses to cotrol half-bridge trasistors. Problem: Voltage may drop whe the iput voltage is decreased. Solutio: A feedback etwork may be added for voltage regulatio.
Chops the 1 VDC to produce a 1 V, 100 khz, square pulse Problem: IRF740A MOSFETs has a R ds (o) = 0.55Ω, resultig i high power losses. Solutio: Choose IRF530 MOSFETs with a R ds (o) = 0.16 Ω Half-Bridge Coverter
Coverts 170 VDC to a 10 Vrms, 60 Hz, sie wave IRF740A MOSFETs Vdss = 400 V Id = 10 A Rds(o) = 0.55 Ω Full-bridge Iverter
Software Flow Diagram (Dr. Yaroslav Koshka) Iitialize all variables Cout0 = 300 (300 duty cycles) o 300 duty cycle values? yes Output 1 = high, Output = low duty cycle table (icremet poiter) Duty cycle ad samplig period timer Output 1 = low, Output = high Decremet Cout0 by 1 o Has duty cycle bee reached? yes o Oe Samplig Period? ye s
Low-pass Filter d order L-C filter Filters to retai a 60 Hz fudametal frequecy Few compoets Hadle curret Wid iductor (fie tue)
PCB Layout
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