5 Coon-ource Aplifier tage Two types of coon-source aplifiers will be investigated in lab projects. One is with the source grounded and the other is with a current-source bias (dual power supply). In Units 5.1 and 5. we discuss various aspects of the coon-source stage with grounded source, in Unit 5.3 we take up circuit-linearity considerations, and in Unit 5.4 we cover the basics of the dual-power-supply aplifier. Both aplifiers are based on the PMO, as in the projects. The first two units are ostly a review of the basic aplifier as presented in previous units, to reinforce the basic concepts. The PMO replaces the NMO (Units and 4) in this unit, to provide failiarity with the opposite polarity in bias considerations and to illustrate that the linear odel applies in the sae anner for both transistor types. 5.1 C (Bias) Circuit c circuits for the grounded-source aplifier are shown in Fig. 5.1 (PMO). The circuit in (a) is based on a single power supply, and the gate bias is obtained with a resistor voltage-divider network. The circuit in (b) is for a laboratory project aplifier. Both GG and are negative, since the source is at ground. There is no voltage drop across G since there is negligible gate current. G is necessary only to prevent shorting the input signal,. i The bias current I for a given applied G will respond according to (3.8), which is I p ( ) ( λ ) k 1 G tpo p 45
46 Unit 5 Coon-ource Aplifier tage GG Fig. 5.1 Basic PMO coonsource aplifiers. ingle-powersupply aplifier (a) and laboratory aplifier (b) with G ( GG ) and controlled by AQ output channels. Note that either end of the circuit of (a) can be at ground. i G G1 o i G o (a) (b) The two circuits are equivalent, as GG and G of Fig. 5.1.b are the Thévenin equivalent of the bias network of the Fig. 5.1(a). In the project on the aplifier, they are actually a voltage and a resistor. This is not a bias-stable circuit, as a slight change in G or the transistor paraeters can result in a significant change in I. The dual-power-supply circuit of Unit 5.4 is considerably better in this respect. 5. Aplifier oltage Gain This dc (bias) circuit becoes an aplifier now siply by adding a signal source at the gate as in Fig. 5.. This requires a coupling capacitor, as shown here in the coplete circuit, to prevent disturbing the bias upon connecting the input signal to the circuit. In the aplifier of Project 5, the signal will be superiposed on the bias voltage at the node of GG. This can be facilitated with LabIEW and the AQ. A capacitor, as in an actual aplifier, is therefore not required. The requireent for having LabIEW control over both GG and, and the liitation of two output channels, dictates this configuration. In Project 5 we easure the gain as a function of bias current, I. For a PICE coparison, we need an expression for the gain. For the ideal case, which neglects the output conductance, g ds, the output current is related to the input voltage by (4.1), which is I d g gi
Unit 5. Aplifier oltage Gain 47 GG Fig. 5. A signal source is connected to the gate through a coupling capacitor. The capacitor is necessary to isolate the dc circuit fro the signal source. s G C g i o The output signal voltage is, in general, ds (5.1) o I d - i G o Fig. 5.3 ignal-equivalent version of the aplifier stage. c nodes are set to zero volts (circuit reference). The reactance of C is assued to be zero. g g The convention used here for subscript order for signal (linear) variables is coon to the NMO and PMO. This is consistent with the fact that the linear odel does not distinguish between the two types. Thus, for exaple, the dc terinal voltage for a PMO is G, but the signal equivalent is (Fig. 5.3) and the signal input voltage is positive at the input terinal (coon-source, gate input). For the PMO, i is defined as positive out of the drain, but the signal output current is into the drain (as in the NMO). We note that a positive ( sg ) corresponds to a decrease in the total gate source voltage, G which is consistent with a decrease of i and positive I d. v,
48 Unit 5 Coon-ource Aplifier tage Thus, the negative sign in (5.1) is consistent with the flow of current I d up through the resistor (Fig. 5.3) for positive i. The coon-source stage is an o inverting aplifier and has an inherent 180 phase shift. Fro (4.1) and (5.1), the gain is av o (5.) i g where both i and o ds are with respect to ground or the source terinal for the coon-source stage. If the output resistance, 1 /g, cannot be neglected (which is the case for the ds project on PMO aplifiers), the transistor current, g, i is shared between the output resistance and. The portion that flows through is (Fig. 5.4) 1 I g i 1 g ds (5.3) Note again that the signal scheatic transistor represents a current source with value g i, as established in connection with Fig. 4.1. The additional feature of the transistor odel is included with the addition of 1/g. This resistance is ds actually part of the transistor and is between the drain and source of the transistor, but the circuit as given is equivalent, as the source is at ground. ince the output voltage is I, the new gain result is o av g (5.4) 1 d Note that this for evolves fro ideal transistor current, g, flowing through the parallel cobination of the output resistance and. To facilitate an intuitive grasp of the agnitude of the effect of g ds, we use the expression for g ds (4.13) in (5.4), to obtain a v g (5.5) 1 λ p I Note that supply, we choose power λ for our devices will show that I is the voltage drop across. For exaple, for a 10- I 5. A easureent of p
Unit 5. Aplifier oltage Gain 49 λ 1/0, which results in p p I 1 / 4 case is significant. λ. Thus, the effect of g ( I ) for this ds λ p i G g i o 1 / g ds Fig. 5.4 Coon-source aplifier stage signal circuit, with all dc nodes set to zero volts. The transistor odel includes output resistance 1/g ds, which appears directly in parallel with with the source grounded. Finally, we can get an overall current dependence for of g, using (4.5) with k p kp, which results in a v with the eliination a v k pi (5.6) 1 λ pi Using an alternative for for g ( I / effp ), also (4.5), the gain expression is a v I effp 1 (5.7) λ pi where effp I λ I k p (1 p ) k p For siplicity, approxiate fors of (4.5) and (4.13) of g and g ds are used here, which are independent of. For reference, the exact and approxiate fors of (4.5) and (4.13), respectively, are repeated here: g k (1 λ )I k I p p p and
50 Unit 5 Coon-ource Aplifier tage g ds λ p 1 λ I p λ pi The exact equations of g and gds are used in conjunction with the aplifier projects to copare the coputed gain with the easured gain plotted against I. This is done in both LabIEW and Mathcad. Paraeters k p and tpo (to get effp ) will be extracted fro the easured dc data, and λ p will be used as an adjustable paraeter to fit the PICE and easured gain data. 5.3 Linearity of the Gain of the Coon-ource Aplifier The connection between I d and is linear provided that is sall enough, as considered in the following units. Use of the linear relations also assues that the output signal reains in the active region (i.e., neither in the linear region nor near cutoff). This is discussed below. NMO subscripts are used. The results are the sae for the PMO, with a p subscript substituted for n and the subscript order reversed for all bias-voltage variables. 5.3.1 Nonlinearity eferred to the Input The general equation again is (3.8) i k n ( v ) G tno Then using Id i I and v G G, the equation for the increental drain current becoes ( ) I k d n G tno (5.8) which leads to a nonlinear (variable) transconductance, g, given by ( ) Therefore, the condition for linearity is that k I n effn d g g 1± effn (5.9) <<, with eff effn G tno
Unit 5.3 Linearity of the Gain of the Coon -ource Aplifier 51 and using g k n effn. With this condition not satisfied, an output signal is distorted. However, for the purpose of easuring the aplifier gain, our signal volteter will take the average of the positive and negative peaks, which is I davg ( eff ) k n( eff ) k n (5.10) In the parabolic relationship, the squared ters cancel entirely. In general, though, the output signal contains haronic content (distortion) when is too large copared to. effn 5.3. Nonlinearity eferred to the Output The discussion above of liits iposed on assues that the transistor reains in the active ode. To clarify this point, reference is ade to the output characteristics of Fig. 5.5. The graph has plots of the output characteristic for three values of v G in addition to the load line. The characteristic plot in the idrange is for no signal. Operating point variables are.5 and I 40 µ A. With a large, positive, the characteristic oves up to the high-level plot ( i hi ) and the opposite occurs for a large but negative ( i lo ). The highlevel plot is shown for when the transistor is about to ove out of the active region and into the linear region. Attepts to force v to lower values will create considerable distortion in the output signal voltage. The lower curve suggests that the positive output signal is on the verge of being cut off (clipped) for an additional increase in the negative-input signal voltage. According to the discussion above, the negative signal output voltage is liited to ds inus (5.11) effn Technically, effn is fro the high-current signal state, but for siplicity, a reasonable estiate can be ade fro the dc case; that is, effn G tno. The positive signal liit is dsplus I (5.1
5 Unit 5 Coon-ource Aplifier tage v effn i ( µ A) i hi I i lo v () Fig. 5.5 Coon-source aplifier stage output characteristics. Output characteristics are fro top to botto, large high-current signal swing, i hi, dc bias, I, low-current signal swing, i lo. Also shown is the load line. The current voltage circuit solution is always the intersection between a given characteristic and the load line. The actual output-signal liit is dictated by the saller of the two for a syetrical periodic signal such as a sine-wave. In the exaple shown in Fig. 5.5, 0.5,.5, and effn 5. The plus and inus signal-voltage liits are about.5 and.0, respectively. epending on the dc bias, the liit could be dictated by one or the other. In the aplifier projects, the gain will typically be easured over a range of dc bias current for a fixed resistor. This eans that for the low-current end of the scan, the signal will be liited by the agnitude of I and, by design, the plus and inus swin will be ade to be about equal at the highest dc current. istortion associated with the nonlinear I d relation and that due to signal liits at the output ay be taking place siultaneously. This is seen fro the gain expression (5.7) ( g ds 0) a v effp where n a / and where the approxiation is for the case of neglecting the v ds λ factor. Thus, for a given, is ds
Unit 5.4 Current-ource Coon-ource Aplifier: Coon-ource Aplifier with a ource esistor 53 effp (5.13) ds If, for exaple, is pushed to the positive output-signal liit, then ds ds. According to (5.13), effp /, and exceeds the condition for a linear I d relation as given in (5.9), I ± d g g 1 effn 5.4 Current-ource Coon-ource Aplifier: Coon-ource Aplifier with a ource esistor The bias circuit of the current-source bias aplifier, shown in Fig. 5.6, has a dual power supply. One advantage of this is that the input is at zero dc volts such that the signal can be connected directly without interfering with the bias. The dc circuit equation for setting up the bias is I G (5.14) where ( k p k p ) G I /k p tp. This circuit is ore bias stable than the grounded source aplifier, as slight changes in G (due to device paraeter variations or teperature) are usually sall copared to. Note that tp is used in lieu of tpo as B 0. The chip (C4007) used in the projects is a p-well device (as noted in Unit 3), with the NMO transistors in the well. The well is connected to, while the body of the chip is connected, as in Fig. 5.6, to. The pn junction fored by the well and the bulk is thus reverse-biased with a voltage. In the aplifier projects, however, we have the latitude to connect the body and source as there is only one transistor in the circuit and the body can float along with the source. Thus we can assue that. tp tpo As shown in Fig. 5.7, the signal circuit requires the addition of a bypass capacitor, C s. This places the source at signal ground provided that the capacitor is large enough. The criterion
54 Unit 5 Coon-ource Aplifier tage for this is discussed in Unit 6. The voltage-gain equation is the sae as in the aplifier, with the source actually grounded. Fig. 5.6 c circuit of the dual-powersupply coon-source aplifier. The gate is at ground potential, allowing the signal to be connected directly to the gate. G is necessary only to prevent shorting out the input signal. G G Without the bypass capacitor, is in the signal circuit and a fraction of the applied signal voltage at the gate is dropped across the resistor. The signal circuit for this case is shown in Fig. 5.8. The circuit transconductance of the aplifier with was discussed initially in Unit 4. This is reviewed in the following. Fig. 5.7 Aplifier circuit with a bypass capacitor attached between the source and ground to tie the source to signal ground. ignal input is attached directly to the gate. Body and source are connected internally in the project chip for the transistor used in the aplifier. i g G o C s An applied input signal, i g, divides between the gate source terinals and the source resistor according to [(4.6)] I g d
Unit 5.5 esign of a Basic Coon-ource Aplifier 55 Fig. 5.8 ignal circuit for dual-power supply coon-source aplifier. Input signal voltage,, is divided between i, the control voltage, and the source resistor according to the ratio 1 :g. i g G - o When cobing this with I, we obtain [(4.7)] d g I ( ) ( ) d g g 1 g 1 g The circuit transconductance, g G, is then [(4.8)] G Id g 1 g g The gain for this case is thus (neglecting g ds ) av d g g G (5.15) 1 g In one of the aplifier projects,, and the gain without the bypass capacitor is actually less than unity. 5.5 esign of a Basic Coon-ource Aplifier Unlike in the laboratory environent, an actual practical coon-source aplifier would have a single power supply for the base and collector circuit bias. Also, the circuit design requires a tolerance to a wide range of paraeter
56 Unit 5 Coon-ource Aplifier tage variation, including that due to teperature change. In this unit, the design process for a possible coon-source aplifier is discussed. Ephasis is on dc bias stability, that is, on tolerance to device paraeter and circuit coponent variations. The coon-source aplifier to be designed is shown in Fig. 5.9. ource resistor,, is included for bias (and gain) stabilization. The goal is for the circuit to function properly for any NMO transistor, which has device paraeters k n and that fall into a wide range of values, as is norally expected. Tolerance tno to coponent variation, such as resistor values, could also be built into the design. Fig. 5.9 NMO coon-source aplifier with for bias and gain stabilization. Gate bias is provided by a voltage-divider network consisting of G1 and. The body G and source terinals are connected. i G1 C g o C s G Gate voltage G is provided by the voltage divider, consisting of resistors G1 and. ince there is no gate current, the gate bias voltage is [(1.)] G G G G G1 oltage G is thus relatively stable and can be considered constant. Once G has been established, the drain current will be dictated by I G G (5.16) ince the gate source voltage is given by
Unit 5.5 esign of a Basic Coon-ource Aplifier 57 I G tno k n (5.17) the drain current, I, ay be expressed in ters of the device paraeters as I G I k n tno (5.18) This result reveals the dependence of I on the agnitudes of k n and tno. (Again, for siplicity, as in the aplifier projects, we will assue that the body and source are connected such that.) tn tno Bias current I is assued to be a given. The initial design then is conducted for the NMO noinal, average values for k n and tno. Any cobination of G and that satisfies (5.18) will provide the design I. pecific values for G and will be dictated by stability requireents. uppose that k n is expected to fall within k ±δ k and no n tno within tnoo ±δ tno, where k no and tnoo are the noinal values of the original design. Assue that the design bias current associated with k and no tnoo is I o will be. At the extrees for the paraeters, the low and high currents I lo,hi ( ) I ±δ G tnoo tno k δk no n (5.19) esistor, for the given G and design drain current, is G Go (5.0) Io is obtained fro (5.17), using the noinal paraeter values. The low and Go high current liits tend to converge on G / as G becoes large. That is, in the liit, G doinates the voltages in the nuerator of (5.19), thus rendering the expression insensitive to the inor contributions fro changes in k n and. tno An iportant design consideration is drain source voltage,, as this dictates the output signal range. This is calculated fro
58 Unit 5 Coon-ource Aplifier tage ( ) I (5.1) In the design of the aplifier, drain resistor is norally selected for equal positive and negative peak-signal axius. This configuration is illustrated in Fig. 5.10, which shows the output characteristic of the transistor in the circuit. The signal is liited by and effno Go at the high and low ends tno of the voltage range, respectively. Therefore, noinal bias should be set at o I o effno (5.) For siplicity, it is assued that v effn effno.,, and I effno o o are the bias values at the noinal paraeter values. The bias drain voltage is o plus the drop across, that is, (5.3) I o o o Knowing o then provides for the calculation of fro o (5.4) Io where o and I o are for the initial design with k no and tnoo. An optiization design sequence plots the liits for a range of G and for specified δ tno and δ k. An exaple is shown in Fig. 5.11. The plot of n o corresponds to the noinal k no and tnoo. The curve slopes downward as I increases for increasing G at constant noinal bias current, I o. hi is for the cobination of δ tno and δ k, which gives the axiu positive deviation fro n the noinal, and lo is the opposite. The exaple of Fig. 5.11 is for 10 and design bias current of I o 100 µ A and noinal paraeters k 300 µ A /, no 1.5, δ 0.1, and δ k 100 µ A /. Experience with the CMO chip of tnoo tno n our aplifier project (Project 7) indicates that these are representative. Figure 5.1 shows plots of the coputed positive and negative signal-peak liits. ue to the increasing with increasing G, the signal range decreases, as shown by the plots. Thus, the signal-peak liits have a axiu, as is evident in the graph. The design of the aplifier uses G at the axiu of the lower
Unit 5.5 esign of a Basic Coon-ource Aplifier 59 curve. The value of G 5.11. In the exaple, G is consistent with the axiu lo in the plot of Fig. 3. v effn i ( µ A) i i sig I i v () I Fig. 5.10 Output characteristic of the transistor of the aplifier with bias set approxiately according to (5.). The signal is restricted within the range and approxiately v. The characteristic effn curves are for no signal (solid plot) and for the signal at a axiu (dashed plot), as liited by the transistor going into the inactive (linear) region. The load lines are dc (solid line) and signal (ac, dashed line). Once G is deterined, the selection of G1 is ade fro (1.), which is G G G G G1 G1 where G is the parallel cobination G G G1 G G1 G can be selected soewhat arbitrarily but could be dictated by the coupling capacitor, C, requireent. Associated with the coupling capacitor is the 3 - db g frequency (6.), which is
60 Unit 5 Coon-ource Aplifier tage f3db π 1 C G g hi o lo Fig. 5.11 Coputed high and low range of as a function of gate-bias voltage G. The coputation is with k 300 µ A/, no tnoo 1.5, δ 0.1, tno and δ k 100 µ A/. n G G is then calculated fro G G1 G G1 G The gain equations for the circuit of Fig. 5.9, with and without a bypass capacitor, are (5.) and (5.15), respectively. These are av g and a v 1 g g In the design procedure outlined in this unit, ephasis is on stability and the gain falls out. This would typically be the case for this type of aplifier. We note that due to the characteristically sall g of MOFETs, the voltage gain is
Unit 5.5 esign of a Basic Coon-ource Aplifier 61 relatively sall. Gain can be iproved considerably through the use a currentsource load, as in the aplifier of Unit 10. dplus dplus dinus din us Fig. 5.1 Coputed axius for negative and positive output voltage signal peaks as a function of G : dplus, positive axiu; dinus, negative axiu. G
6 Unit 5 Coon-ource Aplifier tage 5.6 uary of Equations Coon-source aplifier-stage voltage gain. av g a v g g 1 Coon-source aplifier gain including g 1 λp I output resistance, PMO. (ae for NMO with λ n.) Nonlinear transconductance for large input ± signals. (ae for PMO with effp.) effn Negative output signal liit, NMO. ds inus ds inus effn Negative output signal liit, PMO. effp dsplus I Positive output signal liit, NMO. dsplus I a v G 1 Positive output signal liit, PMO. 1 g g g g 5.7 Exercises and Projects oltage gain of coon-source stage with source resistor. Circuit transresistance of coon-source stage with source resistor. Project Mathcad Files Laboratory Project 5 Exercise05.cd - Project05.cd PMO Coon-ource Aplifier P5. PMO Coon-ource Aplifier C etup P5.3 Aplifier Gain at One Bias Current P5.4 Aplifier Gain versus Bias Current