Features Active pull-up on data input pins Low power version (6V8L) 55 ma max. commercial (0, 5, 25 ns) 65 ma max. industrial (0, 5, 25 ns) 65 ma military (5 and 25 ns) Standard version has low power 90 ma max. commercial (0, 5, 25 ns) 5 ma max. commercial (7 ns) 30 ma max. military/industrial (0, 5, 25 ns) CMOS Flash technology for electrical erasability and reprogrammability PCI-compliant User-programmable macrocell Output polarity control Individually selectable for registered or combinatorial operation Logic Block Diagram (PDIP/CDIP) Flash-Erasable Reprogrammable CMOS PAL Device Up to 6 input terms and eight outputs 7.5 ns com l version 5 ns t CO 5 ns t S 7.5 ns t PD 25-MHz state machine 0 ns military/industrial versions 7 ns t CO 0 ns t S 0 ns t PD 62-MHz state machine High reliability Proven Flash technology 00% programming and functional testing Functional Description The Cypress is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. GND I 8 I 7 I 6 I 5 I 4 I 3 I 2 I CLK/I 0 0 9 8 7 6 5 4 3 2 PROGRAMMABLE AND ARRAY (64 x 32) 8 8 8 8 8 8 8 8 Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Pin Configurations 2 3 4 5 6 7 8 9 20 OE/I 9 I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 V CC CLK/I 0 I I 2 I 3 I 4 I 5 I 6 DIP Top View 2 3 4 5 6 7 20 9 8 7 V CC I/O 7 I/O 6 I/O 5 6 I/O 4 5 I/O 3 4 I/O 2 I7 8 3 I/O I 8 GND 9 0 2 I/O 0 OE/I 9 I 3 I 4 I 5 I 6 I 7 4 5 6 7 8 PLCC/LCC Top View I I 2 0 CLK/I V CC I/O 7 3 2 209 8 7 6 5 4 9 023 I 8 GND OE/I I/O I/O 9 0 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 Cypress Semiconductor Corporation 390 North First Street San Jose, CA 9534 408-943-2600 Document #: 38-03025 Rev. *A Revised April 22, 2004
Selection Guide t PD ns t S ns t CO ns I CC ma Generic Part Number Com l/ind Mil Com l/ind Mil Com l/ind Mil Com l Mil/Ind -5 5 3 4 5-7 7.5 7 5 5-0 0 0 0 0 7 0 90 30-5 5 5 2 2 0 0 90 30-25 25 25 5 20 2 2 90 30 L-5 5 5 2 2 0 2 55 65 L-25 25 25 5 20 2 20 55 65 Shaded areas contain preliminary information. Functional Description The is executed in a 20-pin 300-mil molded DIP, a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. The device provides up to 6 inputs and 8 outputs. The can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 20-pin PLDs such as 6L8, 6R8, 6R6, and 6R4. The features 8 product terms per output and 32 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. There are a total of 8 architecture bits in the macrocell; two are global bits that apply to all macrocells and 6 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the Configuration Table macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. Power-Up Reset All registers in the power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-low outputs. Electronic Signature An electronic signature word is provided in the that consists of 64 bits of programmable memory that can contain user-defined data. Security Bit A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. CG 0 CG CL0 x Cell Configuration Devices Emulated 0 0 Registered Output Registered Med PALs 0 Combinatorial I/O Registered Med PALs 0 0 Combinatorial Output Small PALs 0 Input Small PALs Combinatorial I/O 6L8 only Document #: 38-03025 Rev. *A Page 2 of 3
Macrocell OE V CC 0 X 0 0 0 0 0 To Adjacent Macrocell CG CL0 x 0 X I/O x D Q 0 V CC CLK Q CL x CG for pin 3 to 8 CG 0 for pin 2 and 9 0 0 X CL0 x From Adjacent Pin Document #: 38-03025 Rev. *A Page 3 of 3
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature... 65 C to +50 C Ambient Temperature with Power Applied... 55 C to +25 C Supply Voltage to Ground Potential (Pin 24 to Pin 2)... 0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State... 0.5V to +7.0V DC Input Voltage... 0.5V to +7.0V Output Current into Outputs (LOW)... 24 ma DC Programming Voltage... 2.5V Latch-Up Current... > 200 ma Operating Range Range Ambient Temperature V CC Commercial 0 C to +75 C 5V ±5% Military [] 55 C to +25 C 5V ±0% Industrial 40 C to +85 C 5V ±0% Electrical Characteristics Over the Operating Range [2] I = 3.2 ma Com l 2.4 V I = 24 ma Com l 0.5 V Parameter Description Test Conditions Min. Max. Unit V OH Output HIGH Voltage V CC = Min., V IN = V IH or V IL OH I OH = 2 ma Mil/Ind V OL Output LOW Voltage V CC = Min., V IN = V IH or V IL OL I OL = 2 ma Mil/Ind V IH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs [3] 2.0 V V [4] IL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs [3] 0.5 0.8 V I IH Input or I/O HIGH Leakage 3.5V < V IN < V CC 0 µa Current [5] I IL Input or I/O LOW Leakage 0V < V IN < V IN (Max.) 00 µa Current I SC Output Short Circuit Current V CC = Max., V OUT = 0.5V [6, 7] 30 50 ma I CC Operating Power Supply V CC = Max., 5, 7 ns Com l 5 ma Current V IL = 0V, V IH = 3V, 0, 5, 25 ns 90 ma Output Open, f = 5 MHz 5L, 25L ns 55 ma (counter) 0, 5, 25 ns Mil/Ind 30 ma 5L, 25L ns Mil. 65 ma 5L, 25L ns Ind. 65 ma Capacitance [7] Parameter Description Test Conditions Typ. Unit C IN Input Capacitance V IN = 2.0V @ f = MHz 5 pf C OUT Output Capacitance V OUT = 2.0V @ f = MHz 5 pf Endurance Characteristics [7] Parameter Description Test Conditions Min. Max. Unit N Minimum Reprogramming Cycles Normal Programming Conditions 00 Cycles Notes:. T A is the instant on case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. V IL (Min.) is equal to 3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03025 Rev. *A Page 4 of 3
AC Test Loads and Waveforms 3.0V GND <2ns 0% ALL INPUT PULSES 90% 90% 0% <2ns 5V S OUTPUT R R2 C L TEST POINT Specification S C L R R 2 R R 2 Measured Output Value Commercial Military t PD, t CO Closed 50 pf 200Ω 390Ω 390Ω 750Ω.5V t PZX, t EA Z H: Open.5V Z L: Closed t PXZ, t ER H Z: Open L Z: Closed 5 pf H Z: V OH 0.5V L Z: V OL + 0.5V Commercial and Industrial Switching Characteristics [2] 6V8-5 6V8-7 6V8-0 6V8-5 6V8-25 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit t PD Input to Output 5 3 7.5 3 0 3 5 3 25 ns Propagation Delay [8, 9] t PZX OE to Output Enable 6 6 0 5 20 ns t PXZ OE to Output Disable 5 6 0 5 20 ns t EA Input to Output 6 9 0 5 25 ns Enable Delay [7] t ER Input to Output 5 9 0 5 25 ns Disable Delay [7, 0] t CO Clock to Output Delay [8, 9] 4 2 5 2 7 2 0 2 2 ns t S Input or Feedback 3 5 7.5 2 5 ns Set-up Time t H Input Hold Time 0 0 0 0 0 ns t P External Clock Period (t CO + t S ) 7 0 4.5 22 27 ns Shaded areas contain preliminary information. Notes: 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This specification is guaranteed for all device outputs changing state in a given access cycle. 0. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below V OH min. or a previous LOW level has risen to 0.5 volts above V OL max.. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 2. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 3. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 4. This parameter is calculated from the clock period at f MAX internal (/f MAX3 ) as measured (see Note 7 above) minus t S. Document #: 38-03025 Rev. *A Page 5 of 3
Military Switching Characteristics [7] 6V8-0 6V8-5 6V8-25 USE ULTRA37000 FOR Commercial and Industrial Switching Characteristics (continued) [2] Parameter Description 6V8-5 6V8-7 6V8-0 6V8-5 6V8-25 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. t WH Clock Width HIGH [7] 3 4 6 8 2 ns t WL Clock Width LOW [7] 3 4 6 8 2 ns f MAX External Maximum 43 00 69 45.5 37 MHz Frequency (/(t CO + t S )) [7, ] f MAX2 Data Path Maximum 66 25 83 62.5 4.6 MHz Frequency (/(t WH + t WL )) [7, 2] f MAX3 Internal Feedback Maximum Frequency (/(t [7, 3] CF + t S )) 66 25 74 50 40 MHz t CF Register Clock to 3 3 6 8 0 ns Feedback Input [7, 4] t PR Power-Up Reset Time [7] µs Unit Parameter Description Min. Max. Min. Max. Min. Max. Unit t PD Input to Output Propagation Delay [8, 9] 3 0 3 5 3 25 ns t PZX OE to Output Enable 0 5 20 ns t PXZ OE to Output Disable 0 5 20 ns t EA Input to Output Enable Delay [7] 0 5 25 ns t ER Input to Output Disable Delay [7, 0] 0 5 25 ns t CO Clock to Output Delay [8, 9] 2 7 2 0 2 2 ns t S Input or Feedback Set-up Time 0 2 5 ns t H Input Hold Time.5.5.5 ns t P External Clock Period (t CO + t S ) 7 22 27 ns t WH Clock Width HIGH [7] 6 8 2 ns t WL Clock Width LOW [7] 6 8 2 ns f MAX External Maximum Frequency 58 45.5 37 MHz (/(t CO + t S ) [7, ] f MAX2 Data Path Maximum Frequency 83 62.5 4.6 MHz (/(t WH + t WL )) [7, 2] f MAX3 Internal Feedback Maximum 62.5 50 40 MHz Frequency (/(t CF + t S )) [7, 3] t CF Register Clock to 6 8 0 ns Feedback Input [7, 4] t PR Power-Up Reset Time [7] µs Document #: 38-03025 Rev. *A Page 6 of 3
Switching Waveform INPUTS, I/O, REGISTERED FEEDBACK t t t S t WH WL H CP REGISTERED OUTPUTS t CO t P t PXZ,t [0] ER t EA,t [0] PZX COMBINATORIAL OUTPUTS t PD t PXZ,t [0] ER t EA,t [0] PZX Power-Up Reset Waveform POWER SUPPLY VOLTAGE 0% 90% t PR V CC REGISTERED ACTIVE LOW OUTPUTS t S CLOCK t PR MAX = µs t WL Document #: 38-03025 Rev. *A Page 7 of 3
Functional Logic Diagram for PIN NUMBERS PRODUCTLINE FIRSTCELL NUMBERS 0 3 4 7 8 2 5 6 9 20 23 24 27 28 3 INPUT LINE NUMBERS PIN NUMBERS V CC 20 2 00 32 64 96 28 60 92 224 MC7 CL=2048 CL0=220 PTD=228-235 9 3 256 288 320 352 384 46 448 480 MC6 CL=2049 CL0=22 PTD=236-243 8 4 52 544 576 608 640 672 704 736 MC5 CL=2050 CL0=222 PTD=244-25 7 5 768 800 832 864 896 928 960 992 MC4 CL=205 CL0=223 PTD=252-259 6 6 024 056 088 20 52 84 26 248 MC3 CL=2052 CL0=224 PTD=260-267 5 7 280 32 344 376 408 472 440 504 MC2 CL=2053 CL0=225 PTD=268-275 4 8 536 568 600 632 664 728 696 760 MC CL=2054 CL0=226 PTD=276-283 3 9 792 824 856 888 920 984 952 206 MC0 CL=2055 CL0=227 PTD=284-29 2 0 0 3 4 7 8 2 5 6 9 20 23 24 27 28 3 USER ELECTRONIC SIGNATURE ROW 2056 2064 2072 2080 2088 2096 204 22 29 GLOBALARCH BITS BYTE0 BYTE BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 CG 0 =292 CG =293 MSB LSB MSB LSB Document #: 38-03025 Rev. *A Page 8 of 3
Ordering Information I CC t PD t S t CO Package Operating (ma) (ns) (ns) (ns) Ordering Code Name Package Type Range 5 5 3 4-5JC J6 20-Lead Plastic Leaded Chip Carrier Commercial 5 7.5 5 5-7JC J6 20-Lead Plastic Leaded Chip Carrier Commercial -7PC P5 20-Lead (300-Mil) Molded DIP 90 0 7.5 7-0JC J6 20-Lead Plastic Leaded Chip Carrier -0PC P5 20-Lead (300-Mil) Molded DIP 30 0 7.5 7-0JI J6 20-Lead Plastic Leaded Chip Carrier Industrial -0PI P5 20-Lead (300-Mil) Molded DIP 30 0 0 7-0DMB D6 20-Lead (300-Mil) CerDIP Military -0LMB L6 20-Pin Square Leadless Chip Carrier 90 5 2 0-5JC J6 20-Lead Plastic Leaded Chip Carrier Commercial -5PC P5 20-Lead (300-Mil) Molded DIP 30 5 2 0-5PI P5 20-Lead(300Mil) Molded DIP Industrial -5DMB D6 20-Lead (300-Mil) CerDIP Military -5LMB L6 20-Pin Square Leadless Chip Carrier 90 25 5 2-25JC J6 20-Lead Plastic Leaded Chip Carrier Commercial -25PC P5 20-Lead (300-Mil) Molded DIP 30 25 5 2-25JI J6 20-Lead Plastic Leaded Chip Carrier Industrial -25DMB D6 20-Lead (300-Mil) CerDIP Military -25LMB L6 20-Pin Square Leadless Chip Carrier 55 0 7.5 7 L-0JC J6 20-Lead Plastic Leaded Chip Carrier Commercial L-0PC P5 20-Lead (300-Mil) Molded DIP 65 0 0 7 L-0JI J6 20-Lead Plastic Leaded Chip Carrier Industrial L-0PI P5 20-Lead (300-Mil) Molded DIP 55 5 2 0 L-5JC J6 20-Lead Plastic Leaded Chip Carrier Commercial L-5PC P5 20-Lead (300-Mil) Molded DIP 65 5 2 0 L-5DMB D6 20-Lead (300-Mil) CerDIP Military L-5LMB L6 20-Pin Square Leadless Chip Carrier 55 25 5 2 L-25JC J6 20-Lead Plastic Leaded Chip Carrier Commercial L-25PC P5 20-Lead (300-Mil) Molded DIP 65 25 5 2 L-25DMB D6 20-Lead (300-Mil) CerDIP Military L-25LMB L6 20-Pin Square Leadless Chip Carrier Shaded areas contain preliminary information. Document #: 38-03025 Rev. *A Page 9 of 3
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter V OH, 2, 3 V OL, 2, 3 V IH, 2, 3 V IL, 2, 3 I IX, 2, 3 I OZ, 2, 3 I CC, 2, 3 Package Diagrams Subgroups Switching Characteristics Parameter Subgroups t PD 9, 0, t CO 9, 0, t S 9, 0, t H 9, 0, 20-Lead (300-Mil) CerDIP D6 MIL-STD-835 D-8 Config. A 5-80029-** Document #: 38-03025 Rev. *A Page 0 of 3
Package Diagrams (continued) 20-Lead Plastic Leaded Chip Carrier J6 5-85000-*A 20-Square Leadless Chip Carrier L6 5-80049-** Document #: 38-03025 Rev. *A Page of 3
Package Diagrams (continued) 20-Lead (300-Mil) Molded DIP P5 5-850-*A Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03025 Rev. *A Page 2 of 3 Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Document History Page Document Title: Flash Erasable Reprogrammable CMOS PAL Device Document Number: 38-03025 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 06370 07//0 SZV Change from Spec Number: 38-00364 to 38-03025 *A 23375 See ECN FSG Added note to title page: Use Ultra37000 For All New Designs Document #: 38-03025 Rev. *A Page 3 of 3