12-bit Digital-Analog Converter ECE262 Analog Circuit Design Team Member Jae Shik Lim Chao Chen Lingzhao Xie
Agenda Abstract Background Block Diagram Module Level Design System Level Design Design Review 2
Abstract Design of a 12-bit Digital-Analog Converter with mixed-signal design The lower 8 bits of digital-analog conversion are implemented by R-2R Ladder while the upper 4 bits are implemented by Binary-to-Thermometer Decoder Carefully design the Op-Amp to optimize the performance of the DAC 3
Background Binary-to-Thermometer Decoder R-2R ladder requires significantly high precision resistors and is usually limited to a max of 8-bit resolution. The implementation of Thermometer Decoder allows for a 12-bit resolution while only needing the accuracy of a 8-bit DAC N inputs thermometer decoder has 2 n 1 outputs. Each output corresponds to a base 10 value of the possible binary inputs. 4
Background Example of 3bits Binary-to-Thermometer Decoder Three bits input and corresponding seven outputs 5
Background R-2R Ladder with Thermometer Decoder 4 bits Thermometer Decoder R Array R-2R Ladder 6
Block Diagram MSB 4-bit Thermometer Decoder 15-bit R Array Analog Opamp Low Pass Filter Analog output 8-bit LSB + R-2R Ladder 7
Module Design 8
R-2R Ladder and R Array Module Thermometer Decoder R Array Opamp Low Pass Filter R-2R Ladder 9
R-2R Ladder (8bits) Schematic 10
R-2R Ladder (8bits) Simulation using Hspice (Inputs) 11
R-2R Ladder (8bits) Simulation using Hspice (Output) 12
R-2R Ladder and R Array Module Layout (Both LVS and DRC clean) 13
4bits Thermometer Decoder Module Thermometer Decoder R Array Opamp Low Pass Filter R-2R Ladder 14
4bits Thermometer Decoder Module Schematic 15 bits output to R Array 15
4bits Thermometer Decoder Module Schematic Thermometer Decoder R Array R-2R Ladder 16
4bits Thermometer Decoder Module Simulation using Eldo (12bits input) Inputs for the thermometer decoder and R-2R array 17
4bits Thermometer Decoder Module Simulation using Eldo (output) Output of the thermometer decoder and R-2R array 18
4bits Thermometer Decoder Module Simulation using Eldo (magnified output) 3.29422 3.29290 Resolution=1.3mV 19
4bits Thermometer Decoder Module Layout for MOS Gates 4 input NAND 4 input NOR 3 input NAND 3 input NOR 20
4bits Thermometer Decoder Module Layout for MOS Gates 2 input NAND 2 input NOR 21
4bits Thermometer Decoder Module Layout (Both DRC and LVS Clean) 22
OP Amplifier Module Thermometer Decoder R Array Opamp Low Pass Filter R-2R Ladder 23
OP Amplifier Module Schematic 24
OP Amplifier Module Specification Linear through the whole range Input range: 0.575V ~ 4.807V DC Gain: 72.775 db Phase Margin: 81.865 degrees Unity Gain Bandwidth: 28 MHz Slew rate: 8.4V/us 25
OP Amplifier Module Simulation using Eldo OPAMP Output R, R-2R Output 26
OP Amplifier Module Simulation using Eldo 1.3mV 27
OP Amplifier Module Layout (Both DRC and LVS Clean) 28
OP Amplifier Module Layout (General View) 29
OP Amplifier Module Layout (Details) Tail bias Out bias 30
OP Amplifier Module Layout (Details) P Load P Out 31
OP Amplifier Module Layout (Details) Common Centroid Differential Pair 32
Low Pass Filter Module Thermometer Decoder R Array Opamp Low Pass Filter R-2R Ladder 33
Active Low Pass Filter Schematic Second-order unity-gain Tschebyscheff LPF 34
Active Low Pass Filter Simulation - Hspice Cut off frequency: 27.24MHz 35
Active Low Pass Filter Simulation - Hspice Roll-off of 2 nd order LPF: 39.6712 db/decade 36
Active Low Pass Filter Layout OPAmp 5k Ω 2ea 22pF 0.3pF 37
System Design 38
12-bit Digital-Analog Converter Top Level Schematic Analog VDD Thermometer Decoder + R Array Analog GND Source Follower Active Filter Dummy R and C 39
12-bit Digital-Analog Converter Top level simulation using Eldo R, R-2R Output OPAMP Output LPF Output 40
12-bit Digital-Analog Converter Layout (Both DRC and LVS Clean) 41
12-bit Digital-Analog Converter All module layout R Array (Analog) Thermometer Decoder (Digital) OP Amp & LPF (Analog) 42
12-bit Digital-Analog Converter Layout Guard Rings Digital Logic N well, N+ (GND) P+ (GND) N well, N+ (A Vdd) P+ (A Gnd) Analog Circuit 43
12-bit Digital-Analog Converter Simulation using Eldo (Max. at 14MHz) R, R-2R Output OPAMP Output Stable state exist, operate well at 14MHz 44
Design Review Specification Input bits: 12-bit Input voltage: 5V Output range: 0.58V ~ 4.80V Resolution: 1.3mV Bandwidth: 14MHz 45
Design Review Component used R and R-2R Array 9 resistors with resistance 2R (=2*20 kω) 22 resistors with resistance R (=20 kω) Thermometer Decoder 2 Input NAND: 8 ea 3 Input NAND: 3 ea 4 Input NAND: 1 ea 2 Input NOR: 8 ea 3 Input NOR: 3 ea 4 Input NOR: 1 ea Inverter: 15 ea OP-AMP Nmos: 5, Pmos: 4, C: 5pF*1 2 nd order Low Pass Filter OP-AMP Capacitor: 0.3 pf, 22pF Resistor: 5 kω * 2 46
Design Review Power consumption & Area used Total power consumption (from Eldo) P_system=1.5647mW Total Area: 1.4453 mm 2 1077um * 1342 um = 1.4453 mm 2 47
Design Review Output calibration In order to improve the non linearity of analog output, we have calibrated the resistor values connected to output of the thermometer decoder The waveform on the next slide shows that the output of resistor array has almost linear output 48
Design Review Output calibration simulation (Eldo) 49