ECP Embedded Component Packaging Technology A.Kriechbaum, H.Stahr, M.Biribauer, N.Haslebner, M.Morianz AT&S Austria Technologie und Systemtechnik AG Abstract The packaging market has undergone tremendous change in the last years, with several different technologies created to fulfill the increasing demands of the industry. Embedded component technology aims to drive the packaging possibilities for segments demanding the highest levels of miniaturization and integration, combined with performance improvement and reliability needs. Driven by these new industrial demands, embedding of discrete devices into printed circuit boards (PCBs) has received a lot of attention lately for all kinds of applications, ranging from traditional embedding in mobile phone engine boards to packaging solutions for RFID chips. Using embedding technology as a laminate-based packaging solution is the next logical step providing a cost-effective miniaturization opportunity whilst maintaining the flexibility and productivity of PCB-type production processes. The Design Ecosystem has become of crucial importance and Engineering design tools are now being released by the major Engineering Design Automation (EDA) providers. More work is also being carried out regarding test strategy and technology and the commercial window of opportunity to bring products to Market in series production quantities is already open. This presentation outlines AT&S s versatile ECP technology, designed to serve a wide variety of applications. This paper gives an overview of the process steps and potential applications highlighting the capabilities of laminate based technologies, e.g. applications such as sensor packages, embedded passive devices, power modules. Furthermore results of the European Union FP7 project HERMES (High density integration by Embedding chips for reduced size Modules and Electronic Systems) [1] are presented. In the HERMES project, the industrialization of embedding technologies is the key target, in addition to development targets, e.g. ultrafine line technology with 25µm line width and space for complex applications. Key words: Embedding technology, Sensor packages, Power modules, Component, Packaging Introduction Development trends in the handheld electronics market, are delivering dramatically improved device performance and better human interfaces. Product design together with demand for Internet services like HD video streaming and social networks are demanding miniaturization and circuit integration. Smartphones are riding at the forefront of consumer-device technology with significant development potential ahead. In terms of substrate technology, today s smartphone relies on a state-of-the-art anylayer high density interconnect (HDI) printed circuit board, but for the next generation new technologies are needed to achieve higher interconnection densities. Embedded component technology has the potential to play a crucial role, with the possibility to build a variety of very dense SiP (System in Package) modules or SiB (System in Board) utilizing the technology. The offered benefits in terms of miniaturization, reliability [2], electrical and thermal performance, mechanical stability and 3D interconnect capability makes an embedded component concept extremely attractive for a wide range of applications. Table 1 shows some of the application areas of ECP Technology.
Table 1: Application areas of ECP Technology Mobile Devices Automotive Semicon Industrial Medical SIP Modules Converter Modules GPS Modules Sensor Modules DCB replacement Control Units Power Modules Sensor Modules DCDC Converter Industrial Sensorics Battery Management Unit Power Modules Sensor Modules Hearing Aid ECP TECHNOLOGY ECP is a laminate-based chip embedding technology leveraging the core principles of PCB manufacturing. It is a combination of state of the art HDI micro via technology, ultra-fine line technology based on a modified semiadditive patterning process and a component assembly concept adapted for embedding of discrete passive components and modified active components. ECP utilises a chip first method the chip is embedded first in a PCB creating an embedded core. This embedded core can be built in to a multilayer PCB or HDI build up layers are used to provide enhanced routing density. The embedded core itself is already a package for the silicon chip. This option is used today for the first embedded applications. The principle process flow of ECP is shown in figure 1. The process starts with laser marking to define registration marks for mechanical process steps. On the copper foil an adhesive material is printed and in the next step the discrete components are placed in the adhesive. This adhesive is cured to ensure a solid bonding to the copper foil, so that no movement of the component can occur in the next process steps. In the lamination (bonding) process, the copper foil with the mounted components, FR-4 prepregs with openings in the component area, a prepreg without openings and a further copper foil are registered together. This package is laminated in a multilayer press to create the embedded core. Drilling of laser via to the copper pads of the components and drilling of through holes in the ECP core are the next process steps (very similar to HDI technology). Following via formation is hole cleaning and electro-less copper plating. After electro-less copper plating is the modified semi-additive process: A high resolution photoresist is laminated on the ultra-thin copper foil followed by the imaging process of the resist. The resist is developed and in the non-covered areas of the resist the copper pattern is built up by galvanic plating. The remaining photo resist is then stripped away and the ultra-thin copper foil that is exposed after the resist stripping is removed by flash etching.
Figure1: process flow for an ECP core The processing of the ECP core ends with an automatic optical inspection to detect failures and deviation of the copper pattern. More complex modules can be built by adding buildup layers to the ECP core. This is performed by multiple laminations of thin FR-4 prepregs, laser drilling and copper filling of the micro via to enable via stacking. Via stacking is a key requirement for realizing complex packages where routing demands up to five conductive traces per component pitch. Galvanic via-filling in combination with ultra-fine line technology is challenging and requires new plating concepts and plating equipment. High levels of process control are needed to achieve and maintain high manufacturing yields (>99%). Cleanliness of the production environment, product handling and ESD protection are also key influencing factors on yield. At the process level, adhesive printing, embedded component assembly and fine line structuring need in addition to be placed under strict process monitoring. These critical process steps are described more in detail in the following section. Adhesive printing The embedding process starts on a special copper foil which was developed in the frame of the Hermes project. The foil is a 2µm copper deposit, on a copper carrier with very low treatment roughness as shown in figure 2 [3]
Figure 2: 2 µm copper foil on 70 µm carrier This copper foil combines good foil handling during the embedding process and a protection of the sensitive surface of the 2 µm copper foil. Low copper treatment of Rz = 1,8 µm and a thin resin layer on top guarantee high copper bonding force even to high Tg materials. On the copper foil, pads of non-conductive adhesive are screen printed. The components are then assembled over the adhesive pads with the active die side contacting the polymer. In a face-down process flow, the microvia connections to the die are drilled through the adhesive, therefore thickness and hence the volume of the adhesive material under the embedded component has to be tightly controlled. To achieve consistent and stable adhesive deposits, the shape and the volume of the adhesive pad is systematically checked before component placement and assembly (see figure 3). This is carried out with 3D laser scanning equipment, which is a high resolution non-contact tool enabling fast and accurate volume measurements. Figure 3: Shape of adhesive pad and 3D-scanning measurement Embedded component assembly Active and passive component placement is achieved with latest generation Pick & Place machines capable of handling devices from tape and reels or trays. To meet the demanding accuracy requirements, several strategies may be used. The achievable accuracy is first influenced by the placement tool itself. For example, using a twin head system offers better performances compared to a 20 nozzle head, but at the detriment of speed. Figure 4 shows these 2 systems. Actual measurements have shown that placement performance significantly exceeds equipment supplier statements (see table 2). Table 2: Placement accuracy 20 Nozzle head Twin head Max. speed 20000 comp/h 3700 comp/h Accuracy specified +/- 55 µm, +/- 0,7 +/- 30 µm, +/- 0,07 Accuracy measured +/- 20 µm, +/- 0,035 +/- 11 µm, +/- 0,025
Figure 4: Placement tool for the 20 nozzle head (left) and the twin head (right). Placement accuracy is also impacted by the component recognition system. Enhanced accuracy can be obtained when a chip pad design recognition system is used instead of edge recognition which is affected by chipping or component dimensional tolerances. The pad recognition system relies on a high resolution camera (~10 µm per pixel) capable of detecting the individual pads of a chip to calculate the X, Y and θ values for placement. Fine Line Structuring After the lamination process, the embedded core is finished. The core is then processed through laser drilling for via formation and these holes are cleaned and plated with electro-less copper. Then the sequence for the ultrafine line semi-additive process starts. Preceded by hot roll lamination of latest generation dry film photoresist, digital imaging of the photo resist is critical process for 25µm technology and below. The LDI (Laser Direct Imaging) system used is capable to resolve features down to 10 µm line width. This machine addresses 25000 DPI (or 1 µm data resolution) with the capability to adjust the image to registration marks with a maximum failure of 18 µm. The capability to adjust the image on the fly is a very important feature to compensate dimensional instability of the PCB materials, and allow high speed processing on large production formats. After development of the photo resist with an alkaline solution, the boards are plated in unique plating equipment. The single board processor (SBP) processes every panel in a single panel plating bath. This enables full process control where all important plating bath parameters are controlled online and the process data are stored with the identification number of the panel. Best plating uniformity has highest priority therefore the single board processor has a cathode frame that contacts the panel on all edges. Segmented, individually adjustable anodes ensure supreme plating uniformity. In addition a new flood delivery system enables low plating tolerances even with filled via and ultra-fine line technology. Figure 5 shows a top view in the plating cell. In the middle parts of the cathode frames are visible
Figure 5: Plating cell of an industrial single board processor The single board processor is designed to fulfill best in class plating requirements. It was tested with patterned design down to 9 µm line and space. Figure 6 shows 25µm line/space structure manufactured by SBP Figure 6: 25µm line/space structures APPLICATION EXAMPLES Hall Effect Sensor Sensor embedding is an area where ECP makes sense. In Figure 7 a Hall effect sensor, embedded in double sided ECP package can be seen. It is much closer to the surface of the package than existing packages which connect the chip with wire bonds.
Figure 7: Embedded HALL sensor chip The sensor chip has on top of the sensor a redistribution layer which provides interconnection pads to the PCB micro via. With the reduction of the distance between the sensor and the magnetic actuator the sensitivity could be increased by factor 10. Motor Management Module This proof of concept demonstrator shows a motor management module with a size of 13 x 13 mm with an embedded processor die with a size of 8,5 x 8,5 mm. on top of the ECP package the memory and other active and passive components are mounted. Figure 8 shows some details of this module. Figure 8: Motor management module The ECP module is a 6 layer board construction with the ECP core and two buildup layers, stacked via interconnection and 25µm technology in all layers as shown in the top picture of figure 8 are needed. Up to 4 lines per channel are routed though via pads of the 350 µm pitch embedded component. The picture below shows more details of the cross section. The processor has on the top side a redistribution layer, and it is connected with copper filled via to the outer layer of the ECP core.
Power module application This application is used as motor control unit for variable speed drives in industrial application such as washing machines and air conditioners. The power module application combines complex redistribution for power and logic functions, high performance power interconnects and challenging thermal management. The power devices are embedded into the PCB and the application specific logic devices and passives are placed on top of the PCB. This concept provides high flexibility for the logic parts combined with efficient design for the power devices embedded in the PCB and isolated from the heat sink. Figure 9 shows the top view of the power module with assembled logic devices and passives. The cross section in Figure 9 shows embedded power devices. The dies are connected from both sides and have a thickness of 70µm. 1000µm Figure 9: Top view and cross section of the power module Conclusions The production capabilities needed for a chip embedding production line are definitely above a PCB HDI production line. AT&S has installed a dedicated ECP production facility for high volume production using new machine concepts for processing and handling high value products. Discrete component assemblies of passive components and silicon dies, digital imaging, a modified semi-additive process 25 µm line/space capable are the highlights of the ECP production line. High production yields and full traceability down to the wafer is realized to fulfill the requirements for the growing chip embedding business. Acknowledgements The authors would like to express their thanks to the European Commission for their funding of the HERMES project (FP7-ICT-224611). References [1] HERMES Website www.hermes-ect.net [2] C. Ryder et al., " Embedded Component: A Comparative Analysis of Reliability, Proceedings of IPC APEX Conference, Las Vegas, USA, April 2011. [3]: Circuit foil data sheet of DTH-TZA-PA