MOS Amplifier Basics

ECE C Laboratory Manual MOS Aplifier Basics Overview This lab will explore the esign an operation of basic single-transistor MOS aplifiers at i-ban. We will explore the coon-source an coon-gate configurations, as well as a CS aplifier with an active loa an biasing. Table of Contents Pre-lab Preparation Before Coing to the Lab Parts List Backgroun Inforation 3 Sall-Signal Aplifier Design an Biasing 3 MOSFET Design Paraeters an Subthreshol Currents 5 Estiating Key Device Paraeters 7 In-Lab Proceure 8.1 Coon-Source Aplifier 8 Coon-Source, no Source Resistor 8 Linearity an Wavefor Distortion 8 Effect of Source an Loa Ipeances 9 Coon-Source with Source Resistor 9. Coon-Gate Aplifier 10.3 Aplifiers with Active Loaing 11 Feeback-Bias Aplifier 11 CMOS Active-Loa CS Aplifier 1 1

MOS Aplifier Basics Pre-lab Preparation Before Coing to the Lab Rea through the lab experient to failiarize yourself with the coponents an assebly sequence. Before coing to the lab, each group shoul obtain a parts kit fro the ECE Shop. Parts List The ECE lab is stocke with resistors so o not be alare if you kits oes not inclue the resistors liste below. Soe of these parts ay also have been provie in an earlier kit. Laboratory # MOS Aplifiers Qty Description CD4007 CMOS pair/inverter 4 N7000 NMOS 4 1uF capacitor (electrolytic, 5V, raial) 8 10uF capacitor (electrolytic, 5V, raial) 4 100uF capacitor (electrolytic, 5V, raial) 4 100-Oh 1/4 Watt resistor 4 0-Oh 1/4 Watt resistor 1 470-Oh 1/4 Watt resistor 4 10-KOh 1/4 Watt resistor 1 33-KOh 1/4 Watt resistor 47-KOh 1/4 Watt resistor 1 68-KOh 1/4 Watt resistor 4 100-KOh 1/4 Watt resistor 1 1-MOh 1/4 Watt resistor 1 10k tripot 100k tripot

Backgroun Inforation 3 Backgroun Inforation Sall-Signal Aplifier Design an Biasing In earlier experients with transistors we learne how to establish a esire DC operating conition. If a sall tie-varying signal is superipose on the DC bias at the input (gate or base terinal), then uner the right circustances the transistor circuit can act as a linear aplifier. Figure -1 illustrates the situation appropriate to a MOSFET coon-source aplifier. The transistor is first biase at a certain DC gate bias to establish a esire rain current, shown as the Q -point (quiescent point) Figure -1a. A sall AC signal of aplitue V is then superipose on the gate bias, causing the rain current to fluctuate synchronously. If V is sall enough, then we can approxiate the I curve by a straight line with a slope given by I g (.1) V an then the rain current aplitue is I g V. With a rain resistor R as shown, the rain current is relate to the output voltage by Vs V I R, so the AC output signal will be given by Vs I R gr V (.) The voltage gain is therefore Av gr. This can be appreciate graphically using a loaline approach as in Figure -1b. I D R I D I D V Q point V s V Slope I g V V / R Large R Sall R Q point I I V s V t V V knee V V s Vs R I g R V Figure -1 Aplification in a MOSFET coon-source configuration. (a) A sall AC signal is superipose on the DC gate bias, creating an AC rain current. (b) Sae situation with a loa-line superipose on the output characteristic, showing how the AC rain current leas to an AC rain voltage an gain of gr. Figure -1 also illustrates the iportance of the bias point selection in the operation of transistor aplifiers. Figure -1a shows that the transconuctance (an hence the gain) will epen on the gate bias; this can be quantifie using the I characteristic 3

4 MOS Aplifier Basics I K V V (.3) n t Substituting (.3) into (.1) gives I g Kn( V Vt) KnI (.4) ( V Vt ) To establish a large transconuctance we ust bias the evice well above threshol. This is also iportant to insure that the transistor stays in saturation over the full AC cycle. However, there is a liit on gate bias an rain current ipose by the output characteristic an loa resistor as shown in Figure -1b. To allow for axiu output voltage swing the Q-point shoul lie approxiately halfway between V an the ege of the ohic I D P P ax region, shown in the figure as V knee. If I ax the rain current or loa resistor is too large, the evice will swing into the ohic region uring operation leaing to P VsI Pax significant wavefor istortion. Another iportant consieration is the DC power issipation in the evice given by P VsI. This power is issipate as heat within the evice so there is always a theral liit on the issipate power for V ax V s every evice an package. The atasheet will specify the axiu DC power Figure - Liitations on biasing ipose by axiu power consierations. P ax, axiu DC current I ax, an axiu DC voltage V s ax, to avoi estroying the evice. These liits are superipose on the output characteristic in Figure -. The Q-point ust be selecte to lie below the shae region in the figure. Although the focus has been on MOSFETs in this iscussion, it is iportant to recognize that the key conclusions above are largely inepenent of the choice of evice. All transistors can be escribe by an output-current versus input-voltage characteristic like that in Figure -1a, an hence by a bias-epenent transconuctance. Only the etails of the voltage epenence will be ifferent. For exaple, BJTs follow a ioe-like exponential oel; state-of-the-art short-channel MOSFETs have a nearly linear I characteristic an hence a constant g. Lastly, note that the supply voltage is also an iportant variable. Generally a larger supply voltage is esirable for axiu voltage gain an axiu output voltage swing. This can be seen as follows: for a given rain current I, the rain resistor that is require for a rain bias of Vs V / is V Vs V R (.5) I I an thus the gain is given by g V Kn A v gr V I I (.6) The axiu gain scales with supply voltage for a specifie evice an current level.

Backgroun Inforation 5 MOSFET Design Paraeters an Subthreshol Currents For aplifier esigns using any transistor (MOSFETs or BJTs) we nee to know the transconuctance g. For MOSFETs, a knowlege of the threshol voltage V t an the current paraeter K n can be use to estiate g using (.4), assuing the square-law evice oel (.3) hols. A coon etho to estiate these paraeters is to easure an plot the square-root of I versus V, which theoretically shoul yiel a linear epenence, I K V V (.7) n t Thus the x-intercept if such a plot shoul yiel the threshol voltage, an the slope shoul yiel the current paraeter. This etho works reasonably well for oler MOSFET technologies with gate lengths of >μ; such evices are reasonably well oele by a square-law characteristic in saturation. For exaple, Figure -3a shows such a plot for the 6-7-8 NMOS evice in the CD4007 chip; these evices have gate lengths of ~10μ. Clearly the ata is well oele by the linear epenence preicte in (.7) for ost of the anticipate gate-bias range. For this particular ata set we fin Vt 1V an Kn 0.4A/V (reeber that threshol voltages can vary significantly fro one evice to another, so on t assue these values hol for your aplifiers!). 1/ Sqrt(I), I [A] A^0.5.5.0 1.5 1.0 0.5 0.0 0.5 0.0 0.15 0.10 0.05 0.00 0.8 1 1. 1.4 CD4007 n-ch 0 1 3 4 5 V, Volts I, A 6 5 4 3 1 0 Vt 1V K 0.4A/V n CD4007 N-ch Data Moel 0 1 3 4 5 V, Volts (a) (b) Figure -3 (a) Measure ata for one NMOS evice in the CD4007 chip, plotte as I vs. V, showing the linear epenence characteristic of a long-channel square-law evice. (b) Sae ata set plotte as I, with coparison to the ieal oel using given paraeters (ashe line). Near the threshol voltage in Figure -3a you can start to see soe sall eparture fro the square-law characteristic, which is typical of all MOS evices. Ieally the current shoul go to zero at the threshol voltage, but in real evices it just tails off exponentially an never quite goes to zero. This is calle subthreshol conuction, an the etails are beyon the scope of our iscussion here. The effect is significant only if we inten to operate the evice near threshol. For linear aplifiers using the CD4007, that is unlikely. Why? The MOSFETs in the CD4007 are sall, with gate withs of 30μ, an have a low n C ox prouct. Consequently they can not carry uch current (the ata sheet says 10A is the absolute axiu) an the transconuctance is rather sall. To get a nice voltage gain fro these evices we will nee to axiize the gr prouct, an for this particular evice that eans we nee to operate well above threshol. Even at a rain bias of ~5A, which is about as high as we can safely go, the transconuctance is only ~3S. So, as far as the 5

6 MOS Aplifier Basics CD4007 is concerne, we will always be operating it well above threshol where the evice is very well oele by a square-law characteristic. The N7000, also in your parts kit, is at the other extree: it is intene for larger currents an has an inherently larger transconuctance. Consequently we nee to operate this evice closer to threshol in orer to keep the DC currents low, an iperative fro a DC powerissipation stanpoint. The ata sheet specifies a axiu DC power issipation of 400W; for rain voltages in the range of.5-5v (appropriate to supply voltages in the range of 5-10V) we woul nee to keep the currents below ~100A. Figure -4 shows a easure plot of I for a N7000 for currents in this range; on this scale we can see a significant eparture fro the square-law characteristic. This evice has gate lengths of aroun.5u. 1/ Sqrt(I), I [A] A^0.5 N7000 10 9 8 7 6 5 Subthreshol 4 currents 3 1 0 1.5.0.5 3.0 V, Volts I, A 10 100 80 60 40 0 Vt.35V K 0A/V n N7000 Data Moel 0..4.6.8 3.0 3. V, Volts (a) (b) Figure -4 (a) Data for a N7000 evice plotte as I, showing sub-threshol currents. (b) Sae ata set plotte as I, with coparison to the ieal oel using given paraeters (ashe line) Is this a proble? No, it just eans that we can t expect (.3) to work well below currents of aroun 10A. Above 10A, the oel sees to work reasonably well, an for the particular evice shown in Figure -4 we fin Vt.35V an Kn 0A/V. Reeber, these paraeters vary fro N7000 evice to evice, an also ay vary 10 consierably fro anufacturer to 100 anufacturer. Figure -5 shows a 80 coparison of characteristic fro four ifferent N7000 evices, two fro one 60 anufacturer, an two fro another 40 anufacturer, selecte ranoly. Not only 0 oes the threshol voltage vary, but it is 0 apparent that the current paraeter K n..4.6.8 3.0 3. also varies between anufacturers. V, Volts Frankly the N7000 isn t a great choice for sall-signal linear aplifier esigns, it Figure -5 Coparison of four ifferent N7000 is really intene for use in power evices. Dashe lines an soli lines represent ifferent anufacturers. switching circuits. You ight woner why we chose the N7000 for this experient. The siple answer: it is cheap an ubiquitous, a coon thee for coponents use in ECE labs! I, A

Backgroun Inforation 7 Estiating Key Device Paraeters Measureents like those in Figure -3 an Figure -4 are great if you have the, but they take soe tie to generate. For siple aplifier esign we just nee a rough estiate of the evice paraeters, an the circuit in Figure -6 can be use for a quick estiate of g an V t. Recall that connecting the rain an gate terinals forces the FET to operate in saturation for any bias above threshol, so siply varying the supply voltage V allows us to ap out any part of the I characteristic in saturation. The proceure for eterining g is then as follows: ajust the supply voltage so that the aeter reas the esire bias current I, an recor the gate voltage. Next, change the supply voltage just a little, so that the gate voltage changes by a sall aount (e.g. V 50V ), an recor the resulting sall change in rain current I. The transconuctance is then approxiate by I g V (.8) A siilar proceure can be use to fin the threshol voltage, but for this step we ust assue that our square-law oel hols. Start again with a supply voltage that gives the esire rain current I ; if we efine V 1 as the corresponing gate voltage, then I K V V (.9) 1 n t Now, increase the supply voltage so that the rain current increases by a factor of four. This happens at a new gate voltage V 1, such that I K V V (.10) 4 n t Equations (.9) an (.10) can now be solve for the threshol voltage, giving V V V (.11) t 1 Once the threshol voltage is known, K n can be eterine by substituting back into (.9). It ust be reebere that the step outline above for eterining the threshol voltage epens on the use of a square-law oel for I. We have alreay seen that this oel oes not work well near threshol. Many oern FETs with short channel also follow a ifferent oel. So this etho only works well for oler, long-channel evices an at suitably chosen currents. In suary, using the circuit in Figure -6 allows the evice paraeters to be estiate quickly as follows: 1. Ajust the supply voltage V to establish a esire rain current I, an recor the corresponing gate voltage V 1. Increase V slightly so that V increases by a sall fixe aount (e.g. 50V), then fin g using (.8) 3. Increase the supply voltage further until the rain current increases to 4I, recor the corresponing gate voltage V, an fin the threshol voltage fro (.11) 4. Use one of the ata points above an your estiate of V t to eterine K n A V V out Figure -6 Circuit for estiating FET paraeters. 7

8 MOS Aplifier Basics In-Lab Proceure.1 Coon-Source Aplifier Coon-Source, no Source Resistor Figure -7 shows the basic coon-source aplifier with no source resistance. We have learne that this topology is intolerant of evice variations, specifically gate threshol variations, but it is nevertheless a goo place to start our experientation. The only new aitions to the circuit in coparison to the biasing networks we built in ECE B are the AC coupling capacitors. In this lab we will use rather large capacitors an focus just on the iban gain; the next lab will explore the ipact of these capacitors on the frequency response. Using the technique escribe in the backgroun section, fin the transconuctance for your N7000 evices assuing a esire bias current of I 0A, an also fin the threshol voltage an current paraeters. +10 V Using the circuit of Figure -7 an the paraeters you foun in the previous section, choose a suitable resistor R g1 that 0 Ω 100 kω will give a DC rain bias current of 10 μf V out I 0A (within 0% of that goal is fine) such that V V /. Feel free to use a V 10 μf in tripot or a ecae box for R g1. Recor the resistance value an resulting DC rain 10 kω current an rain voltage. R g1 Next, apply a 0.1V aplitue 1kHz sinewave at the input terinal using your bench function generator, an recor the input an Figure -7 Coon-source aplifier output wavefors on the oscilloscope. Be sure to use the correct polarity for the coupling capacitors. What is that voltage gain for this circuit? Copare with the siple result Av gr for the coon-source aplifier. Replace the 0Ω rain resistor with a 100Ω resistor an re-easure the voltage gain (the rain current shoul not change uch since this is eterine by V ). Copare again to the theoretical gain. Linearity an Wavefor Distortion Note that we have thus far kept the input signal very sall, well within the sall-signal requireent. As the input signal is increase in aplitue, eventually the sall-signal oel breaks own an the nonlinearity of the evice becoes iportant. This is anifest as significant wavefor istortion in the output signal. Using the circuit of Figure -7 with the 0Ω rain resistor, ouble the aplitue of the input signal to a 0.V aplitue sinusoi at 1kHz. Can you begin to see asyetry in the output signal? Recor your observations. Increase the input signal to 0.5V an recor the result.

Coon-Source Aplifier 9 The output signal can becoe istorte even for sall input signals if the gain is too large or the bias point is poorly chosen. In that case the output signal swing ay be large enough to causes the evice to enter the Ohic region of operation uring part of the cycle. Return the function generator to a 0.1V aplitue sinusoi, but swap the 0Ω rain resistor for a 470Ω resistor. Now recor the output wavefor. Can you explain why there is signal istortion in this case? Effect of Source an Loa Ipeances In the above experients we have teste the aplifier uner soewhat ieal conitions: using a source (the function generator) with a sall source resistance, an a high-ipeance loa (the 10k resistor). In practice the source an loa ipeance ay be coparable to the circuit ipeances an can have a V easurable effect on the aplifier perforance. Figure -8 shows a oifie circuit with these R R g1 aitional resistances. Note that V sig an R sig siply represent the Thevenin equivalent for any circuit R sig V out that rives the aplifier uner test. In a real application this ight be V sig R L another transistor aplifier stage. R g For lab experients we usually use a function generator, in which case the source resistance is shown R s on the front panel. Figure -8 CS ap with source an loa ipeances. Starting again with the circuit of Figure -7, a a loa resistance RL R at the output terinal an re-easure the voltage gain uner sall-signal conitions. Is your result consistent with the theoretical output ipeance of the CS aplifier ( Rout R )? If not, why? Siilarly, a a series resistance R sig that is approxiately equal to the input resistance you woul expect for your aplifier (in this case, Rg1 Rg), an recor the voltage gain. Fro your easureents, tabulate the following results for your aplifier: input ipeance, output ipeance, an open-circuit voltage gain. Fin an recor the source resistance of the benchtop function generator, an the input resistance of the oscilloscope. Fro this inforation an the results of your easureents above, escribe (in your lab report) whether the function generator an oscilloscope ha any significant effect on the easureent of your aplifier. Coon-Source with Source Resistor You ay recall that the aition of a source resistance is avantageous in orer to stabilize the circuit with respect to threshol voltage variations. However, this has a etriental effect on the gain, which we can see as follows: 9

10 MOS Aplifier Basics Construct the circuit of Figure -9. You will nee to change the gate bias network ( R g1 ) in orer to keep the rain current constant at aroun 10A (soething like 100k shoul work well for ost evices). +10 V Now easure the voltage gain uner opencircuit loa conitions an with a 0.1V input sinusoi at 1kHz. Why has the gain 0 Ω change? 100 kω 10 μf V out There is a siple trick to overcoe this liitation: siply a an AC bypass capacitor aroun the source resistance! V in 10 μf 10 kω A a 10μF capacitor in parallel with the 100 Ω source resistance an re-easure the voltage gain. Copare with the original circuit without the source resistance. Figure -9 Aing a source resistance. Explore the perforance of the circuit with respect to evice variations by swapping in a ifferent N7000 evice an re-easuring the DC rain current, DC rain voltage, an AC voltage gain. Inclue a coplete AC/DC analysis of this circuit in your lab report with coparison to your easure results. R g1. Coon-Gate Aplifier With a sall oification to the previous circuit we can ipleent a coon-gate aplifier, as shown in Figure -10. Note the 100μF AC coupling capacitor at the input, an the 10μF bypass capacitor on the gate; the latter akes the gate an AC groun, appropriate to the coon-gate configuration. Construct the circuit in circuit Figure -10. Be sure to use the correct polarity for the coupling capacitors, or the circuit ay not function properly. With the power supply on, the function generator connecte to the input port, an the oscilloscope set to observe the input voltage V in, ajust the aplitue of the function generator such that V in is a 50V sinusoi at 1kHz. Then easure an recor the AC voltage gain Vout / V in an copare with theory. You can appreciate the iportance of source resistance an input resistance consierations in this circuit with the following test: with the aplifier configure as in the previous step 10 μf 100 kω V in R g1 100 μf +10 V 0 Ω 10 μf R s 100 Ω 10 kω V out Figure -10 Coon-gate aplifier.

Aplifiers with Active Loaing 11 an the oscilloscope set to observe V in, turn off the +10V power supply to the circuit. The input wavefor shoul change significantly. Why? In aition to the non-inverting nature of this aplifier, the key ifference in coparison to the CS aplifier is the input resistance, which is approxiately Rin 1/ g. We will talk ore about this in lecture an in connection with the frequency response in later labs. In this case, the low input resistance fors a voltage ivier with the function generator. When the transistor is unbiase (off), R in the input resistance is approxiately Rin Rs 100, an when it is biase on, the input resistance is the parallel cobination of R an 1/ g. s Using the source resistance of the function generator, calculate the actual signal voltage V sig fro your easureent of V in in the unbiase state, an use this to eterine the overall gain of the circuit, V / V. out sig The low input resistance also eans that we ust use a larger AC coupling capacitor at the input, to keep the RF tie constant large enough for operation at 1 khz. You can see the iportance of this consieration in the following test: Replace the 100μF input capacitor by a 1uF capacitor an re-easure the voltage gain. Recor an explain your observations..3 Aplifiers with Active Loaing Feeback-Bias Aplifier You ay recall seeing the feeback-bias arrangeent shown in Figure -11a fro lecture an hoework assignents last quarter. This is attractive because it forces the evice to stay in saturation. Otherwise, the circuit is siilar in ost respects to the coon-source aplifier we constructe earlier: the voltage gain is approxiately A v g R. V V R f R R f I V out V out R L V in V in Figure -11 (a) Feeback-bias aplifier configuration, an (b) Siilar circuit with rain bias set with current source instea of a resistor. A rawback with this an our earlier CS aplifier is that the rain resistor siultaneously controls the gain an the rain bias point. As we saw earlier, if the rain resistance is increase in an attept to increase the gain, the rain bias point is reuce an R 11

1 MOS Aplifier Basics hence the allowable signal swing at the output is reuce. In contrast, the circuit of Figure -11b uses a constant-current bias to set the rain current. Since the effective ipeance of a current-source is infinite, the voltage gain in this case will be set by the loa resistance, ie. Av grl. In other wors, using a constant-current-source biasing, we can ecouple the gain an bias so that each can be ajuste inepenently. Constant-current biasing can be accoplishe with circuits like the one shown in Figure -1. Here Q3-Q4 are use to set a constant gate bias for Q, which serves as constantcurrent source for Q1; this is calle active loaing. However, Q is not an V V ieal current source; it has a finite output resistance given by Q Q ro VA / I, where V A is the Early 3 voltage. So in this case the gain will R C V A g r R. The f out becoe v o L open-circuit gain g r o is soetie calle the intrinsic gain of the circuit. You ay woner why we in t just use a resistor ivier to set the bias point for Q instea of Q3-Q4. We certainly coul ake a working circuit that way, but in integrate circuit esign it is ore size- an Q 4 C 1 cost-efficient to use transistors than resistors whenever possible. Seconly, active bias networks can also be esigne so that the bias-point to autoatically ajusts for evice variations inuce by teperature changes. That is a topic you will take up in ECE 137AB. CMOS Active-Loa CS Aplifier Let s buil the circuit Figure -1 using the CD4007. For convenience we have inclue the CD4007 pinout an equivalent circuits in Figure -13 below. V in Figure -1 CMOS coon-source aplifier with active (constant-source) biasing. Q 1 R L 1 V DD 14 P P 13 14 11 3 1 4 N P 11 6 13 8 3 1 5 10 1 5 10 6 N 9 7 N 8 7 4 9 V SS Figure -13 CD4007 pinout an siplifie scheatics.

Aplifiers with Active Loaing 13 NOTE: reeber that pins 14 an 7 ust ALWAYS be connecte to V (the positive supply) an Vss (the negative supply, or groun in this case) no atter which evices are being use: As a first step, easure the transconuctance g assuing a rain current of ~5A, an also easure the threshol voltage V t an current paraeter K n using the etho we iscusse earlier in the backgroun section (currents fro A to 8A are a goo choice). Measure one each of the n-channel an p-channel evices. Next, with the help of Figure -13, a pin nubers to the scheatic of Figure -1 to ake assebly easier. Because of the coon gate connections in the paire evices, so you will nee to use evices fro separate pairs for Q1 an Q. Now, asseble the circuit of Figure -1 using V 10V, R f 1M, an 1μF coupling capacitors ( C 1 an C ). Be sure to use the correct polarity of the coupling capacitors, or the circuit ay not function properly. Measure the DC voltages at the gate of Q an the rain of Q1. Fro this, estiate the current in Q1 an the transconuctance at this current using your oel paraeters. Apply a 0.1V sinusoi at 1 khz to the input an recor the input an output wavefors uner open-circuit loa conitions. Recor this intrinsic voltage gain. Now a a loa resistor RL 10k an re-easure the gain. Fro the reuction in gain, estiate the output resistance R out r o of the aplifier, an copare the easure intrinsic gain with the theoretical gr o. Now a a loa of RL 1k an easure the gain. How oes it copare with the A g r R? theoretical v o L Congratulations! You have now coplete Lab 13