Differential Amplifiers (Chapter 8 in Horenstein)

Differential Amplifiers (Chapter 8 in Horenstein) Differential amplifiers are pervasive in analog electronics Low frequency amplifiers High frequency amplifiers Operational amplifiers the first stage is a differential amplifier Analog modulators Logic gates Advantages Large input resistance High gain Differential input Good bias stability Excellent device parameter tracking in IC implementation Examples Bipolar 741 op-amp (mature, well-practiced, cheap) CMOS or BiCMOS op-amp designs (more recent, popular) SC412, slide 8-1 Amplifier With Bias Stabilizing Feedback Resistor Single transistor common-emitter or common-source amplifiers often use a bias stabilizing resistor in the common node leg (to ground) as shown below Such a resistor provides negative feedback to stabilize dc bias But, the negative feedback also reduces gain accordingly We can shunt the common node bias resistor with a capacitor to reduce the negative impact on gain Has no effect on gain reduction at low frequencies, however Large bypass capacitors are difficult to implement in IC design due to large area Conclusion: try to avoid using feedback resistor R2 in biasing network SC412, slide 8-2 1

Differential Amplifier Topology In contrast to the single device common-emitter (common-source) amplifier with negative feedback bias resistor of the previous slide, the differential shown at left provides a better bypass scheme. Device 2 provides bypass for active device 1 Bias provided by dc current source Device 2 can also be used for input, allowing a differential input Load devices might be resistors or they might be current sources (current mirrors) The basic differential amplifier topology can be used for bipolar diff amp design or for CMOS diff amp design, or for other active devices, such as JFETs SC412, slide 8-3 Differential Amplifier with Two Simultaneous Inputs The differential amplifier topology shown at the left contains two inputs, two active devices, and two loads, along with a dc current source We will define the differential mode of the input v i,dm = v 1 v 2 common mode of the input as v i,cm = ½ (v 1 +v 2 ) Using these definitions, the inputs v 1 and v 2 can be written as linear combinations of the differential and common modes v 1 = v i,cm + ½ v i,dm v 2 = v i,cm ½ v i,dm These definitions can also be applied to the output voltages Differential mode v o,dm = v o1 v o2 Common mode v o,cm = ½ (v o1 + v o2 ) Alternately, these can be written as v o1 = v o,cm + ½ v o,dm v o2 = v o,cm ½ v o,dm SC412, slide 8-4 2

Bipolar Transistor Differential Amplifier Q1 & Q2 are matched (identical) NPN transistors Rc is the load resistor Placed on both sides for symmetry, but could be used to obtain differential outputs I o is the bias current Usually built out of NPN transistor and current mirror network r n is the equivalent Norton output resistance of the current source transistor Input signal is switching around ground V ref = 0 for this particular design Both sides are DC-biased at ground on the base of Q1 and Q2 v BE is the forward base-emitter voltage across the junctions of the active devices Since Q1 and Q2 are assumed matched, Io splits evenly to both sides I C1 = I C2 = I o /2 SC412, slide 8-5 Bipolar Transistor Differential Amplifier 3

Small-Signal Model Analysis for Single Input Diff Amp Consider transistor Q2 with grounded base dc small-signal model shown in top-left figure Use the test voltage approach to calculate Q2 s input impedance looking into emitter Using KCL equations, we can write :i test = v test /r o i b2 where i b2 = - v test /r Rearranging and solving for v test /i test, we have r th2 = v test /i test = r /( o + 1) = ~ r / o = 1/g m2 Generally g m2 is large, causing r th2 to act like an ac short, SC412, slide 8-17 Small-Signal Model Analysis for Single Input Diff Amp Consider transistor Q1 with Q2 replaced by r th2 Since r th2 is much smaller than r n (output impedance of Io), we will neglect r n Writing KCL, we have v in = i b1 r 1 + i b1 ( o + 1) r th2 = i b1 2 r 1 where we assumed r 1 = r 2 We can now find vout as a function of vin v out = - i c1 R c = - o i b Rc = - o v in Rc/2r 1 = - ½ g m R c v in where we have used g m = o /r 1, Small signal gain A v = v out /v in = - ½ g m R c 4

Bipolar Diff Amp with Differential Inputs At left is a bipolar differential amplifier schematic having two inputs that are differential in nature, i.e. equal in magnitude but opposite in phase The differential input v 1 v 2 = v a (t) (-v a (t)) = 2v a (t) The common mode input = [v a + (-v a )]/2 = 0 SC412, slide 8-18 Bipolar Diff Amp with Differential Inputs (2) A small-signal model for the diff amp is shown below, where the Tx output collector resistance r o is assumed to be >> R C (in parallel) and is neglected We can derive the small-signal gain due to the differential input by applying KVL to loop A v a (t) (-v a (t)) = 2v a (t) = i b1 r 1 i b2 r 2 = 2i b1 r since i b1 = -i b2 and r 1 = r 2 Or, i b1 = v a (t)/r and i b2 = - v a (t)/r 5

Bipolar Diff Amp with Differential Inputs (continued) Solving for the output voltages we can obtain v o1 = -i c1 R C = - o i b1 R C = - ( o /r )v a (t)r C and v 02 = + ( o /r )v a (t)r C We can now find the gain with differential-mode input and single-ended output or with differential-mode input and differential output A dm-se1 = v 01 /v idm = -g m R C /2 and A dm-se2 = + g m R C /2 A dm-diff = (v 01 v 02 )/ v idm = - g m R C Since corresponding currents on the left and right side of the differential small-signal model are always equal and opposite, implying that no current ever flows throw r n Node E acts as a virtual ground If the output resistances of Q1 and Q2 are low enough to require keeping them in the analysis, we simply replace R C with the parallel combination of R C r o for transistor Q1 and Q2 SC412, slide 8-19 Small-Signal Model of BJT Diff Amp with CM Inputs The figure below is the small-signal model for the diff amp with common-mode inputs v1 = v2 = v b (t) and v icm = ½ (v1 + v2) = v b (t) The common-mode currents from both inputs flow through rn as shown by the two loops i n = 2( o + 1) i b1 = 2 ( o + 1) i b2 and therefore, v b = i b r + 2( o + 1)i b r n or i b = v b /[r + 2( o + 1)r n ] The collector voltages can be found as v 01 = v 02 = - o R C v b /[r + 2( o + 1)r n ] = ~ - g m R C v b / [1 + 2g m r n ] The common-mode gain with single-ended output is given by A cm-se1 = A cm-se2 = v o1 /v icm = v o2 /v icm = - g m R C /[1 + 2g m r n ] = ~ -R C /2r n The common-mode gain with differential output is A cm-diff = (v o1 v o2 )/v icm = 0 Do Example 8.1, p. 488 SC412, slide 8-20 6

Small-Signal Model of BJT Diff Amp with CM Inputs BJT Diff Amp Circuit with Both Diff & CM Inputs The example below illustrates the principle of superposition in dealing with both differential mode and common mode inputs to a diff amp v 1 = v x cos 1 t + v y sin 2 t and v 2 = v x cos 1 t v y sin 2 t Using the definitions of differential mode and common mode inputs, respectively, v idm = v1 v2 = 2v y sin 2 t and v icm = (v1 + v2)/2 = v x cos 1 t, we can obtain v o1 = A dm-se1 v idm + A cm-se1 v icm = - o R C [(v y / r ) sin 2 t + (v x /{r + 2 ( o + 1) r n }) cos 1 t] The expression for v 02 is similar except that the first term (differential mode) has a minus sign Note that the common mode output is reduced by the factor ( o + 1) in the denominator SC412, slide 8-21 7

Common-Mode Rejection Ratio In a differential amplifier we typically want to amplify the differential input while, at the same time, rejecting the common-mode input signal A figure of merit Common Mode Rejection Ratio is defined as CMRR = A dm / A cm where A dm is the differential mode gain and A cm is the common mode gain For a bipolar diff amp with differential output, the CMRR is found to be CMRR = A dm-diff / A cm-diff = - g m R C / 0 = infinity In the case of the bipolar diff amp with single-ended output, CMRR is given by CMRR = A dm-se / A cm-se = ½g m R C / o R C /[r + 2( o + 1)r n ] = [r + 2( o + 1)r n ]/2r = ~ o r n /r = g m r n = I C r n / V T = I o r n /2 V T since o = g m r and V T is defined as kt/q CMRR is often expressed in decibels, in which case the definition becomes CMRR = 20 log ( A dm / A cm ) SC412, slide 8-22 BJT Diff Amp Input and Output Resistance Input Resistance: For differential-mode inputs, the input resistance can be found as r in-dm = (v1 v2)/i b1 = (v a (-v a )) / (v a /r ) = 2v a r /v a = 2r For common-mode inputs, the input resistance is quite different r in-cm = ½(v1 + v2)/i b1 = v b / [v b /(r + 2( o + 1)r n )] = r + 2( o + 1)r n Output Resistance: For differential outputs, we can use the test voltage method (below) for deriving the output resistance where all inputs are set to zero Since i b1 and i b2 are both zero, we have i test = v test /(R C + R C ) = v test /2R C or r out-diff = 2R C For single-ended outputs, r out-se = R C r o = ~ R C SC412, slide 8-23 8

Bipolar Diff Amp Biasing Considerations SC412, slide 8-24 A bipolar differential amplifier with ideal current source and resistor loads is shown It is assumed that components are matched sufficiently such that bias current Io is split evenly between the left and right-hand legs Node E will take a voltage value such that I C1 = I C2 = Io/2 when v1 = v2 = 0 By using the Ebers-Moll dc model for the NPN transistors, we can determine the voltage at node E I E = I EO [exp (qv BE / kt) 1] = I EO exp (qv BE / kt) = Io/2 or, V BE = ( kt/q) ln (I E /I EO ) Typically, V BE = 0.75-0.85 V in modern NPN transistors It is important to design R C such that v out never drops so low so as to force Q1 or Q2 into saturation. BJT Diff Amp with Simple Resistor Current Source The simplest approach to building a current source is with a resistor Given that node E is one V BE drop below GND, we can choose R E to provide the desired bias current I o R E = (0 V BE V EE ) / Io Preventing saturation in Q1 and Q2 provides an upper bound for R C R C ~ < (V CC 0)/(Io/2) = 2 V CC / Io Look at Example 8.3 in text. Do problem 8.31 in class. SC412, slide 8-25 9

Example 8.3: Diff Amp with Complete Bias Design Example 8.3: Diff Amp with Complete Bias Design Design Conditions Differential-mode, single-ended gain > = 50 Common-mode, single-ended gain < = 0.2 Completed design is shown above In class Exercise: 8.4, 8.5, & 8.6 SC412, slide 8-26 10

DISEÑO BJT Diff Amp with BJT Current Source The expression for common-mode gain on slide 8-20 (-R C /2r n ) shows that in order to reduce A cm, we want to make the effective impedance of the current source very high Using a resistor to generate the current source limits our design options in making r n (R E in this case) high An alternate method of generating Io is to use an NPN transistor current source similar to that shown at the left Q3 is an NPN biased in the forward active region so that r n (given by the inverse slope of the collector characteristics) is very high RA and RB form a voltage divider establishing V B = V EE x RA/(RA + RB) where V EE is <0 The voltage across RE can be used to find Io V RE = V B V f V EE Io = (V B V f V EE )/RE is the bias current provided to the diff amp SC412, slide 8-27 11

SC412, slide 8-28 Small Signal Model of BJT Current Source Transistor Find the small-signal resistance looking into the collector of Q3 on slide 8-27 diff amp If R E were = 0, then the solution becomes simply r o, since the incremental base current i b3 would, in fact, be 0 With a finite feedback resistor R E, we need to use KVL and KCL to derive an expression for r n (See Example 8.4 in text) Apply a test current i test and find v test Obtain v 3 by applying KVL to the 3 left-most resistors to obtain i b3 and multiply by r 3 v 3 = -i test R E r 3 /[R E + r 3 + R P ] If we multiply this result by g m3 and substract from i test, we obtain i o3 which can be used to find v o3 by multiplying by r 03 v o3 = i test {1 + g m3 R E r 3 /[R E + r 3 + R P ]}r o3 v e can be found as (i test + i b3 ) x R E v e = i test (r 3 + R P ) R E /(R E + r 3 + R P ) Adding v o3 + v e = v test, we obtain r n = v test /i test r n = R E (r 3 + R P ) + r 03 [1 + o R E /(R E + r 3 +R P )] Do Exercise 8.8 and 8.9 in class. Bipolar Current Mirror Circuit A method used pervasively in analog IC design to generate a current source is the current mirror circuit In the bipolar design arena, the method is as follows: A reference current is forced through an NPN transistor connected as a base-emitter diode (base shorted to collector), thus setting up a V BE in the reference transistor This V BE voltage is then applied to one or more other identical NPN transistors which sets up the same current I ref in each one of the bias transistors As long as the bias transistor(s) is (are) identical to the reference transistor, and as long as the bias transistor(s) is maintained in its normal active region (where collector current is independent of the collector-emitter voltage), then the current in the bias transistor(s) will be identical to the current in the reference transistor. Variations on the basic current mirror circuit can be used to generate 2X or 3X or maybe 10X the original reference current by using several bias NPN transistors in parallel Or alternately, by using an emitter that has 2X or 3X or 10X emitter stripes and is otherwise identical to the reference transistor Advantages One reference current generator can be used to provide bias to several stages Very high incremental output impedance can be obtained from the current mirror The technique can be used in both bipolar and in CMOS/BiCMOS technologies SC412, slide 8-29 12

Bipolar Current Mirror Bias Circuit Design Design procedure: Given R A and the I C vs V BE characteristics of the NPN reference device, we can determine I A, or Given the desired I A and the I C vs V BE characteristics of the NPN reference device, we can choose R A We can find I A by dividing the voltage drop across R A by the resistance value I A = (V CC V BE1 V EE ) / R A Assuming that the two base currents are small, we can say I A = I ref Because of the current mirror action, the V BE1 set up in Q1 to sustain current I ref will be equal to V BE2, the base-emitter voltage in Q2 Therefore, Io = I ref = I A Note: corrections for I B1 and I B2 can easily be made is needed Note 2: Q2 must be maintained in its forward active region SC412, slide 8-30 BJT Diff Amp with Current Mirror Bias (Ex. 8.5) SC412, slide 8-31 Design Objectives: Diff amp with 1.5 ma in each leg 5V drop across load resistors VCC = +10V, VEE = -10V Design Procedure: Set Io = I A = 3 ma R A = (0 V BE = V EE )/3mA = 3.1K where we used V BE = 0.7 volt RC1 & RC2 can be found as follows: RC1 = RC2 = 5V/1.5 ma = 3.3K Check V CE of Q2, Q3, and Q4 to see if they are in normal active region V C = VCC 1.5 ma x 3.3K = 5V V E = 0 V BE = -0.7V V CE = 5 (-0.7) = 5.7V for Q2 and Q3 For Q2 VCE = -0.7V (-10) = -9.3V Calculate power in each device P Q3 = P Q4 = 1.5mA x 5.7V = 8.6 mw P Q2 = 3 ma x 9.3V = 28 mw P Q1 = 3 ma x 0.7V = 2.1 mw 13

BJT Current Mirror Feeding 2-stage Diff Amp The example below shows a 2-stage bipolar diff amp fed from two current sources with a single current mirror Reference current 0.93mA is determined by placing (0 V BE V EE ) across a 10K bias resistor The reference current is used for the first differential stage with 0.47 ma on each leg The second differential stage is to have double the bias current of the first stage This is accomplished by using two bias NPN transistors in parallel giving 1.86 ma bias current with 0.93 ma flowing on each leg (Q7 and Q8) Check the VCE of each device to check for normal active region and calculate power in circuit. The total circuit power is found by computing the sum of the three current source currents multiplied by the source-sink voltage differential for each. Q1: 0.93mA x 10V = 9.3mW Q2: 0.93mA x 20V = 18.6mW Q3/Q4: 1.86mA x 20V = 37.2 mw Total circuit power = 65.1 mw SC412, slide 8-32 Example iteration procedure: Assume that Iref = 1 ma and R2 = 500 ohms. Guess Io inside ln term. Find LHS Io. 1. Initial guess = 0.5 ma, then Io = 0.036mA 2. Try a guess of 0.2 ma, then Io = 0.083mA 3. Try a guess of 0.1mA, then Io = 0.119mA 4. Try a guess of 0.11mA, then Io = 0.114mA Close enough!! Bipolar Widlar Current Source A special use of the current mirror is the Widlar Current Source (shown at left) A resistor in the emitter of Q2 is used to reduce the current Io in Q2 to a value less than that in Q1 Io can be set to a very small value by increasing the R2 value Design procedure: As in the standard current mirror, we can find I ref as follows: I ref = (V CC V EE V BE1 )/R A But, in contrast to the standard current mirror, V BE2 will not be equal to V BE1 V BE1 = V BE2 + I E2 R 2 Using the Ebers-Moll model for emitter current I E = I EO (exp[v BE / V T ] 1) = ~ I EO exp[v BE / V T ] We can invert this expression and insert it into the above equation for V BE1 to obtain I E2 = ( V T /R 2 ) ln(i E1 /I E2 ) = Io = ( V T /R 2 ) ln(i ref /I o ) Since this is not a closed form solution, an iterative approach can be used to solve for Io by starting with a best guess. SC412, slide 8-33 14

Small-Signal Model for Widlar Current Source Q1 The incremental output impedance (looking into Q2 collector) of Widlar Current Source is similar to the expression derived for the BJT current source (slide 8-28) except that RP must be replaced by the incremental resistance at the base of Q1 From the model below, the incremental resistance at the base of Q1 is given by r 1 1/g m1 r o1 R A = ~ [r 1 /( o1 + 1)] R A Thus, the output impedance seen looking into the collector of the Widlar Current Source is given by r n = R 2 (r 2 + R P ) + r 02 [1 + o2 R 2 /(R 2 + r 2 +R P )] where the above expression is to be used in place of R P However, with a number of approximations and using the relation I o R 2 / V T = ln (I ref /I o ), the expression may usually be simplified to r n = r 02 [1 + ln (I ref /I o )] Look over Example 8.9 in text. SC412, slide 8-34 Amp. Multietapa con Diferenciales El circuito de la figura 2 funciona como un amplificador rudimentario. La salida del amplificador diferencial está derivada en una forma de una sola terminal y alimentada a un seguidor de voltaje que sirve como un acoplador de salida. Suponga que la BF de cada transistor ocurre en el rango de 50 a 200. A. Encuentre el punto de operación aproximado de cada transistor del circuito para un valor supuesto de Vf=0.7V. B. Identifique las entradas V+ y V-. C. Determine las expresiones para las ganancias diferencial y común del amplificador. V1 0 Q4 R3 5k R1 10k Q5 VCC=6 0 VEE=-6 Figura 2 V2 Q3 Vo R2 10k 15

Amp. Multietapa con Diferenciales Utilicé donde sea apropiado aproximaciones de ingeniería, y suponga que están pareados todos los BJT, determine Los valores aproximados del punto de polarización de cada uno de los transistores. La ganancia de voltaje en pequeña señal Vo/(V1-V2). R1 39k R2 27k R3 27k R4 10k Q3 Q4 R5 10k VCC=10 V1 Q1 Q2 V2 Q5 Vo QA QB QC R7 10k VEE=-10 Diseño Con Amplificadores Diferenciales Diseñe un amplificador diferencial a BJT que cumpla con las especificaciones siguientes: A dm =100, CMRR>60dB, Rango de excursión diferencial en las terminales de salida de por lo menos 3 v pico. r in-dif >1k r out-se <1k, Están disponibles canales de alimentación de mas o menos 10 v 16

Para la figura 1 todos los transistores PNP están pareados, con B 0 =100 para todos los transistores, determine: Determine la corriente Ic y los voltajes colector emisor de cada transistor. (0.5) Dibuje el modelo en pequeña señal y determine la rin de entrada y la resistencia de salida en modo diferencial y modo común del amplificador.(0.6) Especifique cuál es la terminal v+ y cual es la v-.(0.4) Encuentre la ganancia en la banda media en modo diferencial.(0.4) Encuentre la ganancia en la banda media en modo común.(0.4) Determine el CMRR del amplificador.(0.2) 10V Q1 Q2 R1 30K R5 50K 0 Q4 V1 Q3 0 V2 Q5 Vout 0 R2 33K R3 33K R4 22K -10V 17