NCS711, NCV711 1.8 Volt RailtoRail Operational Amplifier The NCS711 operational amplifier provides railtorail operation on both the input and output. The output can swing within 5 mv of each rail. This railtorail operation enables the user to make full use of the entire supply voltage range available. It is designed to work at very low supply voltages (1.8 V and ground), yet can operate with a supply of up to 1 V and ground. The NCS711 is available in the space saving SOT235 package with two industry standard pinouts. Features Low Voltage, Single Supply Operation (1.8 V and Ground to 1 V and Ground) 1. pa Input Bias Current Unity Gain Bandwidth of 1. MHz at 5. V,.9 MHz at 1.8 V Output Voltage Swings Within 5 mv of Both Rails @ 1.8 V No Phase Reversal on the Output for OverDriven Input Signals Input Offset Trimmed to 1. mv Low Supply Current (I D = 1. ma) Works Down to Two Discharged NiCd Battery Cells ESD Protected Inputs Up to 2. kv These Devices are PbFree and are RoHS Compliant AECQ1 Qualified and PPAP Capable *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements Typical Applications Dual NiCd/NiMH Cell Powered Systems Portable Communication Devices Low Voltage Active Filters Power Supply Monitor and Control Interface to DSP LOW VOLTAGE RAILTORAIL OPERATIONAL AMPLIFIER 5 V OUT NonInverting Input V OUT V EE NonInverting Input 1 CASE 483 SOT235 SN SUFFIX MARKING DIAGRAM 5 x = C for SN1 D for SN2 AAx AYW A = Assembly Location Y = Year 1 W = Work Week = PbFree Package (Note: Microdot may be in either location) PIN CONNECTIONS 1 2 3 5 4 V EE Style 1 Pin Out (SN1T1) 1 2 3 5 4 Inverting Input Inverting Input Rail to Rail Input Rail to Rail Output Style 2 Pin Out (SN2T1) ORDERING INFORMATION 1.8 V to 1 V This device contains 68 active transistors. Figure 1. Typical Application Device Package Shipping NCS711SN1T1G NCV711SN1T1G* NCS711SN2T1G NCV711SN2T1G* SOT235 (PbFree) 3 Tape & Reel (7 inch Reel) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. Semiconductor Components Industries, LLC, 211 October, 211 Rev. 4 1 Publication Order Number: NCS711/D
NCS711, NCV711 MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage ( to V EE ) V S 1 V Input Differential Voltage Range (Note 1) V IDR V EE 3 mv to 1 V V Input Common Mode Voltage Range (Note 1) V ICR V EE 3 mv to 1 V V Output Short Circuit Duration (Note 2) t SC Indefinite sec Junction Temperature T J 15 C Power Dissipation and Thermal Characteristics SOT235 Package Thermal Resistance, JunctiontoAir Power Dissipation @ T A = 7 C R JA 22 P D 364 Storage Temperature Range T stg 65 to 15 C Operating Ambient Temperature Range NCS711 NCV711 T A 4 to 85 4 to 125 ESD Protection at any Pin Human Body Model (Note 3) V ESD 2 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Either or both inputs should not exceed the range of V EE 3 mv to V EE 1 V. 2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. T J = T A (P D R JA ) 3. ESD data available upon request. C/W mw C 2
NCS711, NCV711 DC ELECTRICAL CHARACTERISTICS ( = 2.5 V, V EE = 2.5 V, V CM = V O =, R L to GND,, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage =.9 V, V EE =.9 V = 2.5 V, V EE = 2.5 V = 5. V, V EE = 5. V Input Offset Voltage Temperature Coefficient (R S = 5) T A = 4 C to 125 C V IO 7. 9. 7. 9. 7. 9..6.6.6 7. 9. 7. 9. 7. 9. mv V IO / T 8. V/ C Input Bias Current ( = 1.8 V to 1 V) I IB 1. pa Common Mode Input Voltage Range V ICR V EE V Large Signal Voltage Gain = 5. V, V EE = 5. V R L = 1 k R L = 2. k A VOL 16 16 5 3 kv/v Output Voltage Swing, High (V ID =.2 V) =.9 V, V EE =.9 V () R L = 1 k R L = 2. k R L = 1 k R L = 2. k = 2.5 V, V EE = 2.5 V () R L = 6 R L = 2. k R L = 6 R L = 2. k = 5. V, V EE = 5. V () R L = 6 R L = 2. k R L = 6 R L = 2. k V OH.85.8.85.79 2.1 2.35 2. 2.4 4.4 4.8 4.4 4.8.88.82 2.21 2.44 4.6 4.88 V Output Voltage Swing, Low (V ID =.2 V) =.9 V, V EE =.9 V () R L = 1 k R L = 2. k R L = 1 k R L = 2. k = 2.5 V, V EE = 2.5 V () R L = 6 R L = 2. k R L = 6 R L = 2. k = 5. V, V EE = 5. V () R L = 6 R L = 2. k R L = 6 R L = 2. k V OL.88.82 2.22 2.38 4.66 4.88.85.8.85.78 2.1 2.35 2. 2.3 4.4 4.8 4.35 4.8 V Common Mode Rejection Ratio V in = to 1 V V in = to 5. V CMRR 65 6 db 3
NCS711, NCV711 DC ELECTRICAL CHARACTERISTICS (continued) ( = 2.5 V, V EE = 2.5 V, V CM = V O =, R L to GND,, unless otherwise noted.) Characteristics Symbol Power Supply Rejection Ratio /V EE = 1 V/Ground, V S = 2.5 V Min Typ Max Unit PSRR 65 db Output Short Circuit Current (V in Diff = 1. V) =.9 V, V EE =.9 V Source Sink = 2.5 V, V EE = 2.5 V Source Sink = 5. V, V EE = 5. V Source Sink I SC 2 6 5 14 3. 3. 25 25 72 72 6 2 14 5 ma Power Supply Current (V O = V) =.9 V, V EE =.9 V T A = 4 C to 85 C T A = 4 C to 125 C = 2.5 V, V EE = 2.5 V T A = 4 C to 85 C T A = 4 C to 125 C = 5. V, V EE = 5. V T A = 4 C to 85 C T A = 4 C to 125 C I D.97 1.5 1.13 1.2 1.3 1.6 1.3 1.4 1.7 1.4 1.5 1.8 ma AC ELECTRICAL CHARACTERISTICS ( = 2.5 V, V EE = 2.5 V, V CM = V O =, R L to GND,, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Slew Rate (V O = 2. to 2. V, R L = 2. k, A V = 1.) SR.7 1.2 3. V/ s Gain Bandwidth Product ( = 1 V) GBW.5 1. 3. MHz Gain Margin (R L = 1 k, C L = 5. pf) Am 6.5 db Phase Margin (R L = 1 k, C L = 5. pf) φm 6 Deg Power Bandwidth (V O = 4. Vpp, R L = 2. k, THD 1.%) BW P 13 khz Total Harmonic Distortion (V O = 4. Vpp, R L = 2. k, A V = 1.) f = 1. khz f = 1 khz THD.2.2 % Differential Input Resistance (V CM = V) R in 1. tera Differential Input Capacitance (V CM = V) C in 2. pf Equivalent Input Noise Voltage (Freq = 1. khz) e n 14 nv/ Hz 4
NCS711, NCV711 V sat, OUTPUT SATURATION VOLTAGE (mv) 4 8 12 12 8 High State Output Sourcing Current Low State Output Sinking Current R L = to GND 4 V EE 1 1. k 1 k 1 k 1. M R L, LOAD RESISTANCE ( ) V sat, OUTPUT SATURATION VOLTAGE (V).4.8 1.2 1.2.8.4 R L = to GND High State Output Sourcing Current Low State Output Sinking Current V EE 2. 4. 6. 8. 1 12 I L, LOAD CURRENT (ma) Figure 2. Output Saturation Voltage versus Load Resistance Figure 3. Output Saturation Voltage versus Load Current I IB, INPUT CURRENT (pa) 1 1 1 1..1 R L = C L = A V = 1. 25 5 75 1 125 A VOL, GAIN (db) 1 8 6 4 2 PHASE GAIN V S = ±5. V R L = 1 k 18 1. 1 1 1. k 1 k 1 k 1. M 1 M 2 6 1 14, EXCESS PHASE ( ) T A, AMBIENT TEMPERATURE ( C) Figure 4. Input Bias Current versus Temperature Figure 5. Gain and Phase versus Frequency 5 mv/div V O = 4. V PP R L = 1 k C L = 1 pf A V = 1. 5 mv/div V O = 4. V PP R L = 1 k C L = 1 pf A V = 1. t, time (5 ns/div) t, time (1. s/div) Figure 6. Transient Response Figure 7. Slew Rate 5
NCS711, NCV711 V out, OUTPUT VOLTAGE (V PP ) 14 12 1 8. 6. 4. 2. V S = ±5. V V S = ±.9 V R L = 1 k A V = 1. 1. k 1 k 1 k 1. M Figure 8. Output Voltage versus Frequency CMR, COMMON MODE REJECTION (db) 1 9 8 7 6 5 4 3 2 1 1 1 1 1. k 1 k 1 k 1. M 1 M R L = A V = 1. Figure 9. Common Mode Rejection versus Frequency PSR, POWER SUPPLY REJECTION (db) 1 9 8 7 6 5 4 3 2 1 PSR PSR 1 1 1 1. k 1 k 1 k 1. M 1 M R L = A V = 1. I SC, OUTPUT SHORT CIRCUIT CURRENT (ma) 14 12 1 8 6 4 2 Output Pulsed Test at 3% Duty Cycle 25 C 4 C 85 C ±1. ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) Figure 1. Power Supply Rejection versus Frequency Figure 11. Output Short Circuit Sinking Current versus Supply Voltage I SC, OUTPUT SHORT CIRCUIT CURRENT (ma) 14 12 1 8 6 4 2 Output Pulsed Test at 3% Duty Cycle 25 C 4 C 85 C ±1. ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) I D, SUPPLY CURRENT (ma) 1.4 1.2 1..8.6 85 C 25 C 4 C.4 R L =.2 A V = 1. V in = V ±1. ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) Figure 12. Output Short Circuit Sourcing Current versus Supply Voltage Figure 13. Supply Current versus Supply Voltage with No Load 6
NCS711, NCV711 THD, TOTAL HARMONIC DISTORTION (%) 1 1..1.1 A V = 1 A V = 1 A V = 1 A V = 1..1 1 1 1. k 1 k 1 k Figure 14. Total Harmonic Distortion versus Frequency with 5. V Supply THD, TOTAL HARMONIC DISTORTION (%) 1 1..1 A V = 1 A V = 1 A V = 1 V out = 4. V PP.1 R L = 2 k A V = 1. V S = ±5. V V out = 8. V PP R L = 2 k.1 1 1 1. k 1 k 1 k Figure 15. Total Harmonic Distortion versus Frequency with 1 V Supply THD, TOTAL HARMONIC DISTORTION (%) 1 1..1.1 A V = 1 A V = 1 A V = 1 V out = 4. V PP R L = 1 k A V = 1..1 1 1 1. k 1 k 1 k Figure 16. Total Harmonic Distortion versus Frequency with 5. V Supply THD, TOTAL HARMONIC DISTORTION (%) 1 1..1 A V = 1 A V = 1.1 A V = 1 V S = ±5. V V out = 8. V PP R L = 1 k A V = 1..1 1 1 1. k 1 k 1 k Figure 17. Total Harmonic Distortion versus Frequency with 1 V Supply SR, SLEW RATE (V/ s) 1.6 1.2.8.4 Slew Rate, Slew Rate, Slew Rate, V S = ±.9 V R L = 1 k C L = 1 pf A V = 1. Slew Rate, V S = ±.9 V 5 25 25 5 75 1 125 GBW, GAIN BANDWIDTH PRODUCT (MHz) 3. 2. 1. R L = 1 k C L = 5.3 pf 5 25 25 5 75 1 125 T A, AMBIENT TEMPERATURE ( C) T A, AMBIENT TEMPERATURE ( C) Figure 18. Slew Rate versus Temperature (Avg.) Figure 19. Gain Bandwidth Product versus Temperature 7
NCS711, NCV711 A V, GAIN (db) 5 2 4 3 2 1 1 2 V S = ±.9 V 3 3 1 k 1 k 1. M 1 M 1 M R L = 1 k A V = 1 2 6 1 14 18 22 26 Φ, EXCESS PHASE ( ) A m, GAIN MARGIN (db) 8 7 6 5 4 3 2 1 Phase Margin Gain Margin R L = 1 k C L = 1 pf 5 25 25 5 75 1 125 T A, AMBIENT TEMPERATURE ( C) 8 7 6 5 4 3 2 1 Φ m, PHASE MARGIN ( ) Figure 2. Voltage Gain and Phase versus Frequency Figure 21. Gain and Phase Margin versus Temperature A m, GAIN MARGIN (db) 1 8 6 4 2 Phase Margin Gain Margin 1 R L = 1 k 2 C L = 5. pf 2 4 4 1 1 1. k 1 k 1 k 1.M R t, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 22. Gain and Phase Margin versus Differential Source Resistance 8 6 4 2 Φ m, PHASE MARGIN ( ) A V, GAIN MARGIN (db) 7 6 5 4 3 2 1 Phase Margin Gain Margin R L = 1 k A V = 1 1. 1 1 1 C L, CAPACITIVE LOAD (pf) Figure 23. Gain and Phase Margin versus Output Load Capacitance 7 6 5 4 3 2 1 Φ m, PHASE MARGIN ( ) V out, OUTPUT VOLTAGE (V PP ) 12 1 8. 6. 4. 2. R L = 1 k A V = 1 Split Supplies 2. 4. 6. 8. 1 V EE, SUPPLY VOLTAGE (V) Figure 24. Output Voltage Swing versus Supply Voltage A m, GAIN MARGIN (db) 8 7 6 5 4 3 2 1 A V = 1 R L = 1 k C L = ±1. Phase Margin Gain Margin ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) Figure 25. Gain and Phase Margin versus Supply Voltage 8
NCS711, NCV711 A VOL, OPEN LOOP GAIN (db) 12 11 1 9 8 7 6 ±1. ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) R L = 1 k C L = V IO, INPUT OFFSET VOLTAGE (mv) 2 15 1 5 5 1 15 R L = C L = A V = 1. 2 3. 2. 1. 1. 2. 3. V CM, COMMON VOLTAGE RANGE (V) Figure 26. Open Loop Voltage Gain versus Supply Voltage (Split Supplies) Figure 27. Input Offset Voltage versus Common Mode Input Voltage Range, V S = 2.5 V V IO, INPUT OFFSET VOLTAGE (mv) 2 15 1 5 5 1 15 V S = ±.9 V R L = C L = A V = 1. 2 1..8.6.4.2.2.4.6.8 1. V CM, COMMON MODE INPUT VOLTAGE (V) V CM, COMMON MODE INPUT VOLTAGE RANGE (V) 6. 4. 2. 2. 4. V IO = 5. mv R L = C L = A V = 1. 6. ±.5 ±1. ±2. ±3. ±4. ±5. V S, SUPPLY VOLTAGE (V) Figure 28. Input Offset Voltage versus Common Mode Input Voltage Range, V S =.9 V Figure 29. CommonMode Input Voltage Range versus Power Supply Voltage 9
NCS711, NCV711 APPLICATION INFORMATION AND OPERATING DESCRIPTION GENERAL INFORMATION The NCS711 is a railtorail input, railtorail output operational amplifier that features guaranteed 1.8 volt operation. This feature is achieved with the use of a modified analog CMOS process that allows the implementation of depletion MOSFET devices. The amplifier has a 1. MHz gain bandwidth product, 1.2 V/ s slew rate and is operational over a power supply range less than 1.8 V to as high as 1 V. Inputs The input topology of this device series is unconventional when compared to most low voltage operational amplifiers. It consists of an Nchannel depletion mode differential transistor pair that drives a folded cascode stage and current mirror. This configuration extends the input common mode voltage range to encompass the V EE and power supply rails, even when powered from a combined total of less than 1.8 volts. Figures 27 and 28 show the input common mode voltage range versus power supply voltage. The differential input stage is laser trimmed in order to minimize offset voltage. The Nchannel depletion mode MOSFET input stage exhibits an extremely low input bias current of less than 4 pa. The input bias current versus temperature is shown in Figure 4. Either one or both inputs can be biased as low as V EE minus 3 mv to as high as 1 V without causing damage to the device. If the input common mode voltage range is exceeded, the output will not display a phase reversal but it may latch in the appropriate high or low state. The device can then be reset by removing and reapplying power. If the maximum input positive or negative voltage ratings are to be exceeded, a series resistor must be used to limit the input current to less than 2. ma. The ultra low input bias current of the NCS711 allows the use of extremely high value source and feedback resistor without reducing the amplifier s gain accuracy. These high value resistors, in conjunction with the device input and printed circuit board parasitic capacitances C in, will add an additional pole to the single pole amplifier shown in Figure 3. If low enough in frequency, this additional pole can reduce the phase margin and significantly increase the output settling time. The effects of C in, can be canceled by placing a zero into the feedback loop. This is accomplished with the addition of capacitor C fb. An approximate value for C fb can be calculated by: Cfb R in Cin Rfb Input R in C in C fb Figure 3. Input Capacitance Pole Cancellation R fb Output C in = Input and printed circuit board capacitance Output The output stage consists of complementary P and N channel devices connected to provide railtorail output drive. With a 2. k load, the output can swing within 1 mv of either rail. It is also capable of supplying over 95 ma when powered from 1 V and 3. ma when powered from 1.8 V. When connected as a unity gain follower, the NCS711 can directly drive capacitive loads in excess of 39 pf at room temperature without oscillating but with significantly reduced phase margin. The unity gain follower configuration exhibits the highest bandwidth and is most prone to oscillations when driving a high value capacitive load. The capacitive load in combination with the amplifier s output impedance, creates a phase lag that can result in an underdamped pulse response or a continuous oscillation. Figure 32 shows the effect of driving a large capacitive load in a voltage follower type of setup. When driving capacitive loads exceeding 39 pf, it is recommended to place a low value isolation resistor between the output of the op amp and the load, as shown in Figure 31. The series resistor isolates the capacitive load from the output and enhances the phase margin. Refer to Figure 33. Larger values of R will result in a cleaner output waveform but excessively large values will degrade the large signal rise and fall time and reduce the output s amplitude. Depending upon the capacitor characteristics, the isolation resistor value will typically be between 5 to 5 ohms. The output drive capability for resistive and capacitive loads is shown in Figures 2, 3, and 23. Input R Isolation resistor R = 5 to 5 Output C L Figure 31. Capacitance Load Isolation Note that the lowest phase margin is observed at cold temperature and low supply voltage. 1
NCS711, NCV711 Figure 32. Small Signal Transient Response with Large Capacitive Load Figure 33. Small Signal Transient Response with Large Capacitive Load and Isolation Resistor. 11
NCS711, NCV711.9 V C T 1. nf R 1a 47 k R 1b 47 k R T 47 k 47 k f O = 1.5 khz Output Voltage Timing Capacitor Voltage.67 The noninverting input threshold levels are set so that the capacitor voltage oscillates between 1/3 and 2/3 of. This requires the resistors R 1a, R 1b and to be of equal value. The following formula can be used to approximate the output frequency. f O.33 1 1.39 R T C T Figure 34. Square Wave Oscillator 1. M cww cw 1 k 1 k D 1 1N4148 D 2 1N4148 Output Voltage Timing Capacitor Voltage.67.33 Clockwise, Low Duty Cycle C T 1. nf R 1a 47 k f O Output Voltage Timing Capacitor Voltage.67.33 CounterClockwise, High Duty Cycle R 1b 47 k 47 k The timing capacitor C T will charge through diode D 2 and discharge through diode D 1, allowing a variable duty cycle. The pulse width of the signal can be programmed by adjusting the value of the trimpot. The capacitor voltage will oscillate between 1/3 and 2/3 of, since all the resistors at the noninverting input are of equal value. Figure 35. Variable Duty Cycle Pulse Generator R 1 1. M 2.5 V C in 1 F 2.5 V R 3 1. k 1, F 1. M Ceff. R 1 R3 C in Figure 36. Positive Capacitance Multiplier 12
NCS711, NCV711 C f 4 pf A f R f 1 k f L f H V in 1 k C 1 8 nf R 1 1 k.9 V.9 V V O f L 1 2 R 1 C 1 2 Hz f H 1 2 R f C f 4. khz A f 1 R f 11 Figure 37. Voice Band Filter V supply V in I sink V in R sense R sense Figure 38. High Compliance Current Sink V L I s 5. V 1. R sense R 3 1. k R L R 1 1. k R 4 1. k V O R 5 I s V O 1. A 67.93 mv 2.4 k.5 A 78.67 mv 3.3 k For best performance, use low tolerance resistors. Figure 39. High Side Current Sense 13
NCS711, NCV711 k k R 1 V O il V S R1, Note that i L is independent of R L R 1 V S R L i L Figure 4. Current Source R 1 i S V O V O = i S R 1 Figure 41. Current to Voltage Converter V S i = R L i L R 1 i R1 V O ir1 il V R1 R1 V S R1 Figure 42. Voltage to Current Converter 14
NCS711, NCV711 V 1 V 2 R 1 R 3 R 4 V O VO V2 R4 R3 R4 R1 1 V1 R1 If R 1 = R 3, and = R 4, the equation simplifies to: VO (V2 V1) R1 Figure 43. Differential Amplifier R 4 V 2 V 1 V 2 R 1 R 3 V O VO R2 V 1 R1 V 2 R2 V 3 R3 R 5 To minimize input offset current take: R 5 = R 1 // // R 3 // R 4 Figure 44. Summing Amplifier 15
NCS711, NCV711 PACKAGE DIMENSIONS TSOP5 CASE 4832 ISSUE H 2X 2X NOTE 5.1 T.2 T L.5 5 4 1 2 3 H G A B C D 5X.2 C A B T S SEATING PLANE J K DETAIL Z M DETAIL Z SOLDERING FOOTPRINT* NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN.2 FROM BODY. MILLIMETERS DIM MIN MAX A 3. BSC B 1.5 BSC C.9 1.1 D.25.5 G.95 BSC H.1.1 J.1.26 K.2.6 L 1.25 1.55 M 1 S 2.5 3..95.37 1.9.74 2.4.94 1..39.7.28 SCALE 1:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: 336752175 or 8344386 Toll Free USA/Canada Fax: 336752176 or 83443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 82829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 79 291 Japan Customer Focus Center Phone: 813581715 16 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCS711/D