6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course

6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott

Wireless Systems Direct conversion architecture D/A A/D Digital Processing Block D/A sin(w o t) 90 o Power Amp LNA sin(w o t) 90 o A/D Digital Processing Block Transmit IC Receive IC Transmitter issues - Meeting the spectral mask (LO phase noise & feedthrough, quadrature accuracy), D/A accuracy, power amp linearity Receiver Issues - Meeting SNR (Noise figure, blocking performance, channel selectivity, LO phase noise, A/D nonlinearity and noise), selectivity (filtering), and emission requirements

Future Goals Low cost, low power, and small area solutions - New architectures and circuits! Increased spectral efficiency - Example: GSM cellphones (GMSK) to 8-PSK (Edge) Requires a linear power amplifier! Increased data rates - Example: 802.11b (11 Mb/s) to 802.11a (> 50 Mb/s) GFSK modulation changes to OFDM modulation Higher carrier frequencies - 802.11b (2.5 GHz) to 802.11a (5 GHz) to? (60 GHz) New modulation formats - GMSK, CDMA, OFDM, pulse position modulation New application areas

High Speed Data Links A common architecture Digital Processing Block MUX Driver Clock Generation 10 Gb/s Data Link Amp Clock and Data Recovery Clock Distribution DEMUX Digital Processing Block Transmit IC Receive IC Transmitter Issues - Intersymbol interference (limited bandwidth of IC amplifiers, packaging), clock jitter, power, area Receiver Issue - Intersymbol interference (same as above), jitter from clock and data recovery, power, area

Future Goals Low cost, low power, small area solutions - New architectures and circuits! Increased data rates - 40 Gb/s for optical (moving to 120 Gb/s!) Electronics is a limitation (optical issues getting significant) - > 5 Gb/s for backplane applications The channel (i.e., the PC board trace) is the limitation High frequency compensation/equalization - Higher data rates, lower bit error rates (BER), improved robustness in the face of varying conditions - How do you do this at GHz speeds? Multi-level modulation - Better spectral efficiency (more bits in given bandwidth)

This Class Circuit AND system focus - Knowing circuit design is not enough - Knowing system theory is not enough Circuit stuff - RF issues: transmission lines and impedance transformers - High speed design techniques - Basic building blocks: amplifiers, mixers, VCO s, digital components - Nonidealities: noise and nonlinearity System stuff - Macromodeling and simulation - Wireless and high speed data link principles - System level blocks: PLL s, CDR s, transceivers

The Goal Design at Circuit/System Level 1. Design architecture with analytical models May require new circuits guess what they look like 2. Verify architectural ideas by simulating with ideal macro-models of circuit blocks Guess macro-models for new circuits 3. Add known non-idealities of circuit blocks (nonlinearity, noise, offsets, etc.) Go back to 1. if the architecture breaks! 4. Design circuit blocks and get better macro-models Go back to 1. if you can t build the circuit! Go back to 1. if the architecture breaks! 5. Verify as much of system as possible with SPICE 6. Layout, extract, verify Do this soon for high speed systems - iteration likely!

Key System Level Simulation Needs You need a fast simulator - To design new things well, you must be able to iterate - The faster the simulation, the faster you can iterate You need to be able to add non-idealities in a controlled manner - Fundamental issues with architectures need to be separated from implementation issues An architecture that is fundamentally flawed should be quickly abandoned You need flexibility - Capable of implementing circuit blocks such as filters, VCO s, etc. - Capable of implementing algorithms - Arbitrary level of detail

A Custom C++ Simulator Will Be Used - CppSim Blocks are implemented with C/C++ code - High computation speed - Complex block descriptions Users enter designs in graphical form using Cadence schematic capture - System analysis and transistor level analysis in the same CAD framework Resulting signals are viewed in Matlab - Powerful post-processing and viewing capability Note: Hspice used for circuit level simulations CppSim is on Athena and freely downloadable at http://www-mtl.mit.edu/~perrott

A Quick Preview of Homeworks and Projects

HW1 Transmission Lines and Transformers High speed data link application: High Speed Trace (RF Connector to Chip Die) package Connector Adjoining pins die Controlled Impedance PCB trace Driving Source Two-Port Model On-Chip V in R o E i1 E r1 Delay = x Characteristic Impedance = R o Ideal Transmission Line C 1 L 1 C 2 E i2 E r2 R L V out

HW2 High Speed Amplifiers Broadband R 1 R 2 Vo+ V o- I bias V in+ M 1 M 2 V in- Narrowband M 3 M 4 I bias = 1mA L d V out M 3 5 kω 50 Ω L g M 2 C L =1pF C big x M 1 V in L s Z in

HW3 Amplifier Noise and Nonlinearity Amplifier circuit I bias R L V out 2 0.18 M 2 R T C big2 M 1 10 0.18 Model 50 Ω C big1 Noise Nonlinearity V in 50 Ω V out V in 50 Ω V out = c o + c 1 x + c 2 x 2 + c 3 x 3

HW4 Low Noise Amplifiers and Mixers Narrowband LNA I bias = 1mA L d 5 kω R pd V out M 3 C big M 2 C L =1pF R ps 50 Ω C big L g R pg M 1 Passive Mixer V in R ps R S /2 C big Z in L s V dd 0 LO C L LO V in V out R L /2 R L /2 V out LO 0 V LO V dd R S /2 C big 0

HW5 Voltage Controlled Oscillators Differential CMOS 1.8 V 100/0.18 M 3 M 4 100/0.18 C tune Colpitts V out V in V out 3 nh L d =4nH R d =10kΩ 50/0.18 0 V M 2 M 1 50/0.18 M 1 V out C 1 =2pF V bias =1.2V I bias =100 µa C 2 =8pF

Project 1 - High Speed Frequency Dividers High speed latches/registers High speed dual-modulus divider 2/3 OUT Load Load OUT IN 2/3 Core A 2 B 2 OUT CON * IN IN CON Control Qualifier Φ Φ 8 + CON Cycles IN A B OUT CON * CON

HW6 Phase Locked Loop Design T Integer-N synthesizer ref(t) PFD e(t) I cp Loop Filter vin(t) out(t) T VCO div(t) Divider N[k] = N nom Phase noise simulation S Φout (f) s 1 + s/(2πf p ) vin out t out(t) = cos(2π (f o +K v vin(τ))dτ) K 1 dbc/hz K 2 dbc -20 dbc/hz/dec v ph 2 v spur = Asin(2πf s t) 0 f s f p f offset

Project 2 GMSK Transmitter for Wireless Apps Reference Frequency (100 MHz) T PFD I cp Loop Filter H(s) vin(t) K v = 30 MHz/V f o = 900 MHz out(t) Power Amp RF Transmit Spectrum Trans. Noise N Limit Amp Q I 90 o 0 f RF f T d T Digital I/Q Generation T t t Data Generator Instantaneous Frequency Gaussian LPF Data Eye T d = t 1 1 MHz f inst K ph 1 - z -1 Peak-to-Peak Frequency Deviation Φ cos(φ) sin(φ) D/A D/A Includes Zero-Order Hold

Project 2 Accompanying Receiver Receiver Noise Received Spectrum f RF f Channel Select Filter Baseband Spectrum S(I R +jq R ) Trans. Noise f RF f N R Band Select Filter LNA cos(2πf RF t) sin(2πf RF t) I R 0 Modulation Signal f Receiver Noise Transmitter Noise Q R

Basics of Digital Communication

Example: A High Speed Backplane Data Link Suppose we consider packaging issues at the receiver side (ignore transmitter packaging now for simplicity) Transmitter 100 Ω 100 Ω V o+ I bias V in+ V in- M 1 M 2 Adjoining pins Controlled Impedance PCB trace Receiver package die M 3 M 4 V in Driving Source 100 Ω E i1 E r1 Ideal Transmission Line Two-Port Model Delay = 110 ps Characteristic Impedance = 50 Ω 0.5 pf 1 nh 0.5 pf E i2 E r2 On-Chip 55 Ω V out intentional mismatch unintentional mismatch

Modulation Format Binary, Non-Return to Zero (NRZ), Pulse Amplitude Modulation (PAM) - Send either a zero or one in a given time interval T d - Time interval set by a low jitter clock - Ideal signal from transmitter: 0.4 0.35 0.3 0.25 0.2 in 0.15 0.1 0.05 0 0.05 0 0.5 1 1.5 2 2.5 TIME x 10 8

Receiver Function Two operations - Recover clock and use it to sample data - Evaluate data to be 0 or 1 based on a slicer Detector Data Out Clock Recovery Recovered Clock Sampling Instant Slice Level Data Recovered Clock 0111 0 0 0 1 0 1 0 0 1 Out

Issue: PC Board Trace is Not an Ideal Channel Chip capacitance and inductance limits bandwidth Transmission line effects cause reflections in the presence of impedance mismatch Example: transmit at 1 Gb/s across link in previous slide (assume bondwire inductance is zero) - Signal at receiver termination resistor 0.4 0.35 0.3 0.25 0.2 out 0.15 0.1 0.05 0 0.05 0 0.5 1 1.5 2 2.5 TIME x 10 8

Eye Diagram for 1 Gb/s Data Rate Wrap signal back onto itself every 2*T d seconds - Same as an oscilloscope would do Allows immediate assessment of the quality of the signal at the receiver (look at eye opening) 0.4 Eye Diagram 0.35 0.3 0.25 0.2 out 0.15 0.1 0.05 0 0.05 0 0.2 0.4 0.6 0.8 1 Time (seconds) 1.2 1.4 1.6 1.8 2 x 10 9

Relationship of Eye to Sampling Time and Slice Level Horizontal portion of eye indicates sensitivity to timing jitter Vertical portion of eye indicates sensitivity to additional noise and ISI 0.4 Sampling Instant Eye Diagram 0.35 0.3 Slice Level 0.25 0.2 out 0.15 0.1 0.05 0 0.05 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Time (seconds) x 10 9

What Happens if We Increase the Data Rate? Limited bandwidth and reflections cause intersymbol interference (ISI) Eye diagram at 10 Gb/s for same data link 0.6 Eye Diagram 0.5 0.4 0.3 out 0.2 0.1 0 0.1 0 1 2 Time (seconds) x 10 10

What is the Impact of the Bondwire Inductance? Rule of thumb: 1 nh/mm for bondwire - Assume 1 nh Impact of inductance here increases bandwidth - less ISI occurs 0.6 Eye Diagram 0.5 0.4 0.3 out 0.2 0.1 0 0.1 0 1 Time (seconds) 2 x 10 10

How High of a Data Rate Can The Channel Support? Raise it to 25 Gb/s 0.6 Eye Diagram 0.5 0.4 0.3 out 0.2 0.1 0 0.1 0 2 4 Time (seconds) 6 8 x 10 11 However, we haven t considered other issues - PC board trace attenuates severely at high frequencies Bandwidth is < 5 GHz for 48 inch PC board trace (FR4)

Multi-Level Signaling Increase spectral efficiency by sending more than one bit during a symbol interval - Example: 4-Level PAM at 12.5 Gb/s on same channel Effective data rate: 25 Gb/s 0.5 Eye Diagram 0.4 0.3 0.2 out 0.1 0 0.1 0.2 0 0.2 0.4 0.6 0.8 Time (seconds) 1 1.2 1.4 1.6 x 10 10

How Else Can We Reduce ISI? Consider a system level view of the link - Channel can be viewed as having an equivalent frequency response Assumes linearity and time-invariance (accurate for most transmission line systems) Transmitter Receiver Channel Transmitter Driver Receiver Detector

Equalization Undo channel frequency response with an inverse filter at the receiver - Removes ISI! - Can make it adaptive to learn channel Transmitter Receiver Channel Equalization Transmitter Driver Receiver Detector

The Catch Equalization enhances noise - Overall SNR may be reduced Optimal approach is to make ISI and noise degradation about equal Transmitter Receiver Channel Noise Equalization Transmitter Driver Receiver Detector

Alternative Pre-emphasize at Transmitter Put inverse filter at transmitter instead of receiver - No enhancement of noise, but - Need feedback from receiver to learn channel - Requires higher dynamic range/power from transmitter Trransmitter Receiver Compensation (Pre-emphasis) Channel Noise Transmitter Driver Receiver Detector

Best Overall Performance Combine compensation and equalization - Starting to see this for high speed links Trransmitter Receiver Compensation (Pre-emphasis) Channel Noise Equalization Transmitter Driver Receiver Detector

What are the Issues with Wireless Systems? Noise - Need to extract the radio signal with sufficient SNR Selectivity (filtering, processing gain) - Need to remove interferers (which are often much larger!) Nonlinearity - Degrades transmit spectral mask - Degrades selectivity for receiver Multi-path (channel response) - Degrades signal nulls rather than ISI usually the issue - Can actually be used to advantage! We will look at BOTH broadband data links and wireless systems in this class