Frequency Agile RF Front End Transmitters Architecture for Software Defined Radio

Transcription

1 Frequency Agile RF Front End Transmitters Architecture for Software Defined Radio Patrick Roblin, Roberto Rojas, Mohammed Ismail 3 Sub-projects Mixed Signal Electronics Systems ElectroScience Laboratory Electrical & Computer Engineering The Ohio State University OSU NSF C1 Supplement: Volakis PI 2 year project (Au 07-Su 09) January 24 th & 25 th, Semi Annual Meeting Scottsdale, AZ Arizona State University University of Arizona University of Hawaii Rensselaer Polytechnic Institute The Ohio State University National Science Foundation Industry/University Cooperative Research Center

2 C1 SDR Group + Collaborators 3 students: Shashank Mutha Keum-su Song Xi Yang (1.5 supported by C1) 3 advisors: Patrick Roblin Mohammed Ismail Roberto Rojas C1 PI: Volakis PI Consultant: Dr. Chaillot, CEA 4 Leverage Students: Bou Sleiman, Khaled Obeidat & Bryan Raines

3 1 2 3 New SDR Architecture: To address issues of wide-bandwidth, linearity, power efficiency and frequency agile filtering we propose a programmable RF front end transceiver based on: 1. FPGA based Multi-band Predistortion Linearization 2. Poly-phase Up-converter: filter-less removal of spurious 3. Non-Foster Broadband Matching (an alternative to MEMS) Demo targeted: WiMAX

4 1 Predistortion Linearization 5 MHz Previous Work: Frequency Selective Predistorter for 2 band WCDMA: independently linearizes each band and their interactions (Roblin et al. IEEE Trans. On MTT, Jan 2008) MHz before linearization a c LSB linearization(in and interband) b d USB linearization(in and interband) USB and LSB linearization E e Inband A ina ina I in in I o o Hilbert Tranform I e e E o inb Inband B inb I o o I e e I in in inter Interband I out out inter DAC DAC LO RF PA

5 1 Targeted PD Linearization for 4 Bands Method: I in-band blocks 3 inter-band blocks + others Based on new power dependent Volterra theory! I 2 2 I 3 3 I 4 4 E in E in E in E in in1 in2 Inband Inband Inband in3 in4 Inband in1 i2 in3 in4 I o o inter1 inter2 inter3 Interband Interband Interband inter1 inter2 inter3 Imbedded NIOS processor Gain: Linearization bandwidth increased by factor 4 (4x100 MHz) Property: Topology compatible with memory polynomials Cost : 20 (4x4 + 3x2) complex coefficients (40 unknowns) Solution: Calibrated by an adaptative algorithm DAC DAC ADC ADC LO RF RF PA

6 1 MATLAB Simulation of Adaption Spectrum of I & EVM in dbm Adaptative removal of intermodulation st iter 2nd iter 3rd iter 4th iter Intermod removal In-band dist. removal 2 band MATLAB demo Frequency Bandwidth:20MHz Future Work: FPGA implementation of adaptation in 2/4 band predistorter 4 bands I OFD M Gen NIOS Predis -torter FPGA F F T I p d pd D A C I Mod I Demo d P A FPGA OFDM GUI

7 2 Improved Poly-phase Up-Converter Compared to: R. Shrestha et al. A Polyphase Multipath Technique for Software-Defined Radio Transmitters, IEEE Journal of Solid-State Circuits, Vol. 41, No. 12, Dec 2006, p Channel Poly-Phase Reduced number of IF inputs Multi-path baseband generated on chip Octa-Phase: Low noise sinusoidal differential LO Digital balance tuning Differential poly-phase multipath

8 2 Proposed 8 Channel I modulator Extended Gilbert-cell architecture Direct differential implementation RF LO signal crossing only one layer of transistors Octa-Phase LO: J. Kim & H. Yoo APMC 2005 Proc.

9 2 4 Channel Polyphase I modulator & Predistortion: OSU Demo LS IMD3 Image Band Desired Band LO Leakage US IMD3 SSB mixer Desired Band LO leakage Strongly non-linear I modulator! Before After Future Work: Design, fab and test of 8 channel polyphase modulator RFIC in TSMC 0.18 for WiMAX

10 3 Non-Foster Matching Networks PI: Roberto G. Rojas Goal: Design, build and test simple integrated (TSMC 0.18 µm) matching network using Non-Foster elements Key steps: Design of stable negative impedance converter (NIC) circuits for operation in the frequency range 2 to 6 GHz Implementation and testing of integrated matching network (MN) with NIC circuits Technical Details Foster Reactance Theorem : The slope of the reactance or susceptance versus frequency for a lossless one-port network is always positive. Non-Foster element : If a network device does not obey Foster Reactance theorem, then it is called Non-Foster element. Examples: Negative inductance/capacitance [1]. Non-Foster element can be realized by using Negative Impedance Converter (NIC). A NIC is an active network which has the property that a drivingpoint immittance at one terminal-pair is the negative of the load immittance connected to the other terminal-pair. Voltage inversion / Current inversion NIC. A NIC is potentially unstable because of positive feedback system. It is important to verify stability of NIC. Advantage of Non-Foster Elements in MN: Overcoming limitation of gain-bandwidth product. X ( ω) > 0 and ω Reactance B( ω) > 0 ω X ( ω) or B ( ω) Matching Network reactance 1 (C < 0) ω C Net reactance = 0 0 freq Capacitive reactance (Load) 1 (C > 0) ωc ω [1] S. E. Sussman-Fort, Matching Network Design Using Non-Foster Impedance, Int. Jour of RF and Microwave computer Aided Engineering, vol. 16, issue 2, Mar 2006,

11 3 NIC with Discrete Components NE68033(NPN BJT) spice model from NEC. V ce = 2.5 ~ 6V and I c = 0.3 ~ 20mA Frequency range = 0.05 ~ 3GHz Γ s Γ in Z L NIC [2-3] Z L = 10pF Port 1 = 50Ω Port 1 Z in -Z L < Z in > To be unconditionally stable circuit: Γ in < 1 ( Γ s < 1) Potentially unstable for freq > 2.98 GHz Limitations of NIC with discrete components : Do not work well in GHz range due to parasitics. 1GHz 0.5GHz < Γ in > [2] J. G. Linvill, Transistor Negative Impedance Converters, Proc. IRE, Vol. 41, June 1953, [3] James T. Aberle and Robert Loepsinger-Romak, Active Antenna with Non-Foster Matching Networks, San Francisco, Morgan and Claypool Publishers, 2007 < Relative Error >

12 3 NIC with TSMC 0.18 µm MOS Simulated previous NIC: TSMC 0.18µm MOSFET Size Width 1000*0.22 µm Length 1*0.18 µm Simulated frequency range = 0.5 ~ 10 GHz Integrated NIC: Decreases relative error between simulated and reference reactances. Future Work: Will simulate negative inductance. Improve stability (change topology if necessary). Implement and test simple integrated NIC circuit (L/C). Stable (0.5 ~ 10GHz) 0.5GHz < Z in > 3GHz < Γ in > < Relative Error >

13 1 2 3 Software Defined Radio Testbed Vector Signal Generator Analog Signal Generator Wideband Vector Signal Analyzer + Spectrum Analyzer Cascade RF Probe System -up to 60 GHz Mixed Signal Oscilloscope AFRL/NSF Non-Linear RF Lab (MISES, PI Roblin) Vector Network Analyzer NSF Integrated Wireless Communications Systems Laboratory (ESL, PI: Rojas)