WiSER: Dynamic Spectrum Access Platform and Infrastructure I. Seskar, D. Grunwald, K. Le, P. Maddala, D. Sicker, D. Raychaudhuri Rutgers, The State University of New Jersey University of Colorado, Boulder Contact: Ivan Seskar seskar (at) winlab (dot) rutgers (dot) edu
Cognitive Experiments at Scale ORBIT radio grid testbed currently supports ~10 USRP and ~32 USRP2 (GNU) radios, 100 low-cost spectrum sensors, WARP and GENI CR-Kit platforms Plan to reach ~64 cognitive radio nodes (Q4 2013) Suburban ORBIT Radio Grid 500 meters Office 20 meters Urban Current ORBIT sandbox with GNU radio 30 meters 300 meters Radio Mapping Concept for ORBIT Emulator 400-node Radio Grid Facility at Tech Center Programmable ORBIT radio node URSP CR board
Why (CRKIT) Framework? INNOVATION CYCLE Focus on Creativity, not Engineering Complexity : Split Baseband in two domain spaces : Dynamic Swappable Communication APPs (creative problem) Static - Open-sourced System-on-Chip (complex engineering problem) Abstract lower level design complexities from Users FSoC Features CRKIT = make real-time and widetuning radio a viable solution for large scale experiments. Live system runs Access to lower level resources thru APIs VITA radio transport protocol for radio control Networking capable node Support up to four dynamic APPs Library of Open-sourced Communication APPs Static Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7. Transparent to underlying FPGA technology. Can be ported to future HW platforms and newer FPGA technologies. WDR from Radio Technology Solutions
What is GENI CRKIT Framework? CRKIT HW Platform SW Platform ORBIT Integration Wideband Radio Flexible Baseband Embedded HOST PHY Layer Exp. Exp. Scalability FPGA- SoC Comm. APPs Radio APIs OMF Baseband Processor : FPGA-based off-the-shelf board Control up to 4 full-duplex wideband radios FPGA-based System-on-Chip (FSoC) implementation CRKIT baseband with 4 stacked radios Wideband Radio (WDR) Module : Baseband with 1 mounted radio Actual CogRadio with enclosure, 2 WDRs Wideband : tunable range 300MHz to 7.5GHz 25MHz bandwidth 50Msps 12-bit ADC, 200Msps 12-bit DAC 50us switch between frequencies
Spiral II GENI project: CR kit HW Wide-tuning Digital Radio (WDR) block diagram Range of baseband FPGA platforms 4 (2) configurable radio modules for phased or smart antenna applications with Phase I: Each module allows two 25 MHz bands from 300 to 6000 MHz Phase II: Each module allows two different 300 MHz bands from 100 to 7500 MHz Each module supports independent full duplex operation. 1 usec RF frequency switching time Switched antenna diversity for both TX and RX channels.n
CRKIT Programming Model Network HOST CRKIT Application development CRKIT development Java, C# C C GUI Algorithm Comm. APP Embedded SW System Debugging System Test CR DSA VHDL/ Verilog Mathworks Simulink IP Networking HW Configuration Host CMD Parsing DHCP/ARP Lookup Tables/ RF ETH/VITA
APP Development Flow MATLAB Simulink Flow APP Specification Design dynamic APP APP Validation PCORE boots Execute CRKIT Embedded SW CRKIT Flow Compile APP CRKIT Embedded SW 1. Get IP address using DHCP 2. Discover HOST 3. Configure CRKIT hardware 4. Parse HOST commands Link APP to Framework Host CMD Parsing HW Config. Networking Xilinx ISE Flow Compile Framework Generate FPGA bit file Download to Hardware Lookup Table Configuration dynamic Config. (ETH/VITA) initial config. RF Control
WiSER NSF CRI Project Use off-the-shelf hardware produced by commercial OEM vendors System integration with existing software components Community release of open-source software platform and related software radio design Tools including PHY/MAC hardware accelerators, spectrum measurement and protocol components. Reference implementation on two campuses of a multi-node dynamic spectrum access network
WiSER Baseline Hardware Zynq-7000 SoC / Analog Devices Software-Defined Radio Kit ZedBoard baseboard (Zynq XC7Z020 device) Dual-core ARM Cortex -A9 256 KB on-chip RAM Gigabit Ethernet, 2x SD/SDIO, USB,CAN, SPI, UART,I2C 512 MB DDR3, 256 Mb QSPI Flash 85K Logic Cells, 106K FF 220 Programmable DSP Slices (18x25 MACCs) Analog Devices FMC RF Front-end Software tunable across wide frequency range (400MHz to 4GHz) with 125MHz channel bandwidth (250MSPS ADC, 1GSPS DAC) RF section bypass for baseband sampling Phase and frequency synchronization on both transmit and receive paths
CRKit Phase II RF Front-end Dual full duplex operation 300-6000 MHz (bandwidths up to 500MHz). Transmitter: dual 16 bit 800MSps DAC, filtering, IQ modulator, RF filtering and power amplifier. Receiver: LNA, selectable RF filters, IQ demodulator and dual ADC (8 bits @ 1000 MSps or 12 bits @ 640 MSps) Features: +10dBm of output power, 50 µsec. frequency hop, carrier lock to internal or external reference, carrier phase adjust, 32 db gain adjust, carrier feedthru suppression and sideband balance adjustment. +10dBm of output power, 50 usec. frequency hop, carrier lock to internal or external reference, carrier phase adjust, 32 db gain adjust, carrier feedthru suppression and sideband balance adjustment.
WiSER HW Extensions 16-core (64-core) Adapteva processor hosted by the Zedboard motherboard, as shown below The Epiphany multi-core chip daughter card
Future Framework Architecture 1. Dual-core ARM processors Linux support Dual AXI bus architecture Independent Data and Control traffic 2. Independent APP sampling rates Support Multirate and Multi-APP systems Decoupling of APP clock domains from overall Framework. Permits Spectrum Sensing APP + Communication APP in same architecture 3. Applications Reuse previously designed APPs NC-OFDM Spectrum Sensing 4. RF 400MHz to 4GHz tuning range 125MHz Channel Bandwidth (250MSPS ADC, 1GSPS DAC) Full-duplex