RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London
RAPID PROTOTYPING OF DIGITAL SYSTEMS SECOND Table of Contents EDITION 1 Tutorial I: The 15 Minute Design 1.1 Design Entry using the Graphic Editor 1.2 Compiling the Design 1.3 Simulation of the Design 1.4 Downloading Your Design to the UP 1 or UP IX Board 1.5 The 10 Minute VHDL Entry Tutorial 1.6 Compiling the VHDL Design 1.7 The 10 Minute Verilog Entry Tutorial 1.8 Compiling the Verilog Design 1.9 Timing Analysis 1.10 The Floorplan Editor 1.11 Symbols and Hierarchy 1.12 Functional Simulation 1.13 For additional Information 1.14 Laboratory Exercises 2 The Altera UP 1 and UP IX CPLD Boards_ 2.1 Programming Jumpers 2.2 MAX 7000 Device and UP 1 I/O Features 2.3 MAX and FLEX Seven-segment LED Displays, 2.4 FLEX 10K Device and UP 1 I/O Features 2.5 Obtaining a UP 1 or UP IX Board and Power Supply 3 Programmahle Logic Technology 3.1 CPLDs and FPGAs 3.2 Altera MAX 7000S Architecture - A Product Term CPLD Device_ 3.3 Altera FLEX 10K Architecture - A Look-Up Table CPLD Device_ 3.4 Xilinx 4000 Architecture - A Look-Up Table FPGA Device.10.12.14.17.17.21.22.23.24.24.25 25 30.31.31.31.34 36 38.41.42.43 47
vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic 3.6 Next Generation FPLD CAD tools 3.7 Applications offplds 3.8 Features of New Generation FPLDs 3.9 For additional information 3.10 Laboratory Exercises 4 Tutorial II: Sequential Design and Hierarchy_ 4.1 Install the Tutorial Files and UPlcore Library 4.2 Open the tutor2 Schematic 4.3 Browse the Hierarchy 4.4 Using Buses in a Schematic 4.5 Testing the Pushbutton Counter and Displays 4.6 Testing the Initial Design on the UP 1 Board._ 4.7 Fixing the Switch Contact Bounce Problem 4.8 Testing the Modified Design on the UP 1 Board. 4.9 Laboratory Exercises 5 UPlcore Library Functions 5.1 UPlcore DEC_7SEG: Hex to Seven-segment Decoder 5.2 UPlcore Debounce: Pushbutton Debounce 5.3 UPlcore OnePulse: Pushbutton Single Pulse_ 5.4 UPlcore Clk Div: Clock Divider 5.5 UPlcore VGASync: VGA Video Sync Generation, 5.6 UPlcore CHAR ROM: Character Generation ROM 5.7 UPlcore Keyboard: Read Keyboard Scan Code 5.8 UPlcore Mouse: Mouse Cursor 6 Using VHDL for Synthesis of Digital Hardware 6.1 VHDL Data Types 6.2 VHDL Operators 6.3 VHDL Based Synthesis of Digital Hardware 6.4 VHDL Synthesis Models of Gate Networks _ 6.5 VHDL Synthesis Model of a Seven-segment LED Decoder 6.6 VHDL Synthesis Model of a Multiplexer 6.7 VHDL Synthesis Model of Tri-State Output
vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic 49 3.6 Next Generation FPLD CAD tools 50 3.7 Applications offplds 50 3.8 Features of New Generation FPLDs 50 3.9 For additional information 51 3.10 Laboratory Exercises 52 4 Tutorial II: Sequential Design and Hierarchy 54 4.1 Install the Tutorial Files and UPlcore Library 54 4.2 Open the tutor2 Schematic 54 4.3 Browse the Hierarchy 56 4.4 Using Buses in a Schematic 57 4.5 Testing the Pushbutton Counter and Displays 58 4.6 Testing the Initial Design on the UP 1 Board. 59 4.7 Fixing the Switch Contact Bounce Problem 60 4.8 Testing the Modified Design on the UP 1 Board. 61 4.9 Laboratory Exercises 61 5 UPlcore Library Functions 66 5.1 UPlcore DEC_7SEG: Hex to Seven-segment Decoder 67 5.2 UPlcore Debounce: Pushbutton Debounce 68 5.3 UPlcore OnePulse: Pushbutton Single Pulse 69 5.4 UPlcore Clk_Div: Clock Divider 70 5.5 UPlcore VGASync: VGA Video Sync Generation 71 5.6 UPlcore CHAR ROM: Character Generation ROM 73 5.7 UPlcore Keyboard: Read Keyboard Scan Code 74 5.8 UPlcore Mouse: Mouse Cursor 75 6 Using VHDL for Synthesis of Digital Hardware 78 6.1 VHDL Data Types 78 6.2 VHDL Operators 79 6.3 VHDL Based Synthesis of Digital Hardware 80 6.4 VHDL Synthesis Models of Gate Networks 80 6.5 VHDL Synthesis Model of a Seven-segment LED Decoder 81 6.6 VHDL Synthesis Model of a Multiplexer 83 6.7 VHDL Synthesis Model of Tri-State Output 84
Table of Contents VII 6.8 VHDL Synthesis Models of Flip-flops and Registers 84 6.9 Accidental Synthesis of Inferred Latches 86 6.10 VHDL Synthesis Model of a Counter 86 6.11 VHDL Synthesis Model of a State Machine 87 6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter 89 6.13 VHDL Synthesis of Multiply and Divide Hardware 90 6.14 VHDL Synthesis Models for Memory 91 6.15 Hierarchy in VHDL Synthesis Models 94 6.16 Using a Testbench for Verification 96 6.17 For additional information 97 6.18 Laboratory Exercises 97 7 State Machine Design: The Electric Train Controller 102 7.1 The Train Control Problem 102 7.2 Track Power (Tl, T2, T3, and T4) 104 7.3 Track Direction (DA1-DA0, and DB1-DB0) 104 7.4 Switch Direction (SW1, SW2, and SW3) 105 7.5 Train Sensor Input Signals (Sl, S2, S3, S4, and S5) 105 7.6 An Example Controller Design 106 7.7 VHDL Based Example Controller Design 110 7.8 Simulation Vector file for State Machine Simulation 112 7.9 Running the Train Control Simulation 115 7.10 Running the Video Train System (After SuccessfuI Simulation) 116 7.11 Laboratory Exercises 117 8 A Simple Computer Design: The /JP 1 122 8.1 Computer Programs and Instructions 123 8.2 The Processor Fetch, Decode and Execute Cycle 124 8.3 VHDL Model of the np 1 131 8.4 Simulation of the npl Computer 134 8.5 Laboratory Exercises 135 9 VGA Video Display Generation 140 9.1 Video Display Technology 140 9.2 Video Refresh 140 9.3 Using a CPLD for VGA Video Signal Generation 143
VIII Rapid Prototyping of Digital Systems 9.4 A VHDL Sync Generation Example: UPlcore VGA SYNC 144 9.5 Final Output Register for Video Signals 146 9.6 Required Pin Assignments for Video Output 146 9.7 Video Examples 147 9.8 A Character Based Video Design 147 9.9 Character Selection and Fonts 148 9.10 VHDL Character Display Design Examples 151 9.11 A Graphics Memory Design Example 153 9.12 Video Data Compression 154 9.13 Video Color Mixing using Dithering 155 9.14 VHDL Graphics Display Design Example 155 9.15 Laboratory Exercises 157 10 Communications: Interfacing to the PS/2 Keyboard 160 10.1 PS/2 Port Connections 160 10.2 Keyboard Scan Codes 161 10.3 Make and Break Codes 161 10.4 The PS/2 Serial Data Transmission Protocol 161 10.5 Scan Code Set 2 for the PS/2 Keyboard 164 10.6 The Keyboard UPlcore 166 10.7 A Design Example Using the Keyboard UPlcore 169 10.8 For Additional Information 170 10.9 Laboratory Exercises 170 11 Communications: Interfacing to the PS/2 Mouse 172 11.1 The Mouse UPlcore 174 11.2 Mouse Initialization 174 11.3 Mouse Data Packet Processing 175 11.4 An Example Design Using the Mouse UPlcore 176 11.5 For Additional Information 176 11.6 Laboratory Exercises 176 12 Robotics: The UPI-bot 178 12.1 The UPl-bot Design 178 12.2 UPl-bot Servo Drive Motors 178 12.3 Modifying the Servos to make Drive Motors 179
Table of Contents ix 12.4 VHDL Servo Driver Code for the UPl-bot 12.5 Sensors for the UPl-bot 12.6 Assembly of the UPl-bot Body 12.7 UPl-bot FLEX Expansion B Header Pins 12.8 An Alternative UP 1 Robot Pro.ject Based on an R/C Car 12.9 For Additional Information 12.10 Laboratory Exercises 13 A RISC Design: Synthesis ofthe MIPS Processor Core 13.1 The MIPS Instruction Set and Processor 13.2 Using VHDL to Synthesize the MIPS Processor Core 13.3 The Top-Level Module 13.4 The Control Unit 13.5 The Instruction Fetch Stage 13.6 The Decode Stage 13.7 The Execute Stage 13.8 The Data Memory Stage 13.9 Simulation of the MIPS Design 13.10 MIPS Hardware Implementation on the UP 1 or UP IX Board 13.11 For Additional Information 13.12 Laboratory Exercises Appendix A: Generation ofpseudo Random Binary Sequences Appendix B: MAX+PLUS II Design and Data File Extensions Appendix C: UP 1 and UP IX Pin Assignments Appendix D: The Wintim Meta Assembler Appendix E: An Introduction to Verilog for VHDL users Glossarv Index About the Accompanying CD-ROM 180 182 190 197 198 203 204 210 210 213 214 217 219 222 224 226 227 228 229 230 235 237 239 243 252 259 267 270