Breaking through Fixed PUF Block Limitations with Differential Sequence Coding and Convolutional Codes 04/11/2013
|
|
- Archibald Stephens
- 8 years ago
- Views:
Transcription
1 Matthias Hiller, Michael Weiner, Leandro Rodrigues Lima, Maximilian Birkner and Georg Sigl Breaking through Fixed PUF Block Limitations with Differential Sequence Coding and Convolutional Codes International Workshop on Trustworthy Embedded Devices (TrustED)
2 Outline Introduction Differential Sequence Coding Convolutional Codes DSC + Conv Code Fuzzy Extractor Conclusions Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 2
3 Introduction: PUFs Example: SRAM PUF (Guajardo et al. CHES 2007) Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 3
4 Introduction: Syndrome Coding Secret Key = f (Secret PUF Response, Public Helper Data) Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 4
5 Introduction: Need for Error Correction 520 Bit Secret Reproduction with 15% Bit Error Probability Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 5
6 Introduction: Key Storage with PUFs Generation: Reproduction: Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 6
7 Introduction: State of the Art Fixed blocks sizes for all existing syndrome coding schemes Reliability of the blocks varies Unreliable blocks will lead to errors that cannot be compensated by more reliable blocks Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 7
8 Introduction: State of the Art Goal: one white and one black square in each block of four E.g. required for IBS (Yu and Devadas, 2010) Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 8
9 Introduction: Motivation Law of Large Numbers: We can predict the number of reliable PUF outputs in a long sequence with a high precision. Implementation: Search the long sequence sequentially. Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 9
10 Outline Introduction Differential Sequence Coding Convolutional Codes DSC + Conv Code Fuzzy Exctractor Conclusions Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 10
11 Differential Sequence Coding Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 11
12 Design Criteria Output Error Probability PUF Size Helper Data Size Implem. Complexity Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 12
13 DSC Performance Example: 4 PUF Outputs per Key Bit Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 13
14 Outline Introduction Differential Sequence Coding Convolutional Codes DSC + Conv Code Fuzzy Exctractor Conclusions Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 14
15 Convolutional Codes Highly structured codes Efficient decoding algorithms Suitable for lightweight hardware implemenation Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 15
16 Fuzzy Extractor Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 16
17 Fuzzy Extractor: Performance Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 17
18 Fuzzy Extractor: Spartan 3E Hardw. Impl. PUF Output Bits Helper Data Bits Slices Block RAM Bits Clock Cycles CO + Golay (Bösch et al., 2008) CO + RM (Maes et al., 2009) C-IBS + RM (Hiller et al., 2012) 3,696 3,824 > > 24,024 1,536 13, ,768 10,298 2,304 9, DSC + Conv Code 1,224 2, ,264 30,846 + Hash Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 18
19 Conclusions Differential Sequence Coding High reliability Convolutional Codes Hardware efficient decoder Fuzzy Extractor: Robust against helper data manipulation Most efficient FPGA hardware implementation for SRAM PUF Breaking Through Fixed PUF Block Limitations with DSC and Conv Codes 19
Secure Embedded Systems eine Voraussetzung für Cyber Physical Systems und das Internet der Dinge
Secure Embedded Systems eine Voraussetzung für Cyber Physical Systems und das Internet der Dinge Mitgliederversammlung EIKON e.v. 26. Februar 2014 Prof. Dr.-Ing. Georg Sigl Lehrstuhl für Sicherheit in
More informationLightweight and Secure PUF Key Storage Using Limits of Machine Learning
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning Meng-Day (Mandel) Yu 1, David M Raïhi 1, Richard Sowell 1, Srinivas Devadas 2 1 Verayo, Inc., San Jose, CA, USA 2 MIT, Cambridge,
More informationQuality Limitations on the Extraction of a PUF-based Cryptographic Key
Quality Limitations on the Extraction of a PUF-based Cryptographic Key Sandra L. Lattacher, TECHNIKON Forschungs- und Planungsgesellschaft mbh Joint work with Martin Deutschmann, Michael Höberl, Christina
More informationLogically Reconfigurable PUFs: Memory-Based Secure Key Storage
Logically Reconfigurable PUFs: Memory-Based Secure Key Storage Ilze Eichhorn Intrinsic-ID High Tech Campus 9 Eindhoven, The Netherlands ilze.eichhorn@ intrinsic-id.com Patrick Koeberl Intel Ireland Collinstown
More informationAnti-Counterfeiting with Hardware Intrinsic Security
Anti-Counterfeiting with Hardware Intrinsic Security Vincent van der Leest and Pim Tuyls Intrinsic-ID, Eindhoven, The Netherlands http://www.intrinsic-id.com Abstract Counterfeiting of goods and electronic
More informationFinal Report on Prototype Testing
.. D1.2: Final Report on Prototype Testing Project number: 835932 Project acronym: CODES Project title: Algorithmic extraction and error-correction codes for lightweight security anchors with reconfigurable
More informationPUFKY: A Fully Functional PUF-based Cryptographic Key Generator
PUFKY: A Fully Functional PUF-based Cryptographic Key Generator Roel Maes, Anthony Van Herrewege, Ingrid Verbauwhede KU Leuven Dept. Electrical Engineering-ESAT/SCD-COSIC and IBBT Kasteelpark Arenberg
More informationOffline HW/SW Authentication for Reconfigurable Platforms
Offline HW/SW Authentication for Reconfigurable Platforms Eric Simpson Virginia Tech esimpson@vt.edu Patrick Schaumont Virginia Tech schaum@vt.edu Abstract Many Field-Programmable Gate Array (FPGA) based
More informationDRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification
DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification Daniel E. Holcomb UC Berkeley Mastooreh Salajegheh UMass Amherst Kevin Fu UMass Amherst Amir Rahmati UMass Amherst
More informationHow To Fix A 3 Bit Error In Data From A Data Point To A Bit Code (Data Point) With A Power Source (Data Source) And A Power Cell (Power Source)
FPGA IMPLEMENTATION OF 4D-PARITY BASED DATA CODING TECHNIQUE Vijay Tawar 1, Rajani Gupta 2 1 Student, KNPCST, Hoshangabad Road, Misrod, Bhopal, Pin no.462047 2 Head of Department (EC), KNPCST, Hoshangabad
More informationVideo Conference System
CSEE 4840: Embedded Systems Spring 2009 Video Conference System Manish Sinha Srikanth Vemula Project Overview Top frame of screen will contain the local video Bottom frame will contain the network video
More informationVHDL DESIGN OF EDUCATIONAL, MODERN AND OPEN- ARCHITECTURE CPU
VHDL DESIGN OF EDUCATIONAL, MODERN AND OPEN- ARCHITECTURE CPU Martin Straka Doctoral Degree Programme (1), FIT BUT E-mail: strakam@fit.vutbr.cz Supervised by: Zdeněk Kotásek E-mail: kotasek@fit.vutbr.cz
More informationHorst Görtz Institute for IT-Security
Horst Görtz Institute for IT-Security On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks Extracting Keys from Xilinx Virtex-II FPGAs Amir Moradi, Alessandro Barenghi, Timo
More informationSide Channel Analysis and Embedded Systems Impact and Countermeasures
Side Channel Analysis and Embedded Systems Impact and Countermeasures Job de Haas Agenda Advances in Embedded Systems Security From USB stick to game console Current attacks Cryptographic devices Side
More informationAN RC4 BASED LIGHT WEIGHT SECURE PROTOCOL FOR SENSOR NETWORKS
AN RC4 BASED LIGHT WEIGHT SECURE PROTOCOL FOR SENSOR NETWORKS Chang N. Zhang and Qian Yu Department of Computer Science, University of Regina 3737 Wascana Parkway, Regina, SK S4S 0A2 Canada {zhang, yu209}@cs.uregina.ca
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More information40G MACsec Encryption in an FPGA
40G MACsec Encryption in an FPGA Dr Tom Kean, Managing Director, Algotronix Ltd, 130-10 Calton Road, Edinburgh EH8 8JQ United Kingdom Tel: +44 131 556 9242 Email: tom@algotronix.com February 2012 1 MACsec
More informationNon-Data Aided Carrier Offset Compensation for SDR Implementation
Non-Data Aided Carrier Offset Compensation for SDR Implementation Anders Riis Jensen 1, Niels Terp Kjeldgaard Jørgensen 1 Kim Laugesen 1, Yannick Le Moullec 1,2 1 Department of Electronic Systems, 2 Center
More informationDAC Digital To Analog Converter
DAC Digital To Analog Converter DAC Digital To Analog Converter Highlights XMC4000 provides two digital to analog converters. Each can output one analog value. Additional multiple analog waves can be generated
More informationContents. System Development Models and Methods. Design Abstraction and Views. Synthesis. Control/Data-Flow Models. System Synthesis Models
System Development Models and Methods Dipl.-Inf. Mirko Caspar Version: 10.02.L.r-1.0-100929 Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis
More informationAll Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
More informationHardware Intrinsic Security to Protect Value in the Mobile Market
Hardware Intrinsic Security to Protect Value in the Mobile Market Vincent van der Leest Roel Maes Geert-Jan Schrijen Pim Tuyls Intrinsic-ID { vincent.van.der.leest roel.maes geert.jan.schrijen pim.tuyls
More informationMemory Testing. Memory testing.1
Memory Testing Introduction Memory Architecture & Fault Models Test Algorithms DC / AC / Dynamic Tests Built-in Self Testing Schemes Built-in Self Repair Schemes Memory testing.1 Memory Market Share in
More informationTimer Value IRQ IACK
Real Time Clocks & s Programming with Real-time clocks Real-time clock is just another source of interrupts. Should have high priority in real-time systems Timing jitter must be accommodated or tolerated
More informationHardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner
Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations
More informationWhat Types of ECC Should Be Used on Flash Memory?
What Types of ECC Should Be Used on Flash Memory? Application 1. Abstract NOR Flash normally does not need ECC (Error-Correcting Code). On the other hand, NAND requires ECC to ensure data integrity. NAND
More informationArchitekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen. Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik
Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik Contents Überblick: Aufbau moderner FPGA Einblick: Eigenschaften
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationRAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
More informationTechnical Bulletin. Enabling Arista Advanced Monitoring. Overview
Technical Bulletin Enabling Arista Advanced Monitoring Overview Highlights: Independent observation networks are costly and can t keep pace with the production network speed increase EOS eapi allows programmatic
More informationSecure My-d TM and Mifare TM RFID reader system by using a security access module Erich Englbrecht (info@eonline.de) V0.1draft
Application Report Secure My-d TM and Mifare TM RFID reader system by using a security access module Erich Englbrecht (info@eonline.de) V0.1draft Embedded RF ABSTRACT This application report describes
More informationDevelopment of a Research-oriented Wireless System for Human Performance Monitoring
Development of a Research-oriented Wireless System for Human Performance Monitoring by Jonathan Hill ECE Dept., Univ. of Hartford jmhill@hartford.edu Majdi Atallah ECE Dept., Univ. of Hartford atallah@hartford.edu
More informationSteganographyinaVideoConferencingSystem? AndreasWestfeld1andGrittaWolf2 2InstituteforOperatingSystems,DatabasesandComputerNetworks 1InstituteforTheoreticalComputerScience DresdenUniversityofTechnology
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT
216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,
More informationOptimising the resource utilisation in high-speed network intrusion detection systems.
Optimising the resource utilisation in high-speed network intrusion detection systems. Gerald Tripp www.kent.ac.uk Network intrusion detection Network intrusion detection systems are provided to detect
More informationTo order copies of this booklet, please write to Corporate Communications, Bosch Limited. 09/12
More information
Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationEfficient Software Implementation of AES on 32-bit Platforms
Efficient Software Implementation of AES on 32-bit Platforms Guido Bertoni, Luca Breveglieri Politecnico di Milano, Milano - Italy Pasqualina Lilli Lilli Fragneto AST-LAB of ST Microelectronics, Agrate
More informationComputer Performance. Topic 3. Contents. Prerequisite knowledge Before studying this topic you should be able to:
55 Topic 3 Computer Performance Contents 3.1 Introduction...................................... 56 3.2 Measuring performance............................... 56 3.2.1 Clock Speed.................................
More informationReviving smart card analysis
Reviving smart card analysis Christopher Tarnovsky Karsten Nohl chris@flylogic.net nohl@srlabs.de Executive summary Modern smart cards should be analyzed 1. Smart card chips provide the trust base for
More informationEasy H.264 video streaming with Freescale's i.mx27 and Linux
Libre Software Meeting 2009 Easy H.264 video streaming with Freescale's i.mx27 and Linux July 8th 2009 LSM, Nantes: Easy H.264 video streaming with i.mx27 and Linux 1 Presentation plan 1) i.mx27 & H.264
More informationMultiagent Reputation Management to Achieve Robust Software Using Redundancy
Multiagent Reputation Management to Achieve Robust Software Using Redundancy Rajesh Turlapati and Michael N. Huhns Center for Information Technology, University of South Carolina Columbia, SC 29208 {turlapat,huhns}@engr.sc.edu
More informationCSE2102 Digital Design II - Topics CSE2102 - Digital Design II
CSE2102 Digital Design II - Topics CSE2102 - Digital Design II 6 - Microprocessor Interfacing - Memory and Peripheral Dr. Tim Ferguson, Monash University. AUSTRALIA. Tel: +61-3-99053227 FAX: +61-3-99053574
More informationRfid Authentication Protocol for security and privacy Maintenance in Cloud Based Employee Management System
Rfid Authentication Protocol for security and privacy Maintenance in Cloud Based Employee Management System ArchanaThange Post Graduate Student, DKGOI s COE, Swami Chincholi, Maharashtra, India archanathange7575@gmail.com,
More informationImplementation of Canny Edge Detector of color images on CELL/B.E. Architecture.
Implementation of Canny Edge Detector of color images on CELL/B.E. Architecture. Chirag Gupta,Sumod Mohan K cgupta@clemson.edu, sumodm@clemson.edu Abstract In this project we propose a method to improve
More informationStreaming Lossless Data Compression Algorithm (SLDC)
Standard ECMA-321 June 2001 Standardizing Information and Communication Systems Streaming Lossless Data Compression Algorithm (SLDC) Phone: +41 22 849.60.00 - Fax: +41 22 849.60.01 - URL: http://www.ecma.ch
More informationInternational Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research)
International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) ISSN (Print): 2279-0020 ISSN (Online): 2279-0039 International
More informationDDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2
More informationTriathlon of Lightweight Block Ciphers for the Internet of Things
NIST Lightweight Cryptography Workshop 2015 Triathlon of Lightweight Block Ciphers for the Internet of Things Daniel Dinu, Yann Le Corre, Dmitry Khovratovich, Leo Perrin, Johann Großschädl, Alex Biryukov
More informationTo design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationCrypto- Authentication. High Level Security Models Application Note. Description 1. SHA-256
Description This application note discusses at a high level the security models one might use with the CryptoAuthentication family of devices. The security models support the usage models presented in
More informationWhich ARM Cortex Core Is Right for Your Application: A, R or M?
Which ARM Cortex Core Is Right for Your Application: A, R or M? Introduction The ARM Cortex series of cores encompasses a very wide range of scalable performance options offering designers a great deal
More informationTechnical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview
Technical Note TN-29-06: NAND Flash Controller on Spartan-3 Overview Micron NAND Flash Controller via Xilinx Spartan -3 FPGA Overview As mobile product capabilities continue to expand, so does the demand
More informationPerformance Evaluation of AES using Hardware and Software Codesign
Performance Evaluation of AES using Hardware and Software Codesign Vilas V Deotare 1, Dinesh V Padole 2 Ashok S. Wakode 3 Research Scholar,Professor, GHRCE, Nagpur, India vilasdeotare@gmail.com 1, dvpadole@gmail.com
More informationNetwork Security Technology Network Management
COMPUTER NETWORKS Network Security Technology Network Management Source Encryption E(K,P) Decryption D(K,C) Destination The author of these slides is Dr. Mark Pullen of George Mason University. Permission
More informationModeling SRAM Start-Up Behavior for Physical Unclonable Functions
Modeling SRAM Start-Up Behavior for Physical Unclonable Functions Mafalda Cortez Apurva Dargar Said Hamdioui Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4, 2628 CD Delft,
More informationKS3 Computing Group 1 Programme of Study 2015 2016 2 hours per week
1 07/09/15 2 14/09/15 3 21/09/15 4 28/09/15 Communication and Networks esafety Obtains content from the World Wide Web using a web browser. Understands the importance of communicating safely and respectfully
More informationSafer data transmission using Steganography
Safer data transmission using Steganography Arul Bharathi, B.K.Akshay, M.Priy a, K.Latha Department of Computer Science and Engineering Sri Sairam Engineering College Chennai, India Email: arul.bharathi@yahoo.com,
More informationHomework # 2. Solutions. 4.1 What are the differences among sequential access, direct access, and random access?
ECE337 / CS341, Fall 2005 Introduction to Computer Architecture and Organization Instructor: Victor Manuel Murray Herrera Date assigned: 09/19/05, 05:00 PM Due back: 09/30/05, 8:00 AM Homework # 2 Solutions
More informationTECHNOLOGY BRIEF. Compaq RAID on a Chip Technology EXECUTIVE SUMMARY CONTENTS
TECHNOLOGY BRIEF August 1999 Compaq Computer Corporation Prepared by ISSD Technology Communications CONTENTS Executive Summary 1 Introduction 3 Subsystem Technology 3 Processor 3 SCSI Chip4 PCI Bridge
More informationArchitectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More informationSoftware Hardware Binding with Quiddikey
Software Hardware Binding with Quiddikey Mass scale solution against software piracy Secure your digital life Software-Hardware Binding solutions are typically required for Flash-based systems in which
More informationKhalid Sayood and Martin C. Rost Department of Electrical Engineering University of Nebraska
PROBLEM STATEMENT A ROBUST COMPRESSION SYSTEM FOR LOW BIT RATE TELEMETRY - TEST RESULTS WITH LUNAR DATA Khalid Sayood and Martin C. Rost Department of Electrical Engineering University of Nebraska The
More informationPUF Physical Unclonable Functions
Physical Unclonable Functions Protecting next-generation Smart Card ICs with SRAM-based s The use of Smart Card ICs has become more widespread, having expanded from historical banking and telecommunication
More informationMemory Basics. SRAM/DRAM Basics
Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for
More informationInstructional Design Framework CSE: Unit 1 Lesson 1
Instructional Design Framework Stage 1 Stage 2 Stage 3 If the desired end result is for learners to then you need evidence of the learners ability to then the learning events need to. Stage 1 Desired Results
More informationDigital Signal Controller Based Automatic Transfer Switch
Digital Signal Controller Based Automatic Transfer Switch by Venkat Anant Senior Staff Applications Engineer Freescale Semiconductor, Inc. Abstract: An automatic transfer switch (ATS) enables backup generators,
More informationChapter 7 Memory and Programmable Logic
NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array
More informationSecure Cloud Storage and Computing Using Reconfigurable Hardware
Secure Cloud Storage and Computing Using Reconfigurable Hardware Victor Costan, Brandon Cho, Srini Devadas Motivation Computing is more cost-efficient in public clouds but what about security? Cloud Applications
More informationIntroduction to Computer Security
Introduction to Computer Security Hash Functions and Digital Signatures Pavel Laskov Wilhelm Schickard Institute for Computer Science Integrity objective in a wide sense Reliability Transmission errors
More informationCoding and decoding with convolutional codes. The Viterbi Algor
Coding and decoding with convolutional codes. The Viterbi Algorithm. 8 Block codes: main ideas Principles st point of view: infinite length block code nd point of view: convolutions Some examples Repetition
More informationSDLC Controller. Documentation. Design File Formats. Verification
January 15, 2004 Product Specification 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features AllianceCORE
More informationNAND Flash FAQ. Eureka Technology. apn5_87. NAND Flash FAQ
What is NAND Flash? What is the major difference between NAND Flash and other Memory? Structural differences between NAND Flash and NOR Flash What does NAND Flash controller do? How to send command to
More informationSECURE IMPLEMENTATIONS OF CONTENT PROTECTION (DRM) SCHEMES ON CONSUMER ELECTRONIC DEVICES
SECURE IMPLEMENTATIONS OF CONTENT PROTECTION (DRM) SCHEMES ON CONSUMER ELECTRONIC DEVICES Contents Introduction... 3 DRM Threat Model... 3 DRM Flow... 4 DRM Assets... 5 Threat Model... 5 Protection of
More informationAccelerate Cloud Computing with the Xilinx Zynq SoC
X C E L L E N C E I N N E W A P P L I C AT I O N S Accelerate Cloud Computing with the Xilinx Zynq SoC A novel reconfigurable hardware accelerator speeds the processing of applications based on the MapReduce
More informationMemory Systems. Static Random Access Memory (SRAM) Cell
Memory Systems This chapter begins the discussion of memory systems from the implementation of a single bit. The architecture of memory chips is then constructed using arrays of bit implementations coupled
More informationSecond Level Authentication Using QR Codes
International Journal of Computer and Internet Security. ISSN 0974-2247 Volume 5, Number 2 (2013), pp. 43-50 International Research Publication House http://www.irphouse.com Second Level Authentication
More informationMaritime HMI - S Line.
Maritime HMI - S Line. 9,65 cm (3,8 II ) FSTN (Mono) / LED (white) 14,48 cm (5,7 II ) FSTN (Mono) / LED (white) 14,48 cm (5,7 II ) TFT (colour) / LED (white) 5 Shades of grey 5 Shades of grey 256 320 x
More informationATMEL FPGA 3rd User Group Workshop. 2010, 3rd June Christophe POURRIER
ATMEL FPGA 3rd User Group Workshop 2010, 3rd June Christophe POURRIER Summary Sodern first experience with AT40K Megha-Tropiques Project PHARAO Project ATF280 Evaluation Tests performed on the first development
More informationTesting Framework for estream Profile II Candidates
Testing Framework for estream Profile II Candidates L. Batina 1, S. Kumar 2, J. Lano 1, K. Lemke 2, N. Mentens 1, C. Paar 2, B. Preneel 1, K. Sakiyama 1 and I. Verbauwhede 1 1 Katholieke Universiteit Leuven,
More informationDesign and Implementation of Vending Machine using Verilog HDL
2011 2nd International Conference on Networking and Information Technology IPCSIT vol.17 (2011) (2011) IACSIT Press, Singapore Design and Implementation of Vending Machine using Verilog HDL Muhammad Ali
More informationEmbedded Software development Process and Tools: Lesson-4 Linking and Locating Software
Embedded Software development Process and Tools: Lesson-4 Linking and Locating Software 1 1. Linker 2 Linker Links the compiled codes of application software, object codes from library and OS kernel functions.
More informationIntroduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC 433 - Spring 2013
Introduction to Xilinx System Generator Part II Evan Everett and Michael Wu ELEC 433 - Spring 2013 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point data representation
More informationCSC 774 Advanced Network Security. Outline. Related Work
CC 77 Advanced Network ecurity Topic 6.3 ecure and Resilient Time ynchronization in Wireless ensor Networks 1 Outline Background of Wireless ensor Networks Related Work TinyeRync: ecure and Resilient Time
More informationA Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number
A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number 1 Tomohiro KAMIMURA, 2 Akinori KANASUGI 1 Department of Electronics, Tokyo Denki University, 07ee055@ms.dendai.ac.jp
More informationBinary Number System. 16. Binary Numbers. Base 10 digits: 0 1 2 3 4 5 6 7 8 9. Base 2 digits: 0 1
Binary Number System 1 Base 10 digits: 0 1 2 3 4 5 6 7 8 9 Base 2 digits: 0 1 Recall that in base 10, the digits of a number are just coefficients of powers of the base (10): 417 = 4 * 10 2 + 1 * 10 1
More informationTHE KEY TO DATA SECURITY
Secure Correspondence and File Sharing Zero-Knowledge Client-Side Encryption THE KEY TO DATA SECURITY TitanFile provides the highest level of security without compromising efficiency or ease of use. Securing
More informationMemory unit. 2 k words. n bits per word
9- k address lines Read n data input lines Memory unit 2 k words n bits per word n data output lines 24 Pearson Education, Inc M Morris Mano & Charles R Kime 9-2 Memory address Binary Decimal Memory contents
More informationHardware Implementation of AES Encryption and Decryption System Based on FPGA
Send Orders for Reprints to reprints@benthamscience.ae The Open Cybernetics & Systemics Journal, 2015, 9, 1373-1377 1373 Open Access Hardware Implementation of AES Encryption and Decryption System Based
More informationInternational Journal of Advancements in Research & Technology, Volume 2, Issue3, March -2013 1 ISSN 2278-7763
International Journal of Advancements in Research & Technology, Volume 2, Issue3, March -2013 1 FPGA IMPLEMENTATION OF HARDWARE TASK MANAGEMENT STRATEGIES Assistant professor Sharan Kumar Electronics Department
More informationReconfigurable System-on-Chip Design
Reconfigurable System-on-Chip Design MITCHELL MYJAK Senior Research Engineer Pacific Northwest National Laboratory PNNL-SA-93202 31 January 2013 1 About Me Biography BSEE, University of Portland, 2002
More informationSystolic Computing. Fundamentals
Systolic Computing Fundamentals Motivations for Systolic Processing PARALLEL ALGORITHMS WHICH MODEL OF COMPUTATION IS THE BETTER TO USE? HOW MUCH TIME WE EXPECT TO SAVE USING A PARALLEL ALGORITHM? HOW
More informationFighting product clones through digital signatures
Paul Curtis, Katrin Berkenkopf Embedded Experts Team, SEGGER Microcontroller Fighting product clones through digital signatures Product piracy and forgery are growing problems that not only decrease turnover
More informationLMS is a simple but powerful algorithm and can be implemented to take advantage of the Lattice FPGA architecture.
February 2012 Introduction Reference Design RD1031 Adaptive algorithms have become a mainstay in DSP. They are used in wide ranging applications including wireless channel estimation, radar guidance systems,
More informationAQA GCSE in Computer Science Computer Science Microsoft IT Academy Mapping
AQA GCSE in Computer Science Computer Science Microsoft IT Academy Mapping 3.1.1 Constants, variables and data types Understand what is mean by terms data and information Be able to describe the difference
More informationKEEP IT SYNPLE STUPID
Utilizing Programmable Logic for Analyzing Hardware Targets Dmitry Nedospasov SHORT DESCRIPTION Hardware security analysis differs from software security analysis primarily in the tools
More informationOpen Architecture Design for GPS Applications Yves Théroux, BAE Systems Canada
Open Architecture Design for GPS Applications Yves Théroux, BAE Systems Canada BIOGRAPHY Yves Théroux, a Project Engineer with BAE Systems Canada (BSC) has eight years of experience in the design, qualification,
More information路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
More informationSecure Authentication and Session. State Management for Web Services
Lehman 0 Secure Authentication and Session State Management for Web Services Clay Lehman CSC 499: Honors Thesis Supervised by: Dr. R. Michael Young Lehman 1 1. Introduction Web services are a relatively
More information