Overview of Radiation Test Activities on Memories at ESA

Transcription

1 Overview of Radiation Test Activities on Memories at ESA Dr. Véronique Ferlet-Cavrois IEEE Fellow ESA ESTEC, TEC-QEC 30/04/2015 Contact for information:

2 Outline o Memories in space applications o Different types, usage in space o Availability on the market o Radiation effects o Radiation Hardness Assurance o Utilisation of COTS in space o Typical examples of radiation effects in memories o PCRAM o NAND flash o SDRAM o SRAM o Utilisation of COTS in-flight o Example: SRAM Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 2

3 Memories in space applications Program / Configuration Storage (BIOS, FPGA configuration, etc.): PROM / E²PROM, MRAM, NAND/NOR Flash Data Buffer (TM, HK, Instrument data, etc.): SRAM (async., sync., FIFO, DPRAM), SDRAM MPU/MCU Memory: SRAM (async., sync.), SDRAM Mass Memory Platform Data Handling (OBC MM): SDRAM Payload Data Handling (PDHU, SSR, Compression MMU): SDRAM, NAND Flash [H. Schmidt, Airbus under ESA contract, Nov. 2014] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 3

4 Memories in Space Applications Payload Data Handling Increase of storage size: 10 Tbit (SAR, new optical instruments) Increase of Data Rate: 10 Gbps (SAR) Introduce of nonvolatile memory to increase storage size at reduced power consumption and weight Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 4 4 [H. Schmidt, Airbus under ESA contract, Nov. 2014]

5 Market Analysis Overview 2014 Forecast: Memory Market (US$ 69.9 Billion) 2014 Forecast: Memory Units (33.5 Billion) * NAND = 37% NOR = 3% Source: IC Insights Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 5 * NAND = 19% NOR = 13% [H. Schmidt, Airbus under ESA contract, Nov. 2014] 5

6 Market Analysis Overview Volatile Memory Non-volatile Memory SRAM async. / sync. I/F FIFO, DPRAM, etc. DRAM Computing (SDR, DDRx SDRAM) Mobile (LPDDRx) Graphic (GDDRx, ) ROM / EPROM / E²PROM Flash NOR (1 bit, 2 bits) NAND (SLC, MLC, TLC, 3-D) MRAM PCRAM FeRAM [H. Schmidt, Airbus under ESA contract, Nov. 2014] ReRAM, Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 6

7 Main radiation effects in electronic components Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 7 [R. Ecoffet, TNS June 2013]

8 Radiation Hardness Assurance Application to Memories ECSS-Q-ST-60-15C Space product assurance Radiation hardness assurance EEE components The flight lot is tested to: - TID (Co60) - SEE - high and low energy protons - Heavy ions - Comparison to the mission environment and device function Difficulty when using COTS components Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 8

9 COTS in space Why use Complexity of function Performance Availability [L. Adams, Radiation training course May 2003] Drawback Little or no traceability Rapid and un-announced design and process changes Rapid obsolescence Packaging issues (plastic) Effects of burn-in on radiation effects Deep dielectric charging in space Use of COTS The use of COTS does NOT necessarily result in cost saving Increase of the RISK Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 9

10 Real systems use a large variety of IC technology and generations, Different TID hardness levels [P. E. Dodd, 2009] 200 krad Compilation from data workshops between 2002 and 2004 Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 10

11 Examples of radiation effects in memories PCRAM o TID o SEE: functional failures, SEFIs Other memory types NAND-Flash memories o TID o Destructive events SDRAM o Stuck bits o SEFIs SRAM o MBU o Sensitivity to low energy protons o In-flight example of Latch-up Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 11

12 PCRAM Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 12

13 Micron (ex-numonyx) Omneo P8P NP8P128A13TSM60E phase change memory Radiation test results 1. TID tests a. Co60: No functional failure up to 700 krad(si) (also after annealing following irradiation) b. X-rays: No functional failures before 1.6 Mrad(Si), with one still functional above 4 Mrad(Si) 2. SEE tests [S. Gerardin, et al. a. Few SEUs under heavy ions at grazing angles IEEE TNS 2014] b. latch-up in all operating conditions, c. to a minor extent single event functional interrupts, and bursts of read errors. d. Permanent functional failures were also observed in one revision of the chips. e. No events observed under high energy protons 3. Despite the very good TID tolerance, SEL may prevent these devices to be used in space. [S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 13

14 TID test of the Omneo P8P NP8P128A13TSM60E phase change memory Increase in the standby current as a function of x-ray received dose [S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 14

15 SEE test of the Omneo P8P NP8P128A13TSM60E phase change memory Revision B of the die exhibited functional failure at low LET (3.3 MeVcm 2 /mg) Revision A: SEL, SEFI Rev. A, latch-up In one case, sudden spike in the supply current, which after less than 1 s went back to its normal value, likely due to a logic conflict triggered by an SEU Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 15 A previous report [O Bryan et al. REDW 2010] indicated a lower SEL LET th than found here, but likely due to different chip revision [S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract]

16 SEE test of the Omneo P8P NP8P128A13TSM60E phase change memory Rev. A, SEFIs Errors signaled by dedicated bits in the status register (SR). Other times, the SR reports a successful operation, but a following read showed that the array had not been properly programmed Single Event Functional are likely due to heavy-ion strikes on sensitive regions of the microcontroller (few thousand bits) [S. Gerardin, M. Bagatin, A. Paccagnella, U. Padova, 2013, ESA contract] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 16 SEFI recovery: At low LET: reset is effective most of the time At high LET: a power-cycle is required in 50% of the cases In few cases, repeating the operation is enough

17 Radiation effects in different types of memories Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 17

18 NAND-Flash TID: Errors in Storage Mode Error Share 1E+2 1E+1 1E+0 1E-1 1E-2 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 DUT 51, Micron 32 Gbit, Storage 85 C, 3.6V DUT 45, Micron 16 Gbit, Storage 85 C, 3.6V DUT 60, Micron 4x32 Gbit, Storage 25 C, 3.3V DUT 53, Micron 32 Gbit, MUB Storage 25 C, 3.3V DUT 40, Micron 16 Gbit, Storage 25 C, 3.3V DUT 52, Micron 32 Gbit, Storage 25 C, 3.3V DUT 41, Micron 16 Gbit, MUB Storage 25 C, 3.3V Dose [krad (Si)] [K. Grürmann, IDA, ESA contract ] functional breakdown of each DUT is marked with dotted line first random data errors already between 5 and 10 krad(si) Destructive Failure between 32 and 64 krad (Si) Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 18 18

19 NAND-Flash TID: Errors in Refresh Mode Error Share 1E+2 1E+1 1E+0 1E-1 1E-2 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E Dose [krad (Si)] Refresh every 2.5 krad(si) first random data errors already between 3 and 30 krad(si) periodic refresh keeps the error share below , tolerable before ECC Refresh has no influence on the Destructive Failure with periodic refresh the Destructive Failure occurrence determines the total dose Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 19 DUT 61, Micron 4x32 Gbit, Refresh 25 C, 3.3V DUT 50, Micron 32 Gbit, Refresh 85 C, 3.6V DUT 54, Micron 32 Gbit, Refresh 25 C, 3.3V DUT 42, Micron 16 Gbit, Refresh 25 C, 3.3V DUT 43, Micron 16 Gbit, MUB Refresh 25 C, 3.3V DUT 44, Micron 16 Gbit, Refresh 85 C, 3.6V DUT 20, Samsung 4x8 Gbit, Refresh 25 C, 3.3V [K. Grürmann, IDA, ESA contract ] Samsung 51nm: first SEUs after 70 krad(si), no functional breakdown until end of test at 90 krad(si) 19

20 Single Event Hard Errors: stuck bits Samsung 1Gbits DDR1 SDRAM Hyundai 64-Mb SDRAM Large part to part variations [Edmonds 2001] Micro-dose or displacement damage [Edmonds 2008] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 20 20

21 DDR3 results Stuck bits Stuck bits: can not be removed by rewriting [M. Herrmann, IDA, ESA contract ] 4E+0 Cross section [cm² / bit] 1E-11 1E-13 1E-15 1E-17 4 Gbit Samsung - SEU 4 Gbit Samsung - hard SEU 4 Gbit Elpida - SEU 4 Gbit Elpida - hard SEU 4E-2 4E-4 4E-6 4E-8 Cross section [cm² / device] 1E LET [MeV cm² / mg] 4E-10 Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 21 21

22 Stuck bits in NAND-flash 1.E-09 0 σ SEU [cm 2 bit -1 ] 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 1.E-15 1.E-16 1.E-17 significant soft SEU Annealing only at Nitrogen SEU = soft SEU + hard SEU SEU, Micron 16-Gb soft SEU after 20 days, Micron 16-Gb hard SEU, Micron 16-Gb hard SEU after 20 days, Micron 16-Gb LET [MeV mg -1 cm 2 ] 0 16-G Micron Chip Area / bit [cm 2 bit -1 ] Page Address soft SEU 10 hard SEU Byte Address [K. Grürmann, IDA, ESA contract ] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 22 22

23 Destructive events in NAND-Flash Samsung 8Gb NAND-Flash [K. Grürmann, IDA, ESA contract ] Permanent damage with definite data loss Thermal picture charge pump region [F. Irom, TNS Feb. 2010] 16 Gbit Micron shows also other DF types affecting the on-chip microcontroller Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 23 23

24 Multiple Cell Upset in SRAMs 40nm SRAM Tilt=0, Roll=90, Xenon, UCL [ESTEC contract 18799/04/NL/AG Hirex SEE test report, HRX/SEE/0288 STMicroelectronics 40nm SRAM test vehicle] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 24 One ion strike can induce more than 100 cell upsets 24

25 SEU sensitivity for low energy proton in SRAM from 90nm and beyond Devices with very low LET thresholds are sensitive to proton-induced upset by direct ionization. Bulk 65nm SRAM [B. Sierawski, TNS 2009] [H. Puchner, REDW 2011] Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 25 25

26 Low energy protons sensitivity in 28nm SRAMs STMicroelectronics 28nm ST Low energy protons High energy beam Method needed to calculate the SEE rate due to low energy protons in space [H. Kettunen, et. al. IEEE REDW 2014] ESA contract Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 26

27 In-flight example SRAM Aboard Proba-2 Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 27

28 GPS receiver: latch-up events in 512kx8 SRAM Samsung K6R4016V1D-TC10 The GPS counts two redundant receiver units and a current limiter; in cold redundancy logic Proba-2: polar LEO Samsung K6R4016V1D-TC10 DC 220 TANO6EE KOREA The devices were unsufficiently tested before flight Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 28 [M. D Alessio, et al. ESA at RADECS 2013]

29 Statistical analysis of the GPS latch-up events from Oct-10 to Dec-12 Average upset rate of 12 SELs/month (0.4 SEL/day) Large variability, from 6 to 27 SELs/months 87% SELs are in the SAA Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 29 [M. D Alessio, et al. ESA at RADECS 2013]

30 Statistical analysis of the GPS latch-up events (cont.) 3 Cumulative Weibull ln(-ln(1-δt) orbit 4 orbits 14 orbits Slope of 1: Signature of random single event effects -7 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Time difference between two consecutive latch-ups (s) Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 30 [M. D Alessio, et al. ESA at RADECS 2013]

31 The ground tests of the Samsung K6R4016V1D-TC10 shows large differences vs. Date Code Heavy ion test Heavy ions Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 31 [V. Ferlet-Cavrois, ESA test report 2012]

32 The ground tests of the Samsung K6R4016V1D-TC10 shows large differences vs. Date Code Proton test High energy protons DC220 DC328 DC922 Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 32 [V. Ferlet-Cavrois, ESA test report 2012]

33 Conclusion o Test the flight lots o Test in the application conditions o Test to the environment specifications Test standards: ESCC22900 TID ESCC25100 SEE RHA ECSS-Q-ST-15C Find information in: Resistive memories workshop Véronique Ferlet-Cavrois ESTEC 30/04/2015 Slide 33