Future for photonic ICs assembly and packaging

Transcription

1 Future for photonic ICs assembly and packaging JePPIX training, Daejeon Dr. Tolga Tekin Photonic & Plasmonic Systems Fraunhofer for Reliability and Microintegration (IZM) Technische Universität Berlin Research Center of Microperipheric Technologies Based on the lecture notes Berlin) Packaging Design, Simulation and Reliability of Microsystems DECKBLATT 5G Data Center Silicon Green Integrated Ocean - ICT Bay, EU

2 Why Integrated? Motivation Roadmaps State-of-the-art 3 Moore s Law and More Motivation Technological frontiers between semiconductor technology, packaging, and system design are tending to disappear. Designers of chips, packages, and systems will have to work closer together than ever before in order to drive the performance for future microelectronic systems. The semiconductor technology is heading the basic physical limits to CMOS scaling. The scaling geometries alone do not ensure improvement of performance, less power, smaller size, and lower cost. It will require More than Moore through the tighter integration of system level components at the package level. Gordon Moore Roadmaps State-of-the-art (ITRS: International Technology Roadmap for Semiconductors) 4

3 Bottleneck A key bottleneck to the realization of high-performance microelectronic systems, including SiP, is the lack of low-latency, high-bandwidth, and high density off-chip interconnects. Some of the challenges in achieving high-bandwidth chip-to-chip communication using electrical interconnects include the high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to crosstalk. Obviously, the motivation for the use of photonics to overcome these challenges and leverage low-latency and high-bandwidth communication. The objective is to develop a CMOS compatible underlying technology to enable next generation photonic layer within the 3D SiP towards converged microsystems Motivation Roadmaps State-of-the-art Tekin, T.;, "Review of Packaging of Optoelectronic, Photonic, and MEMS Components," Selected Topics in Quantum Electronics, IEEE Journal of, vol.17, no.3, pp , May-June 2011 doi: /JSTQE Interconnect and packaging technologies Reduce losses for multiple inputs & output chip to chip optical interfaces Support multifunctional applications with new capabilities based on compatible technologies to reduce fabrication costs. Most photonics research programs address only marginally the issues related to photonics packaging. How the photonics packaging changed over the years? MZI packages 6

4 MZI package Monolithically integrated MZI for demultiplexing & wavelength conversion Electrically contacting of SOAs Coupling of three fibers to ±7 tilted waveguides Brass module (60mm x 20mm x 12mm) Chip mounted on ceramic holder Mounted on Peltier element HHI 7 GS-MZI package T. Tekin, M. Schlak, W. Brinker, J. Berger, C. Schubert, B. Maul, and R. Molt. Ultrafast all-optical demultiplexing performance of monolithically integrated band gap shifted Mach-Zehnder interferometer, Proceedings of ECOC, Vol. 4, pp (2001). 8

5 MZI package MZI for synchronous modulation based 3R regeneration 2mm long SOAs 7 tilted waveguides T. Tekin, C. Bornholdt, J. Slovak, M. Schlak, B. Sartorius, J. Kreissl, S. Bauer, C. Bobbert, W. Brinker, B. Maul, C. Schmidt, H. Ehlers. Semiconductor based true all-optical synchronous modulator for 3R regeneration. Proceedings of the 29th ECOC, Vol. 2, pp (2003). 9 Hybrid-MZI packages K. Tajima et al. Hybrid integrated symmetric Mach-Zehnder all-optical switch with ultrafast, high extinction switching, EL vol35pp ,1999 Maxwell, G. Et al. Hybrid integration of monolithic semiconductor optical amplifier arrays using passive assembly, ECTC, Vol

6 Converging Technologies Converging technologies are shaping the future of our society. Boarders between disciplines are disappearing. Information and communication technology transformed our daily life in last century. New technologies such as nanotechnology have significant potential for further transformation. ICT manufacturing concepts, instead of very specialized production lines more and more generic approaches are required to serve a broader area of interest Concentrated know-how and the enormous qualified technology base is available from some institutional core-players in the research field of packaging. Motivation Roadmaps State-of-the-art 11 Generic Packaging Aspects The spectrum of packaging tasks in photonics is diverse and complex: pigtailing, housing design substrate manufacturing dedicated assembly soldering techniques sealing The goal: Not the development application specific packages, but rather to investigate some generic aspects that will become of central importance in silicon photonics packaging. Motivation Roadmaps State-of-the-art 12

7 The Enabling Technology? Electronics Electrical interconnects: limited by RC-delay Electronics is aspect-ratio limited in speed..but still the most mature intelligence platform Motivation Roadmaps State-of-the-art 13 The Enabling Technology? Motivation Silicon Integrated optical components based on Silicon Energy-efficient, high bandwidth data communication on short distances Bit rate is limited only by the carrier frequency (100Tb/s) Light propagation: subjected to diffraction down-limits component size Source: AMO Si Source: IBM SiO 2 Roadmaps State-of-the-art 14

8 The Enabling Technology? Motivation Plasmonics Propagation of Surface Plasmon Polariton (SPP) modes using metallic nanostructures EM waves guided at the metal/dielectric interface 15 Sub-wavelength confinement! No limitations in speed and size Seamless interface between optics-electronics Loss Roadmaps State-of-the-art Operating speed Combine Benefits On-Chip 1THz 1GHz 1MHz 1kHz Plasmonics Electronics Diffraction limit The Past RC-delay limit 10nm 100nm 1μm 10μm 100μm 1mm Critical dimension The next chip-scale technology!!! R. Zia et al., Plasmonics: the next chip-scale technology, Materials Today 9(7-8), 2006 D. K. Gramotnev and S. I. Bozhevolnyi, Plasmonics beyond the diffraction limit, Nature Nanophotonics 4(2), 2010 electronics for smart functions (processing, control) Silicon photonics for low-loss passive optics Plasmonics for low-power active functions Motivation Roadmaps State-of-the-art 16

9 Success Stories Motivation Roadmaps State-of-the-art 17 Success Stories Motivation Roadmaps State-of-the-art 18

10 Success Stories Motivation Roadmaps State-of-the-art 19 Silicon Integrated Circuit Design Rules for Packaging 20

11 Coupled asymmetric SOA MZI Flip Flop optic al IOs SOAs Au bond pads Au wire bonds Au-plated ceramic 21 SOA XGM Flip Flop design rules optic al IOs Au wire bonds Au-plated ceramic SOAs 22

12 Packaging - Providing Reliable Interfaces electrical rf fluidic thermal component wireless optical electrical dc mechanical 23 Photonic ITRS Packaging of optoelectronic and MEMS components has been treated by ITRS in the section ASSEMBLY AND PACKAGING under packaging for specialized functions Optoelectronics packaging covers an expanding range of new technical requirements depending on their applications. Examples of optoelectronic packages and their applications are presented There are many difficult challenges remaining for optical packaging and they will become increasingly critical as the optical communication gets ever closer to the chip. A list of these challenges, technology requirements, potential solutions and the Cross TWG are presented. Review of Packaging of Optoelectronic,Photonic, and MEMS Components IEEE JSTQE (2011) DOI: /JSTQE

13 Silicon Waveguides 4 μm rib waveguide 1.5 μm rib waveguide 0.2 μm nanowaveguide Si SiO 2 25 Endfire coupling to 4 μm rib waveguide Best case: ~3 db loss SMF28 Modedistribution 26

14 Endfire coupling to 1.5 μm rib waveguide Best case: ~12 db loss SMF28 Modedistribution 27 Endfire coupling to 0.2 μm nano waveguide Best case: ~20 db loss SMF28 Modedistribution 28

15 Coupling to Si Nanowaveguides Grating Couplers Out-of-plane Planar process On wafer testing Filter device Polarization Wavelength TE -4.5 db D. Taillaert et al, Grating couplers for coupling between optical fibers and nanophotonic waveguides, Jap. JAP 45 (8A), p (2006) 29 Alignment Tolerances of Grating Couplers 1D grating coupler 70 nm etch 25 periods Measured alignment tolerances 1-2 μm : loss < 1 db 30

16 Specs of commercial available fiber arrays Up to 48 fibers ( 8, 16, 24, 32, 48) 8 tilted! Pitch: 127μm, 250μm, 400μm, 500μm Thickness of array 2.03mm 31 Multi Fiber Array to SOI Chip Coupling Passive SOI test chip 8 grating couplers Pitch 250 μm 6 shortened by waveguides Labeled accordingly use 6 fibers of 8 fiber array Schematic of the shortened grating couplers 32

17 8-Fiber Array based on V-Grooves xy-scanned of fiber positions For fibers 1-3 and 6-8 Source: OZ Optics 33 Misalignment Fibers in V-Groove Array & Fiber Loss measured tolerances of the commercial multi fiber-array mismatch Höhenabweichung in x [μm] fibre # mismatch in x [μm] mismatch in y [μm] loss [db] Discrepancy relative to the ideal conditions are due to tolerances of the v-groove base core/cladding geometry of the fibers mismatch Pitchfehler in y [μm] pitch vertical 34

18 Smart Packaging of Silicon Chip Fibre-array based interconnection without glop top Encapsulated SOI chip on fibre-array in comparison to 1 Euro Cent coin 35 Transmission Test on Smart Packaged SOI Chip Uniformity: 1 db Fiber coupling penalty: ~ 1 db T. Tekin, H. Schröder, L. Zimmermann, P. Dumon, W. Bogaerts "Fibre-array optical interconnection for silicon photonics" Proc. of ECOC, Vol. 5, pp (2008). 36

19 g-pack Generic Packaging for SOI O/E Multiport L. Zimmermann, T. Tekin, P. Dumon, W. Bogaerts. "How to bring nanophotonics to application - silicon photonics packaging". LEOS Newsletter December Concept - Inverted Taper based Coupling a) Coupling structure SOI waveguide b) Inverted taper Lt V Groove W Si substrate Adapt to standard layouts for optoelectronics devices For passive chip assembly Improvement in the alignment Anisotropic KOH etching b) wt H SiO2 BOX c) Optical fiber 38

20 Inverted Taper based Coupling for V-Groove Integration 6dB coupling loss to 10μm MFD standard fibers (TE and TM) Spectral response is almost flat in a wavelength bandwidth higher than 70nm J. V. Galan et al. CMOS compatible silicon etched V-grooves integrated with a SOI fiber coupling technique for enhancing fiber-to-chip alignment IEEE LEOS GFP ThP Possible Chip Layout Optical I/O portsgroove Fiber array Electrical ports Electrical ports 40

21 Fiber pigtailing SM fiber arrays (4 64), 250μm or 125μm pitch, coupling angle 0 15 Vertical grating coupler dimensions: 10μm x 14-17μm Defined position near the chip edge with space for mechanical stabilization of the Connector (connector dimensions define this blind chip area part) Two alignment channels (back-to-back) on chip on both ends of the array to realize active alignment. Minimum distance fiber coupler to chip edge 250μm Minimum vertical distance fiber end to grating μm with optical adhesive within the gap (refractive index has to be clarified) On-chip alignment features: array corner markers required, glue overflow channels beneficial 41 Flip-Chip & Die Bonding Single Chip or Substrate Bumping mechanical Au stud bumping requires bondable surface finish: Al, Au, Pd, Pt, Ag smallest pitch: 60 μm bump diameter: 40 to 60 μm bump height: 20 to 80 μm (stacked balls) Wafer Bumping electroplated bumps minimal pitch: down to 50 μm, smaller on request Electroless underbump metallization (UBM) with standard CMOS finish: Al; Cu possible smallest pad-to-pad distance: 10 μm Flip Chip Assembly Thermocompression / Thermosonic Bonding with post bond accuracy: down to 1 μm Adhesive bonding with pitch down to 100 or 40 μm depending on method Reflow soldering pitch down to 50 μm 42

22 Wire Bonding Fully automatic bonding equipment for ball/wedge and wegde/wegde bonding Bonding of Au, AlSi1, Cu wires (other materials on request) Bonding of Al- or Au-ribbons Wire size μm Minimum pitch size 70 μm for wedge/wedge, 35 μm for ball/wedge Long- and low-loop bonding Room temperature bonding Bonding of stacked dies Typical height step between bonding levels 0,05-2 mm Loop lengths between 0,1 6 mm (10 mm is maximum) 43 UDWDM photodetector array 44

23 UDWDM on the silicon substrate Optical chip coupling with vertical grating couplers Wire bondings for the integrated heaters -> tuning the filters Stubs for impedance matching (20Ohm to 50Ohm) 45 Trans impedance amplifier (TIA) with differential output to SMA Low cost active-passive & low profile package Joint development with UPVLC 46

24 47 Silicon Activities at Fraunhofer IZM epixnet HELIOS PLATON iphos RAMPLAS PARADIGM UPVLC COMANDER 48

25 Fraunhofer IZM s Concept 49 Quo vadis? 1) Light Source External Cavity Laser Light Source Merging of Silicon Electronics and Waveguides 2) Guide Light Splitters Tapers Switches, Couplers, & others 3) Fast Modulation Silicon Modulator 4) Detect Light Photo-Detector 5) Low Cost Assembly Passive Alignment BUILDING BLOCKS OF SILICON PHOTONICS by Intel 6) Intelligence CMOS 50

26 In the Age of Converging Technologies FACT: System complexity and functionality are increasing TARGET: Seamless applications (ICT) FIRST STEP: Generic foundry and packaging approaches That can be satisfied by heterogeneous integration of different technologies, leading to the best compromise in systems functionality and cost of ownership for higher multi functional converging systems. All these technologies need to be optimized All these technologies need to be adapted into a modular integrated process flow Integration Platform Targeting high-performance, low-cost, low-energy and small-size components across the entire interconnect hierarchy level can definitely not rely on a single technology platform. OBJECTIVE Create the optimal synergies between different technologies streamlining their deployment towards Tb/sscale, high-performance, low-cost and low-energy optical interconnect components and sub-systems Mix & Match components / building blocks to deliver the optimal heterogeneous integration and to align their synergistic deployment towards the specific needs of individual functions VSI Tolga Tekin, Michael Töpper and Herbert Reichl, "PICSiP: new system-in-package technology using a high bandwidth photonic interconnection layer for converged microsystems", Proc. SPIE 7366, (2009); 52

27 Silicon Interposer with Optical Layer adaptation to 3D VSI process flow 3D wafer-level system integration (300mm wafer) Die-to-wafer and wafer-to-wafer bonding Wafer-level assembly and 3D stacking Evaluation of die-to-wafer (D2W) and wafer-to-carriewafer (W2W) assembly technologies 3D IC assembly with high-density interconnects (> 1000 I/O) and ultra-fine pitch (< 50μm) 3D IC assembly with thin and ultra-thin chips (20-150μm) Through silicon via technology TSV diameter: 2 20μm; aspect ratio: 5 to 30 Wafer bumping technology 53 back side isolation metallization isolation oe chip Cu TSV isolation Leveraging know-how, experience and technology of 3D heterogeneous integration, including system-in-package Silicon interposer technology with high-density wiring Interposers with high-density Cu-TSV BOX High-density multilayer copper wiring (min. 2μm line /space) Embedding of active and passive devices into the silicon interposer Wafer thinning and handling technology device wafer thickness: <20 μm Temporary wafer bonding and debonding technology Si Building-Blocks for Optical Optical waveguides Coupling to fiber 3dB splitter Ring resonators MUX/DEMUX Switches MZI Electro-optical Photodetectors Light sources: LED, VCSEL Electrical Through-Silicon Vias (TSV) Transmission line: CPW, slotline Antenna Heater developed in projects 54

28 Tb/s Silicon Plasmonic Router Pleros, N.; Vyrsokinos, K.; Papaioannou, S.; Fitsios, D.; Tsilipakos, O.; Pitilakis, A.; Kriezis, E.; Miliou, A.; Tekin, T.; Baus, M.; Karl, M.; Kalavrouziotis, D.; Giannoulis, I.; Avramopoulos, H.; Djellali, N.; Weeber, J.-C.; Markey, L.; Dereux, A.; Gosciniac, J.; Bozhevolnyi, S.;, "Tb/s switching fabrics for optical interconnects using heterointegration of plasmonics and silicon photonics: The FP7 PLATON approach," IEEE Society, rd Annual Meeting of the, vol., no., pp , 7-11 Nov doi: /PHOTONICS Buffering as a Generic HPC Problem Processor memory gap Latency of the entire HPC is limited by the nsec access time of electronic RAM The well-known Memory Wall but electronic RAM is the only available solution for the HPC Storage Area 56

29 Short-Range mmw Very High-Speed Data Link To develop compact, low power, high performance transceivers that enable wireless data transfer at sub-terahertz carrier wave frequencies based on optical signal generation and processing G. Carpintero Integrated photonic transceivers at sub-terahertz wave range for ultra-wideband wireless communications EU ICT RF-MST Cluster Workshop 2/07/2012 Tekin, -SIIT Antalya 57 Integrating RoF with 60GHz wireless and FTTH...in a photonic chip Design, development and deployment of a fully converged Next-Generation Fiber- Wireless network architecture A. Sosa, K. Welikow, R. Broeke, A. Bakker, D. Tsiokos, T. Tekin, and N. Pleros, "Demonstrating efficient design transfer methods for complex photonic integrated circuits", Annual Benelux Symposium 2014, Enschede, The Netherlands, November

30 Heterogeneous Integration Silicon as integration platform Designed by IZM Fabricated in AMO Chracterized in IZM Integrated in IZM Fiber to Si coupler MUX Waveguides Electrical wiring Si to DLSPP interface Plasmonics switches Designed by SDU Fabricated in UB Chracterized in IZM Integrated in IZM Plasmonic switching elements Control IC Designed by IZM Fabricated in ams Chracterized in IZM Integrated in IZM Logic IC Achievements PLATON SOI Platform Design rules 59 is a large-scale European research effort focusing on high-performance, low-energy, low-cost, small-size Optical interconnects across the whole data center ecosystem: on-board, board-to-board and rack-to-rack. 60

31 Objectives Generic building block that can be used for a broad range of applications, extending performance beyond Tb/s and reducing energy by more than 50%. A unified integration/packaging methodology as a cost/energyreduction factor for board-adaptable 3D SiP transceiver and router optochip fabrication. The whole "food-chain" of low-cost and low-energy interconnect technologies concluding to 3 fully functional prototype systems: an >1Tb/s throughput optical PCB and >50% reduced energy requirements a high-end >2Tb/s throughput optical backplane for board-to-board interconnection and a 1.28Tb/s Active Optical Cable that reduces power requirements by >70%. 61 Holistic Approach tackles optical interconnects in a holistic way, synergizing the different technology platforms in order to deploy the optimal "mix&match" technology and tailor this to each interconnect layer. PCBs Interfaces Polymers Glass Glass Plasmonics PICs Transceivers Switches & Routers Si III-V Si CMOS electronics CMOS electronics 62

32 - Optical Interconnection Technologies Opto-Chips increasing optical functionalities 64

33 - Interfaces from standard to emerging technologies 65 - Roadmap Roadmap 66

34 Program : ICT - Information and Communication Technologies Project Coordinator: Dr. Tolga Tekin Photonic & Plasmonic Systems, Fraunhofer for Reliability and Microintegration (IZM) [email protected] 67 Reliability: Essential for System Integration 68

35 Small cause... January 28, 1986 at 11:38:00 a.m. Challenger take off R. P. Feynman 69 Failure 70

36 Failure 71 Advanced packaging technologies will improve future systems: 1. Packaging determines functionality, cost and reliability of future systems. 2. System-in-Package is the way for future subsystems. 3. Future systems are very high complex systems and contain different physical functions. Therefore modularity in heterogeneous integration is required. 4. Future systems combine optical and ultra high frequency functions. They contain antennas, batteries, sensors, optical components, and microelectronic devices. With this a large variety of materials will be applied. For all these components a common smart support substrate such as Silicon will be of importance for future systems. HETERO SILICON PHOTONICS - Integration Platform Tekin, T.;, "Review of Packaging of Optoelectronic, Photonic, and MEMS Components," Selected Topics in Quantum Electronics, IEEE Journal of, vol.17, no.3, pp , May-June 2011 doi: /JSTQE Achievements Design rules