OUTPUT FREQUENCY CONTENTS

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1 SEMIONDUTOR TEHNIAL DATA Order this document by M4 2/D MOS The devices described in this document are typically used as low power, phase locked loop frequency synthesizers. When combined with an external low pass filter and voltage controlled oscillator, these devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the device s frequency limit. For higher VO frequency operation, a down mixer or a prescaler can be used between the VO and the synthesizer I. These frequency synthesizer chips can be found in the following and other applications: ATV AM/FM Radios Two Way Radios TV Tuning Scanning Receivers Amateur Radio OS R ONTROL LOGI φ A N P/P + VO DEVIE DETAIL SHEETS OUTPUT FREQUENY ONTENTS M4 2 Parallel Input, Single Modulus M42 2 Parallel Input, Dual Modulus M4 2 Serial Input, Single Modulus M46 2 Serial Input, Dual Modulus M47 2 Serial Input, Single Modulus M48 2 Serial Input, Dual Modulus FAMILY HARATERISTIS Maximum Ratings D Electrical haracteristics A Electrical haracteristics Timing Requirements Frequency haracteristics Phase Detector/Lock Detector Output Waveforms DESIGN ONSIDERATIONS REV 8/ Phase Locked Loop Low Pass Filter Design rystal Oscillator onsiderations Dual Modulus Prescaling Page Motorola, Inc. M4 2 through M48 2

2 SEMIONDUTOR TEHNIAL DATA Interfaces with Single Modulus Prescalers The M4 2 is programmed by 4 parallel input data lines for the N counter and three input lines for the R counter. The device features consist of a reference oscillator, selectable reference divider, digital phase detector, and 4 bit programmable divide by N counter. The M4 2 is an improved performance drop in replacement for the M4. The power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range On or Off hip Reference Oscillator Operation Lock Detect Signal N ounter Output Available Single Modulus/Parallel Programming 8 User Selectable R Values: 8, 28, 26, 2, 24, 248, 24, 82 N Range = to 68 Linearized Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single Ended (Three State) or Double Ended hip omplexity: 8 FETs or 2 Equivalent Gates P SUFFIX PLASTI DIP ASE 7 DW SUFFIX SOG PAKAGE ASE 7F ORDERING INFORMATION M4P2 M4DW Plastic DIP SOG Package PIN ASSIGNMENT RA RA RA2 fv N N N2 N OSout N N N N2 T/R N N8 N7 N6 N N4 REV 8/ Motorola, Inc. M4 2 through M48 2 2

3 M4 2 BLOK DIAGRAM OSout RA2 RA RA 4 x 8 ROM REFERENE DEODER 4 LOK DETET 4 BIT R OUNTER PHASE DETETOR A 4 BIT N OUNTER T/R 4 TRANSMIT OFFSET ADDER PHASE DETETOR B fv N N N N7 N6 N4 N2 N NOTE: N N inputs and inputs RA, RA, and RA2 have pull up resistors that are not shown. INPUT PINS Frequency Input (Pin ) PIN DESRIPTIONS Input to the N portion of the synthesizer. is typically derived from loop VO and is ac coupled into the device. For larger amplitude signals (standard MOS logic levels) dc coupling may be used. RA RA2 Reference Address Inputs (Pins, 6, 7) These three inputs establish a code deing one of eight possible divide values for the total reference divider, as deed by the table below. Pull up resistors ensure that inputs left open remain at a logic and require only a SPST switch to alter data to the zero state. Reference Address ode RA2 RA RA Total Divide Value N N N ounter Programming Inputs (Pins 2, 22 2) These inputs provide the data that is preset into the N counter when it reaches the count of zero. N is the least significant and N is the most significant. Pull up resistors ensure that inputs left open remain at a logic and require only an SPST switch to alter data to the zero state. T/R Transmit/Receive Offset Adder Input (Pin 2) This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting the VO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 86 when T/R is low and gives no offset when T/R is high. A pull up resistor ensures that no connection will appear as a logic causing no offset addition., OSout Reference Oscillator Input/Output (Pins 27, 26) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. OUTPUT PINS Phase Detector A Output (Pin 4) Three state output of phase detector for use as loop error signal. Double ended outputs are also available for this purpose (see and ). Frequency fv > fr or fv Leading: Negative Pulses Frequency fv < fr or fv Lagging: Positive Pulses Frequency fv = fr and Phase oincidence: High Impedance State M4 2 through M48 2

4 , Phase Detector B Outputs (Pins 8, ) These phase detector outputs can be combined externally for a loop error signal. A single ended output is also available for this purpose (see ). If frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. fv N ounter Output (Pin ) This is the buffered output of the N counter that is internally connected to the phase detector input. With this output available, the N counter can be used independently. Lock Detector Output (Pin 28) Essentially a high level when loop is locked (fr, fv of same phase and frequency). Pulses low when loop is out of lock. POWER SUPPLY Positive Power Supply (Pin ) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (Pin 2) The most negative supply potential. This pin is usually ground. TYPIAL APPLIATIONS 2.48 MHz N N N N2 N OSout N N N8 M4 2 N7 N6 N RA2 RA N4 N N2 RA N N VOLTAGE ONTROLLED OSILLATOR. MHz = MHz =. MHz REF. OS..47 MHz (ON HIP OS. OPTIONAL) REEIVE + V Figure. MHz to. MHz Local Oscillator hannel Spacing = khz T/R TRANSMIT (ADDS 86 TO N VALUE) OSout RA2 RA RA M4 2 HANNEL PROGRAMMING N = 2284 TO 484 LOK DETET SIGNAL HOIE OF DETETOR ERROR SIGNALS LOOP FILTER T: MHz R: MHz 6.2 MHz NOTES:. fr = khz; R = 24; 2.4 MHz low side injection during receive. 2. Frequency values shown are for the MHz band. Similar implementation applies to the MHz band. For 47 2 MHz, consider reference oscillator frequency X for mixer injection signal (.7 MHz). Figure 2. Synthesizer for Land Mobile Radio UHF Bands fv fv X6 VO DOWN MIXER TRANSMIT: MHz REEIVE: MHz (2 khz STEPS) X6 T: MHz R: MHz M4 2 Data Sheet ontinued on Page 2 M4 2 through M48 2 4

5 SEMIONDUTOR TEHNIAL DATA Interfaces with Dual Modulus Prescalers The M42 2 is programmed by sixteen parallel inputs for the N and A counters and three input lines for the R counter. The device features consist of a reference oscillator, selectable reference divider, two output phase detector, bit programmable divide by N counter, and 6 bit programmable A counter. The M42 2 is an improved performance drop in replacement for the M42. Power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range On or Off hip Reference Oscillator Operation Lock Detect Signal Dual Modulus/Parallel Programming 8 User Selectable R Values: 8, 64, 28, 26, 2, 24, 6, 248 N Range = to 2, A Range = to 6 hip omplexity: 8 FETs or 2 Equivalent Gates See Application Note AN P SUFFIX PLASTI DIP ASE 7 DW SUFFIX SOG PAKAGE ASE 7F ORDERING INFORMATION M42P2 M42DW Plastic DIP SOG Package PIN ASSIGNMENT RA RA RA2 M A N N N2 N OSout A4 A A A2 A N N8 N7 N6 N N4 REV 8/ Motorola, Inc. M4 2 through M48 2

6 M42 2 BLOK DIAGRAM OSout RA2 RA RA 2 x 8 ROM REFERENE DEODER 2 2 BIT R OUNTER LOK DETET M ONTROL LOGI PHASE DETETOR 6 BIT A OUNTER BIT N OUNTER A A A2 A N N2 N4 N N7 N NOTE: N N, A A, and RA RA2 have pull up resistors that are not shown. INPUT PINS Frequency Input (Pin ) PIN DESRIPTIONS Input to the positive edge triggered N and A counters. is typically derived from a dual modulus prescaler and is ac coupled into the device. For larger amplitude signals (standard MOS logic levels) dc coupling may be used. RA, RA, RA2 Reference Address Inputs (Pins 4,, 6) These three inputs establish a code deing one of eight possible divide values for the total reference divider. The total reference divide values are as follows: Reference Address ode RA2 RA RA M4 2 through M Total Divide Value N N N ounter Programming Inputs (Pins 2) The N inputs provide the data that is preset into the N counter when it reaches the count of. N is the least significant digit and N is the most significant. Pull up resistors ensure that inputs left open remain at a logic and require only a SPST switch to alter data to the zero state. A A A ounter Programming Inputs (Pins 2, 2, 22, 24, 2, ) The A inputs dee the number of clock cycles of that require a logic on the M output (see Dual Modulus Prescaling section). The A inputs all have internal pull up resistors that ensure that inputs left open will remain at a logic., OSout Reference Oscillator Input/Output (Pins 27, 26) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. OUTPUT PINS, Phase Detector B Outputs (Pins 7, 8) These phase detector outputs can be combined externally for a loop error signal. If the frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. M Dual Modulus Prescale ontrol Output (Pin ) Signal generated by the on chip control logic circuitry for controlling an external dual modulus prescaler. The M level will be low at the beginning of a count cycle and will remain low until the A counter has counted down from its programmed value. At this time, M goes high and remains high until the N counter has counted the rest of the way down from its programmed value (N A additional counts since both N and A are counting down during the first

7 portion of the cycle). M is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + represent the dual modulus prescaler divide values respectively for high and low M levels, N the number programmed into the N counter, and A the number programmed into the A counter. Lock Detector Output (Pin 28) Essentially a high level when loop is locked (fr, fv of same phase and frequency). Pulses low when loop is out of lock. POWER SUPPLY Positive Power Supply (Pin ) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (Pin 2) The most negative supply potential. This pin is usually ground. NO ONNETS TYPIAL APPLIATIONS.24 MHz NOTE LOK DETET SIGNAL R2 7 MHz khz STEPS + V OSout RA2 RA M42 2 RA M R R R2 + M7 NOTE 2 VO N N A A HANNEL PROGRAMMING NOTES:. Off chip oscillator optional. 2. The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure. Synthesizer for Land Mobile Radio VHF Bands M27 64/6 PRESALER M4 2 through M48 2 7

8 REF. OS..6 MHz (ON HIP OS. OPTIONAL) X2 NO ONNETS REEIVER 2ND L.O..72 MHz LOK DETET SIGNAL R2 REEIVER FIRST L.O MHz ( khz STEPS) + V N OSout RA2 RA M42 2 NOTE N A RA M A R R R2 + NOTE 7 VO X4 NOTE 6 TRANSMITTER MODULATION X4 NOTE 6 HANNEL PROGRAMMING M27 64/6 PRESALER NOTE 6 NOTES:. Receiver st I.F. = 4 MHz, low side injection; Receiver 2nd I.F. =.7 MHz, low side injection. 2. Duplex operation with 4 MHz receiver/transmit separation.. fr = 7. khz; R = Ntotal = N 64 + A = 27 to 2866; N = 42 to 44; A = to 6.. M48 2 may be used where serial data entry is desired. 6. High frequency prescalers (e.g., M28 [2 MHz] and M222 [ GHz]) may be used for higher frequency VO and fref implementations. 7. The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure hannel, omputer ontrolled, Mobile Radiotelephone Synthesizer for 8 MHz ellular Radio Systems TRANSMITTER SIGNAL MHz ( khz STEPS) M42 2 Data Sheet ontinued on Page 2 M4 2 through M48 2 8

9 SEMIONDUTOR TEHNIAL DATA Interfaces with Single Modulus Prescalers The M4 2 is programmed by a clocked, serial input, 6 bit data stream. The device features consist of a reference oscillator, selectable reference divider, digital phase detector, 4 bit programmable divide by N counter, and the necessary shift register and latch circuitry for accepting serial input data. The M4 2 is an improved performance drop in replacement for the M4. Power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range On or Off hip Reference Oscillator Operation with Buffered Output ompatible with the Serial Peripheral Interface (SPI) on MOS MUs Lock Detect Signal Two Open Drain Switch Outputs 8 User Selectable R Values: 6, 2, 24, 248, 668, 46, 644, 82 Single Modulus/Serial Programming N Range = to 68 Linearized Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single Ended (Three State) or Double Ended hip omplexity: 64 FETs or 626 Equivalent Gates 8 2 P SUFFIX PLASTI DIP ASE 77 DW SUFFIX SOG PAKAGE ASE 7D ORDERING INFORMATION M4P2 M4DW2 Plastic DIP SOG Package PIN ASSIGNMENTS RA RA2 PLASTI DIP RA OSout REFout SW2 SW ENB DATA LK SOG PAKAGE RA RA N RA OSout REFout N SW2 SW ENB DATA LK N = NO ONNETION REV 8/ Motorola, Inc. M4 2 through M48 2

10 M4 2 BLOK DIAGRAM OSout RA2 RA RA 4 x 8 ROM REFERENE DEODER 4 LOK DETET 4 BIT R OUNTER REFout fr fv PHASE DETETOR A 4 BIT N OUNTER 4 PHASE DETETOR B SW2 ENB LATH LATH SW DATA LK 4 4 BIT SHIFT REGISTER 2 BIT SHIFT REGISTER INPUT PINS PIN DESRIPTIONS Frequency Input (PDIP Pin, SOG Pin ) Input to the N portion of the synthesizer. is typically derived from loop VO and is ac coupled into the device. For larger amplitude signals (standard MOS logic levels) dc coupling may be used. RA, RA, RA2 Reference Address Inputs (PDIP Pins 8,, 2; SOG Pins 2,, 2) These three inputs establish a code deing one of eight possible divide values for the total reference divider, as deed by the table below: Reference Address ode RA2 RA RA LK, DATA Shift Register lock, Serial Data Inputs (PDIP Pins, ; SOG Pins, 2) Total Divide Value Each low to high transition clocks one bit into the on chip 6 bit shift register. The Data input provides programming information for the 4 bit N counter and the two switch signals SW and SW2. The entry format is as follows: N LSB N OUNTER BITS N MSB LAST DATA BIT IN (BIT NO. 6) FIRST DATA BIT IN (BIT NO. ) ENB Latch Enable Input (PDIP Pin 2, SOG Pin ) When high (), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW and SW2. When low (), ENB inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter programming and switch outputs. An on chip pull up establishes a continuously high level for ENB when no external signal is applied. ENB is normally low and is pulsed high to transfer data to the latches., OSout Reference Oscillator Input/Output (PDIP Pins 7, 6; SOG Pins, 8) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. SW2 SW M4 2 through M48 2

11 OUTPUT PINS Phase Detector A Output (PDIP, SOG Pin 6) Three state output of phase detector for use as loop error signal. Double ended outputs are also available for this purpose (see and ). Frequency fv > fr or fv Leading: Negative Pulses Frequency fv < fr or fv Lagging: Positive Pulses Frequency fv = fr and Phase oincidence: High Impedance State, Phase Detector B Outputs (PDIP, SOG Pins 4, ) These phase detector outputs can be combined externally for a loop error signal. A single ended output is also available for this purpose (see ). If frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. Lock Detector Output (PDIP Pin 8, SOG Pin ) Essentially a high level when loop is locked (fr, fv of same phase and frequency). pulses low when loop is out of lock. SW, SW2 Band Switch Outputs (PDIP Pins, 4; SOG Pins 4, ) SW and SW2 provide latched open drain outputs corresponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as V, independent of the supply voltage. These are typically used for band switch functions. A logic causes the output to assume a high impedance state, while a logic causes the output to be low. REFout Buffered Reference Oscillator Output (PDIP, SOG Pin ) Buffered output of on chip reference oscillator or externally provided reference input signal. POWER SUPPLY Positive Power Supply (PDIP, SOG Pin ) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (PDIP, SOG Pin 7) The most negative supply potential. This pin is usually ground. TYPIAL APPLIATIONS UHF/VHF TUNER OR ATV FRONT END M27/74 PRESALER 4. MHz M4 2 + /2 M48* DATA LK ENB KEYBOARD MOS MPU/MU M448 LED DISPLAY * The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure. Microprocessor ontrolled TV/ATV Tuning System with Serial Interface M4 2 through M48 2

12 2.6 MHz FM OS M2 2 PRESALER M4 2 + /2 M48* TO AM/FM OSILLATORS AM OS DATA LK ENB KEYBOARD MOS MPU/MU TO DISPLAY * The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 2. AM/FM Radio Synthesizer M4 2 Data Sheet ontinued on Page 2 M4 2 through M48 2 2

13 SEMIONDUTOR TEHNIAL DATA Interfaces with Dual Modulus Prescalers The M46 2 is programmed by a clocked, serial input, bit data stream. The device features consist of a reference oscillator, selectable reference divider, digital phase detector, bit programmable divide by N counter, 7 bit programmable divide by A counter, and the necessary shift register and latch circuitry for accepting serial input data. The M46 2 is an improved performance drop in replacement for the M46. Power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range On or Off hip Reference Oscillator Operation with Buffered Output ompatible with the Serial Peripheral Interface (SPI) on MOS MUs Lock Detect Signal Two Open Drain Switch Outputs Dual Modulus/Serial Programming 8 User Selectable R Values: 8, 64, 28, 26, 64,, 24, 248 N Range = to 2, A Range = to 27 Linearized Digital Phase Detector Enhances Transfer Function Linearity Two Error Signal Options: Single Ended (Three State) or Double Ended hip omplexity: 64 FETs or 626 Equivalent Gates 2 2 P SUFFIX PLASTI DIP ASE 78 DW SUFFIX SOG PAKAGE ASE 7D ORDERING INFORMATION M46P2 M46DW2 Plastic DIP SOG Package PIN ASSIGNMENT RA RA2 M RA OSout REFout TEST SW2 SW ENB DATA LK REV 8/ Motorola, Inc. M4 2 through M48 2

14 M46 2 BLOK DIAGRAM RA2 RA RA 2 x 8 ROM REFERENE DEODER 2 2 BIT R OUNTER LOK DETET OSout REFout M ONTROL LOGI fr fv PHASE DETETOR A 7 BIT A OUNTER 7 BIT N OUNTER PHASE DETETOR B SW2 ENB A OUNTER LATH N OUNTER LATH LATH SW DATA LK 7 BIT SHIFT REGISTER 7 BIT SHIFT REGISTER 2 BIT SHIFT REGISTER INPUT PINS Frequency Input (Pin ) PIN DESRIPTIONS Input to the positive edge triggered N and A counters. is typically derived from a dual modulus prescaler and is ac coupled into the device. For larger amplitude signals (standard MOS logic levels), dc coupling may be used. RA, RA, RA2 Reference Address Inputs (Pins 2,, 2) These three inputs establish a code deing one of eight possible divide values for the total reference divider, as deed by the table below: Reference Address ode RA2 RA RA Total Divide Value LK, DATA Shift Register lock, Serial Data Inputs (Pins, 2) Each low to high transition clocks one bit into the on chip bit shift register. The data input provides programming information for the bit N counter, the 7 bit A counter, and the two switch signals SW and SW2. The entry format is as follows: A LSB A OUNTER BITS A MSB N LSB N OUNTER BITS LAST DATA BIT IN (BIT NO. ) FIRST DATA BIT IN (BIT NO. ) ENB Latch Enable Input (Pin ) N MSB SW2 When high (), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW and SW2. When low (), ENB inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter programming and switch outputs. An on chip pull up establishes a continuously high level for ENB when no external signal is applied. ENB is normally low and is pulsed high to transfer data to the latches., OSout Reference Oscillator Input/Output (Pins, 8) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. TEST Factory Test Input (Pin 6) Used in manufacturing. Must be left open or tied to. SW M4 2 through M48 2 4

15 OUTPUT PINS Phase Detector A Output (Pin 6) Three state output of phase detector for use as loop error signal. Double ended outputs are also available for this purpose (see and ). Frequency fv > fr or fv Leading: Negative Pulses Frequency fv < fr or fv Lagging: Positive Pulses Frequency fv = fr and Phase oincidence: High Impedance State, Phase Detector B Outputs (Pins 4, ) These phase detector outputs can be combined externally for a loop error signal. A single ended output is also available for this purpose (see ). If frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. M Dual Modulus Prescale ontrol Output (Pin 8) Signal generated by the on chip control logic circuitry for controlling an external dual modulus prescaler. The M level will be low at the beginning of a count cycle and will remain low until the A counter has counted down from its programmed value. At this time, M goes high and remains high until the N counter has counted the rest of the way down from its programmed value (N A additional counts since both N and A are counting down during the first portion of the cycle). M is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + represent the dual modulus prescaler divide values respectively for high and low M levels, N the number programmed into the N counter, and A the number programmed into the A counter. Lock Detector Output (Pin ) Essentially a high level when loop is locked (fr, fv of same phase and frequency). pulses low when loop is out of lock. SW, SW2 Band Switch Outputs (Pins 4, ) SW and SW2 provide latched open drain outputs corresponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as V, independent of the supply voltage. These are typically used for band switch functions. A logic causes the output to assume a high impedance state, while a logic causes the output to be low. REFout Buffered Reference Oscillator Output (Pin 7) Buffered output of on chip reference oscillator or externally provided reference input signal. POWER SUPPLY Positive Power Supply (Pin ) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (Pin 7) The most negative supply potential. This pin is usually ground. M4 2 through M48 2

16 .2 MHz TYPIAL APPLIATIONS LOK DETET SIGNAL + 2 V NOTES AND V FM B + + V REFout LK OSout DATA RA2 RA RA M46 2 ENB SW SW2 M OPTIONAL LOOP ERROR SIGNAL + AM B + /2 M48 NOTE VO KEY BOARD MOS MPU/MU M2 2/2 DUAL MODULUS PRESALER TO DISPLAY DRIVER (e.g., M448) NOTES:. For AM: channel spacing = khz, R = 64 (code ). 2. For FM: channel spacing = 2 khz, R = 28 (code ).. The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter..2 MHz (NOTE ) Figure. AM/FM Radio Broadcast Synthesizer + V REFout LK OSout DATA NAV = OM = RA2 RA RA M46 2 ENB LOK DETET SIGNAL SW SW2 M + VO RANGE NAV: MHz OM T: 8..7 MHz OM R: MHz M7 NOTE VO R/T MOS MPU/MU HANNEL SELETION TO DISPLAY DRIVER (e.g., M448) M26 (NOTES 2 AND 4) 4/4 DUAL MODULUS PRESALER NOTES:. For NAV: fr = khz, R = 64 using.7 MHz lowside injection, Ntotal = For OM T: fr = 2 khz, R = 28, Ntotal = For OM R: fr = 2 khz, R = 28, using 2.4 MHz highside injection, Ntotal = A 2/ dual modulus approach is provided by substituting an M2 for the M26. The devices are pin equivalent.. A 6.4 MHz oscillator crystal can be used by selecting R = 28 (code ) for NAV and R = 26 (code ) for OM. 4. M2 + M combination may also be used to form the 4/4 prescaler.. The and outputs are fed to an external combiner/loop filter. See the Phase Locked Loop Low Pass Filter Design page for additional information. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. Figure 2. Avionics Navigation or ommunication Synthesizer M46 2 Data Sheet ontinued on Page 2 M4 2 through M48 2 6

17 SEMIONDUTOR TEHNIAL DATA Interfaces with Single Modulus Prescalers The M47 2 has a fully programmable 4 bit reference counter, as well as a fully programmable N counter. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. The M47 2 is an improved performance drop in replacement for the M47. Power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range Fully Programmable Reference and N ounters R Range = to 68 N Range = to 68 fv and fr Outputs Lock Detect Signal ompatible with the Serial Peripheral Interface (SPI) on MOS MUs Linearized Digital Phase Detector Single Ended (Three State) or Double Ended Phase Detector Outputs hip omplexity: 64 FETs or 626 Equivalent Gates 6 6 P SUFFIX PLASTI DIP ASE 648 DW SUFFIX SOG PAKAGE ASE 7G ORDERING INFORMATION M47P2 M47DW2 OSout Plastic DIP SOG Package PIN ASSIGNMENT fv REFout fr S/Rout ENB DATA LK REV 8/ Motorola, Inc. M4 2 through M48 2 7

18 M47 2 BLOK DIAGRAM 4 BIT SHIFT REGISTER ENB 4 REFERENE OUNTER LATH 4 LOK DETET fr 4 BIT R OUNTER OSout REFout PHASE DETETOR A 4 BIT N OUNTER 4 PHASE DETETOR B N OUNTER LATH fv DATA BIT ONTROL S/R 4 4 BIT SHIFT REGISTER S/Rout LK INPUT PINS Frequency Input (Pin 8) PIN DESRIPTIONS Input frequency from VO output. A rising edge signal on this input decrements the N counter. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as mv p p. For larger amplitude signals (standard MOS logic levels), dc coupling may be used. LK, DATA Shift lock, Serial Data Inputs (Pins, ) Each low to high transition of the clock shifts one bit of data into the on chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic selects the reference counter latch and a logic selects the N counter latch. The entry format is as follows: ONTROL LSB ENB Latch Enable Input (Pin ) FIRST DATA BIT INTO SHIFT REGISTER A logic high on this pin latches the data from the shift register into the reference divider or N latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the N latches are activated MSB if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches., OSout Reference Oscillator Input/Output (Pins, 2) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. OUTPUT PINS Single Ended Phase Detector A Output (Pin ) This single ended (three state) phase detector output produces a loop error signal that is used with a loop filter to control a VO. Frequency fv > fr or fv Leading: Negative Pulses Frequency fv < fr or fv Lagging: Positive Pulses Frequency fv = fr and Phase oincidence: High Impedance State, Double Ended Phase Detector B Outputs (Pins 6, ) These outputs can be combined externally for a loop error signal. A single ended output is also available for this purpose (see ). M4 2 through M48 2 8

19 If frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. fr, fv R ounter Output, N ounter Output (Pins, ) Buffered, divided reference and frequency outputs. The fr and fv outputs are connected internally to the R and N counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. Lock Detector Output (Pin 7) This output is essentially at a high level when the loop is locked (fr, fv of same phase and frequency), and pulses low when loop is out of lock. REFout Buffered Reference Oscillator Output (Pin 4) This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the system clock to a microprocessor controller. S/Rout Shift Register Output (Pin 2) This output can be connected to an external shift register to provide band switching, control information, and counter programming code checking. POWER SUPPLY Positive Power Supply (Pin 4) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (Pin 6) The most negative supply potential. This pin is usually ground. M47 2 Data Sheet ontinued on Page 2 M4 2 through M48 2

20 SEMIONDUTOR TEHNIAL DATA Interfaces with Dual Modulus Prescalers The M48 2 has a fully programmable 4 bit reference counter, as well as fully programmable N and A counters. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. The M48 2 is an improved performance drop in replacement for the M48. Power consumption has decreased and ESD and latch up performance have improved. Operating Temperature Range: 4 to 8 Low Power onsumption Through Use of MOS Technology. to. V Supply Range Fully Programmable Reference and N ounters R Range = to 68 N Range = to 2 Dual Modulus apability; A Range = to 27 fv and fr Outputs Lock Detect Signal ompatible with the Serial Peripheral Interface (SPI) on MOS MUs Linearized Digital Phase Detector Single Ended (Three State) or Double Ended Phase Detector Outputs hip omplexity: 64 FETs or 626 Equivalent Gates 6 6 P SUFFIX PLASTI DIP ASE 648 DW SUFFIX SOG PAKAGE ASE 7G ORDERING INFORMATION M48P2 M48DW2 OSout Plastic DIP SOG Package PIN ASSIGNMENT fv REFout fr M ENB DATA LK REV 8/ Motorola, Inc. M4 2 through M48 2 2

21 M48 2 BLOK DIAGRAM 4 BIT SHIFT REGISTER ENB 4 REFERENE OUNTER LATH 4 LOK DETET fr 4 BIT R OUNTER OSout REFout ONTROL LOGI PHASE DETETOR A 7 BIT A OUNTER 7 A OUNTER LATH BIT N OUNTER N OUNTER LATH PHASE DETETOR B fv DATA BIT ONTROL S/R 7 7 BIT S/R BIT S/R M LK PIN DESRIPTIONS A N INPUT PINS Frequency Input (Pin 8) Input frequency from VO output. A rising edge signal on this input decrements the A and N counters. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as mv p p. For larger amplitude signals (standard MOS logic levels), dc coupling may be used. LK, DATA Shift lock, Serial Data Inputs (Pins, ) Each low to high transition of the LK shifts one bit of data into the on chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic selects the reference counter latch and a logic selects the A, N counter latch. The data entry format is as follows: ONTROL LSB R FIRST DATA BIT INTO SHIFT REGISTER MSB ONTROL LSB MSB LSB ENB Latch Enable Input (Pin ) FIRST DATA BIT INTO SHIFT REGISTER A logic high on this pin latches the data from the shift register into the reference divider or N, A latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the N, A latches are activated if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches., OSout Reference Oscillator Input/Output (Pins, 2) These pins form an on chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from to ground and OSout to ground. may also serve as the input for an externally generated reference signal. This signal is typically ac coupled to, but for larger amplitude signals (standard MOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSout. MSB M4 2 through M48 2 2

22 OUTPUT PINS Phase Detector A Output (Pin ) This single ended (three state) phase detector output produces a loop error signal that is used with a loop filter to control a VO. Frequency fv > fr or fv Leading: Negative Pulses Frequency fv < fr or fv Lagging: Positive Pulses Frequency fv = fr and Phase oincidence: High Impedance State, Phase Detector B Outputs (Pins 6, ) Double ended phase detector outputs. These outputs can be combined externally for a loop error signal. A single ended output is also available for this purpose (see ). If frequency fv is greater than fr or if the phase of fv is leading, then error information is provided by pulsing low. remains essentially high. If the frequency fv is less than fr or if the phase of fv is lagging, then error information is provided by pulsing low. remains essentially high. If the frequency of fv = fr and both are in phase, then both and remain high except for a small minimum time period when both pulse low in phase. M Dual Modulus Prescale ontrol Output (Pin 2) This output generates a signal by the on chip control logic circuitry for controlling an external dual modulus prescaler. The M level is low at the beginning of a count cycle and remains low until the A counter has counted down from its programmed value. At this time, M goes high and remains high until the N counter has counted the rest of the way down from its programmed value (N A additional counts since both N and A are counting down during the first portion of the cycle). M is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + represent the dual modulus prescaler divide values respectively for high and low modulus control levels, N the number programmed into the N counter, and A the number programmed into the A counter. Note that when a prescaler is needed, the dual modulus version offers a distinct advantage. The dual modulus prescaler allows a higher reference frequency at the phase detector input, increasing system performance capability, and simplifying the loop filter design. fr, fv R ounter Output, N ounter Output (Pins, ) Buffered, divided reference and frequency outputs. The fr and fv outputs are connected internally to the R and N counter outputs respectively, allowing the counters to be used independently, as well as monitoring the phase detector inputs. Lock Detector Output (Pin 7) This output is essentially at a high level when the loop is locked (fr, fv of same phase and frequency), and pulses low when loop is out of lock. REFout Buffered Reference Oscillator Output (Pin 4) This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the system clock to a microprocessor controller. POWER SUPPLY Positive Power Supply (Pin 4) The positive power supply potential. This pin may range from + to + V with respect to. Negative Power Supply (Pin 6) The most negative supply potential. This pin is usually ground. M4 2 through M

23 M4X 2 FAMILY HARATERISTIS AND DESRIPTIONS MAXIMUM RATINGS* (Voltages Referenced to ) Symbol Parameter Value Unit D Supply Voltage. to +. V Vin, Vout Vout Iin, Iout Input or Output Voltage (D or Transient) except SW, SW2 Output Voltage (D or Transient), SW, SW2 (Rpull up = 4.7 kω) Input or Output urrent (D or Transient), per Pin. to +. V. to + V ± ma IDD, ISS Supply urrent, or Pins ± ma PD Power Dissipation, per Package mw Tstg Storage Temperature 6 to + TL Lead Temperature, mm from ase for seconds 26 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical haracteristics tables or Pin Descriptions section. Power Dissipation Temperature Derating: Plastic DIP: 2 mw/ from 6 to 8 SOG Package: 7 mw/ from 6 to 8 These devices contain protection circuitry to protect against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to these high impedance circuits. For proper operation, Vin and Vout should be constrained to the range (Vin or Vout) except for SW and SW2. SW and SW2 can be tied through external resistors to voltages as high as V, independent of the supply voltage. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ), except for inputs with pull up devices. Unused outputs must be left open. ELETRIAL HARATERISTIS (Voltages Referenced to ) Symbol Parameter Test ondition Power Supply Voltage Range V Min Max Min Max Min Max Unit V Iss Dynamic Supply urrent = = MHz, V p p ac coupled sine wave R = 28, A = 2, N = ma ISS Quiescent Supply urrent (not including pull up current component) Vin = or Iout = µa Vin Input Voltage, Input ac coupled sine wave mv p p VIL VIH VIL VIH Low Level Input Voltage, High Level Input Voltage, Low Level Input Voltage except, High Level Input Voltage except, Vout 2. V Vout. V Vout 6. V Vout. V Vout. V Vout 2.7 V Input dc coupled square wave Input dc coupled square wave Iin Input urrent (, ) Vin = or ± 2 ± ± 2 ± 2 ± 2 ± 22 µa IIL IIH Input Leakage urrent (Data, LK, ENB without pull ups) Input Leakage urrent (all inputs except, ) Vin =... µa Vin =... µa µa V V V V (continued) M4 2 through M48 2 2

24 D ELETRIAL HARATERISTIS (continued) Symbol Parameter Test ondition IIL Pull up urrent (all inputs with pull ups) V Min Max Min Max Min Max Unit Vin = µa in Input apacitance pf VOL VOH VOL VOH V(BR)DSS IOL IOH IOL IOH IOL IOL IOH Low Level Output Voltage OSout High Level Output Voltage OSout Low Level Output Voltage Other Outputs High Level Output Voltage Other Outputs Drain to Source Breakdown Voltage SW, SW2 Low Level Sinking urrent M High Level Sourcing urrent M Low Level Sinking urrent High Level Sourcing urrent Low Level Sinking urrent SW, SW2 Low Level Sinking urrent Other Outputs High Level Sourcing urrent Other Outputs IOZ Output Leakage urrent Iout µa Vin = Iout µa Vin = Iout µa Iout µa Rpull up = 4.7 kω V Vout =. V Vout =.4 V Vout =. V Vout = 2.7 V Vout = 4.6 V Vout = 8. V Vout =. V Vout =.4 V Vout =. V Vout = 2.7 V Vout = 4.6 V Vout = 8. V Vout =. V Vout =.4 V Vout =. V Vout =. V Vout =.4 V Vout =. V Vout = 2.7 V Vout = 4.6 V Vout = 8. V Vout = or Output in Off State ±. ±. ±. µa V V V V ma ma ma ma ma ma ma IOZ Output Leakage urrent SW, SW2 Vout = or Output in Off State ±. ±. ±. µa out Output apacitance Three State pf M4 2 through M

25 A ELETRIAL HARATERISTIS (L = pf, Input tr = tf = ns) Symbol Parameter V Guaranteed Limit 2 Guaranteed Limit 4 to 8 Unit tplh, tphl Maximum Propagation Delay, to M (Figures and 4) ns tphl Maximum Propagation Delay, ENB to SW, SW2 (Figures and ) ns tw Output Pulse Width,,, and with fr in Phase with fv (Figures 2 and 4) 2 to 2 2 to to 7 2 to 26 2 to 2 to 8 ns ttlh Maximum Output Transition Time, M (Figures and 4) ns tthl Maximum Output Transition Time, M (Figures and 4) ns ttlh, tthl Maximum Output Transition Time, (Figures and 4) ns ttlh, tthl Maximum Output Transition Time, Other Outputs (Figures and 4) ns SWITHING WAVEFORMS INPUT % tplh OUTPUT % tphl %,, * * fr in phase with fv. Figure. Figure 2. tw ANY OUTPUT ttlh % % tthl Figure. TEST POINT TEST POINT OUTPUT OUTPUT kω DEVIE UNDER TEST L* DEVIE UNDER TEST L* * Includes all probe and fixture capacitance. Figure 4. Test ircuit * Includes all probe and fixture capacitance. Figure. Test ircuit M4 2 through M48 2 2

26 TIMING REQUIREMENTS (Input tr = tf = ns unless otherwise indicated) Symbol Parameter V Guaranteed Limit 2 Guaranteed Limit 4 to 8 Unit fclk Serial Data lock Frequency, Assuming 2% Duty ycle NOTE: Refer to LK tw(h) below (Figure 6) dc to. dc to 7. dc to dc to. dc to 7. dc to MHz tsu Minimum Setup Time, Data to LK (Figure 7) ns th Minimum Hold Time, LK to Data (Figure 7) ns tsu Minimum Setup Time, LK to ENB (Figure 7) ns trec Minimum Recovery Time, ENB to LK (Figure 7) 2 2 ns tw(h) Minimum Pulse Width, LK and ENB (Figure 6) ns tr, tf Maximum Input Rise and Fall Times Any Input (Figure 8) µs SWITHING WAVEFORMS tw(h) DATA % LK, ENB % *Assumes 2% Duty ycle. ANY OUTPUT tt % % * 4 fclk Figure 6. tf tsu LK ENB % th LAST LK tsu % Figure 7. trec PREVIOUS DATA LATHED FIRST LK Figure 8. M4 2 through M

27 FREQUENY HARATERISTIS (Voltages References to, L = pf, Input tr = tf = ns unless otherwise indicated) Symbol Parameter Test ondition fi Input Frequency (, ) R 8, A, N 8 Vin = mv p p ac coupled sine wave R 8, A, N 8 Vin = V p p ac coupled sine wave R 8, A, N 8 Vin = to dc coupled square wave V Min Max Min Max Min Max Unit NOTE: Usually, the PLL s propagation delay from to M plus the setup time of the prescaler determines the upper frequency limit of the system. The upper frequency limit is found with the following formula: f = P / (tp + tset) where f is the upper frequency in Hz, P is the lower of the dual modulus prescaler ratios, tp is the to M propagation delay in seconds, and tset is the prescaler setup time in seconds. For example, with a V supply, the to M delay is 7 ns. If the M228A prescaler is used, the setup time is 6 ns. Thus, if the 64/6 ratio is utilized, the upper frequency limit is f = P / (tp + tset) = 64/(7 + 6) = 744 MHz MHz MHz MHz fr REFERENE OS R fv FEEDBAK ( N) * VH VL VH VL VH HIGH IMPEDANE VL VH VL VH VL VH VL VH = High Voltage Level. VL = Low Voltage Level. * At this point, when both fr and fv are in phase, the output is forced to near mid supply. NOTE: The generates error pulses during out of lock conditions. When locked in phase and frequency the output is high and the voltage at this pin is determined by the low pass filter capacitor. Figure. Phase Detector/Lock Detector Output Waveforms M4 2 through M

28 DESIGN ONSIDERATIONS PHASE LOKED LOOP LOW PASS FILTER DESIGN A) R VO ωn = ζ = KφKVO NR Nωn 2KφKVO F(s) = Rs + B) R R2 VO ωn = ζ = KφKVO N(R + R2) N.. ωn R2 +. KφKVO F(s) = R2s + (R + R2)s + ) R R R2 _ + A VO ωn = ζ = KφKVO NR ωnr2 2 R2 ASSUMING GAIN A IS VERY LARGE, THEN: R2s + F(s) = Rs NOTE: Sometimes R is split into two series resistors, each R 2. A capacitor is then placed from the midpoint to ground to further filter and. The value of should be such that the corner frequency of this network does not significantly affect ωn. The and outputs swing rail to rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. DEFINITIONS: N = Total Division Ratio in feedback loop Kφ (Phase Detector Gain) = /4π for Kφ (Phase Detector Gain) = /2π for and KVO (VO Gain) = 2π f VO VVO for a typical design wn (Natural Frequency) 2πfr (at phase detector input). Damping Factor: ζ REOMMENDED READING: Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley Interscience, 7. Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley Interscience, 8. Blanchard, Alain, Phase Locked Loops: Application to oherent Receiver Design. New York, Wiley Interscience, 76. Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley Interscience, 8. Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood liffs, NJ, Prentice Hall, 8. Berlin, Howard M., Design of Phase Locked Loop ircuits, with Experiments. Indianapolis, Howard W. Sams and o., 78. Kinley, Harold, The PLL Synthesizer ookbook. Blue Ridge Summit, PA, Tab Books, 8. AN, Phase Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 7. AR24, Phase Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design, 87. M4 2 through M

29 RYSTAL OSILLATOR ONSIDERATIONS The following options may be considered to provide a reference frequency to Motorola s MOS frequency synthesizers. Use of a Hybrid rystal Oscillator ommercially available temperature compensated crystal oscillators (TXOs) or crystal controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing µa at MOS logic levels may be direct or dc coupled to. In general, the highest frequency capability is obtained utilizing a direct coupled square wave having a rail to rail ( to ) voltage swing. If the oscillator does not have MOS logic levels on the outputs, capacitive or ac coupling to may be used. OSout, an unbuffered output, should be left floating. For additional information about TXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master atalog, the Gold Book, or similar publications. Design an Off hip Reference The user may design an off chip crystal oscillator using Is specifically developed for crystal oscillator applications, such as the M26 MEL device. The reference signal from the MEL device is ac coupled to. For large amplitude signals (standard MOS logic levels), dc coupling is used. OSout, an unbuffered output, should be left floating. In general, the highest frequency capability is obtained with a direct coupled square wave having rail to rail voltage swing. Use of the On hip Oscillator ircuitry The on chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure. Rf 2 R* FREQUENY SYNTHESIZER OSout * May be deleted in certain cases. See text. Figure. Pierce rystal Oscillator ircuit For =. V, the crystal should be specified for a loading capacitance, L, which does not exceed 2 pf for frequencies to approximately 8. MHz, 2 pf for frequencies in the area of 8. to MHz, and pf for higher frequencies. These are guidelines that provide a reasonable compromise between I capacitance, drive capability, swamping variations in stray and I input/output capacitance, and realistic L values. The shunt load capacitance, L, presented across the crystal can be estimated to be: L = inout + a + o + in + out where in = pf (see Figure ) out = 6 pf (see Figure ) a = pf (see Figure ) O = the crystal s holder capacitance (see Figure 2) and 2 = external capacitors (see Figure ) in Figure. Parasitic apacitances of the Amplifier 2 a out NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal). RS LS S Figure 2. Equivalent rystal Networks The oscillator can be trimmed on frequency by making a portion or all of variable. The crystal and associated components must be located as close as possible to the and OSout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray capacitance should be added to the value for in and out. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 2. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. R in Figure limits the drive level. The use of R may not be necessary in some cases (i.e., R = Ω). To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at OSout. (are should be taken to minimize loading.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R must be increased in value if the overdriven condition exists. The user should note that the oscillator start up time is proportional to the value of R. Through the process of supplying crystals for use with MOS inverters, many crystal manufacturers have developed expertise in MOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful (see Table ). Re Xe O 2 2 M4 2 through M48 2 2

30 Table. Partial List of rystal Manufacturers Name Address Phone United States rystal orp. rystek rystal Statek orp. 6 Mcart Ave., Ft. Worth, TX 76 2 rystal Dr., Ft. Myers, FL 7 2 N. Main St., Orange, A 2668 (87) 2 (8) 6 2 (74) 6 78 NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. REOMMENDED READING Technical Note TN 24, Statek orp. Technical Note TN 7, Statek orp. E. Hafner, The Piezoelectric rystal Unit Deitions and Method of Measurement, Proc. IEEE, Vol. 7, No. 2 Feb., 6. D. Kemper, L. Rosine, Quartz rystals for Frequency ontrol, Electro Technology, June, 6. P. J. Ottowitz, A Guide to rystal Selection, Electronic Design, May, 66. OVERVIEW DUAL MODULUS PRESALING The technique of dual modulus prescaling is well established as a method of achieving high performance frequency synthesizer operation at high frequencies. Basically, the approach allows relatively low frequency programmable counters to be used as high frequency programmable counters with speed capability of several hundred MHz. This is possible without the sacrifice in system resolution and performance that results if a fixed (single modulus) divider is used for the prescaler. In dual modulus prescaling, the lower speed counters must be uniquely configured. Special control logic is necessary to select the divide value P or P + in the prescaler for the required amount of time (see modulus control deition). Motorola s dual modulus frequency synthesizers contain this feature and can be used with a variety of dual modulus prescalers to allow speed, complexity and cost to be tailored to the system requirements. Prescalers having P, P + divide values in the range of / 4 to 28/ 2 can be controlled by most Motorola frequency synthesizers. Several dual modulus prescaler approaches suitable for use with the M42 2, M46 2, or M48 2 are: M2 M2 M2 M2 M26 M27 M28 M222A M22A DESIGN GUIDELINES / 6 8/ / 2/ 4/ 4 64/ 6 28/ 2 64/6 or 28/2 64/6 or 28/2 44 MHz MHz MHz 22 MHz 22 MHz 22 MHz 2 MHz. GHz 2. GHz The system total divide value, Ntotal (NT) will be dictated by the application: NT = frequency into the prescaler frequency into the phase detector = N P + A N is the number programmed into the N counter, A is the number programmed into the A counter, P and P + are the two selectable divide ratios available in the dual modulus prescalers. To have a range of NT values in sequence, the A counter is programmed from zero through P for a particular value N in the N counter. N is then incremented to N + and the A is sequenced from through P again. There are minimum and maximum values that can be achieved for NT. These values are a function of P and the size of the N and A counters. The constraint N A always applies. If Amax = P, then Nmin P. Then NTmin = (P ) P + A or (P ) P since A is free to assume the value of. NTmax = Nmax P + Amax To maximize system frequency capability, the dual modulus prescaler output must go from low to high after each group of P or P + input cycles. The prescaler should divide by P when its modulus control line is high and by P + when its M is low. For the maximum frequency into the prescaler (fvomax), the value used for P must be large enough such that:. fvomax divided by P may not exceed the frequency capability of (input to the N and A counters). 2. The period of fvo divided by P must be greater than the sum of the times: a. Propagation delay through the dual modulus prescaler. b. Prescaler setup or release time relative to its M signal. c. Propagation time from to the M output for the frequency synthesizer device. A sometimes useful simplification in the programming code can be achieved by choosing the values for P of 8, 6, 2, or 64. For these cases, the desired value of NT results when NT in binary is used as the program code to the N and A counters treated in the following manner:. Assume the A counter contains a bits where 2a P. 2. Always program all higher order A counter bits above a to.. Assume the N counter and the A counter (with all the higher order bits above a ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the N counter). The MSB of this hypothetical counter is to correspond to the MSB of N and the LSB is to correspond to the LSB of A. The system divide value, NT, now results when the value of NT in binary is used to program the new n + a bit counter. By using the two devices, several dual modulus values are achievable (shown in Figure ). M4 2 through M48 2

31 M DEVIE A DEVIE B DEVIE DEVIE A M B M2 2/ 2 M2 2/ M2 4/ 4 M8 M4 / 4/ 4 OR 8/ 8 8/ 8 64/ 6 OR 28/ 2 / 8/ 8 NOTE: M2, M2, and M2 are pin equivalent. M2, M26, and M27 are pin equivalent. Figure. Dual Modulus Values M4 2 through M48 2

32 PAKAGE DIMENSIONS P SUFFIX PLASTI DIP ASE (M47 2, M48 D) 6 H A 8 G F D 6 PL B S K.2 (.) M T SEATING T PLANE A M J L M NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.M, ONTROLLING DIMENSION: INH.. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MO FLASH.. ROUNDED ORNERS OPTIONAL. INHES MILLIMETERS DIM MIN MAX MIN MAX A B D..2.. F G. BS 2.4 BS H. BS.27 BS J K L M S P SUFFIX PLASTI DIP ASE 77 2 (M4 2) 8 B NOTES:. POSITIONAL TOLERANE OF LEADS (D), SHALL BE WITHIN.2 (.) AT MAXIMUM MATERIAL ONDITION, IN RELATION TO SEATING PLANE AND EAH OTHER. 2. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL.. DIMENSION B DOES NOT INLUDE MO FLASH. H F G A D N SEATING PLANE K L M J DIM A B D F G H J K L M N MILLIMETERS MIN MAX BS BS INHES MIN MAX BS BS.2.4 M4 2 through M48 2 2

33 P SUFFIX PLASTI DIP ASE 7 2 (M4 2, M42 2) 28 B NOTES:. POSITIONAL TOLERANE OF LEADS (D), SHALL BE WITHIN.2mm (.) AT MAXIMUM MATERIAL ONDITION, IN RELATION TO SEATING PLANE AND EAH OTHER. 2. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL.. DIMENSION B DOES NOT INLUDE MO FLASH. 4 A H G F D N K SEATING PLANE M L J DIM A B D F G H J K L M N MILLIMETERS MIN MAX BS BS..2 INHES MIN MAX BS BS.2.4 P SUFFIX PLASTI DIP ASE 78 (M46 2) 2 -A- B L NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.M, ONTROLLING DIMENSION: INH.. DIMENSION L TO ENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MO FLASH. -T- SEATING PLANE G E F D 2 PL N K.2 (.) M T A M J 2 PL M.2 (.) M T B M DIM A B D E F G J K L M N MIN..24. INHES MAX BS..7. BS BS.2.4 MILLIMETERS MIN MAX BS BS BS.. M4 2 through M48 2

34 DW SUFFIX SOG PAKAGE ASE 7D 4 (M4 2, M46 2) 2 A B X P. (.2) M B M NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.M, ONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INLUDE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXESS OF D DIMENSION AT MAXIMUM MATERIAL ONDITION. 2X D. (.2) M T A S B S 8X G K T SEATING PLANE J F M R X 4 MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F...2. G.27 BS. BS J K M 7 7 P....4 R DW SUFFIX SOG PAKAGE ASE 7F 4 (M4 2, M42 2) -A- -T X D. (.2) M T A S B S 26X G K 4X P R X 4 -B- -T- SEATING PLANE. (.2) M B M M J F NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.M, ONTROLLING DIMENSION: MILLIMETER.. DIMENSION A AND B DO NOT INLUDE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXESS OF D DIMENSION AT MAXIMUM MATERIAL ONDITION. DIM A B D F G J K M P R MILLIMETERS MIN MAX BS. BS INHES MIN MAX M4 2 through M48 2 4

35 DW SUFFIX SOG PAKAGE ASE 7G 2 (M47 2, M48 2) A 6 6X D 4X G B. (.2) M T A S B S 8 K 8X P T SEATING PLANE. (.2) M J F M B M R X 4 NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.M, ONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INLUDE MO PROTRUSION. 4. MAXIMUM MO PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXESS OF D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F...2. G.27 BS. BS J K M 7 7 P....4 R M4 2 through M48 2

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