NVTFS4C10N. Power MOSFET. 30 V, 7.4 m, 47 A, Single N Channel, 8FL

Transcription

1 NVTFS4CN Power MOSFET 3 V, 7.4 m, 47 A, Single N Channel, 8FL Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses NVTFS4CNWF Wettable Flanks Product NVT Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain to Source Voltage V DSS 3 V Gate to Source Voltage V GS ±2 V Continuous Drain Current R JA (Notes, 2, 4) T A = 2 C T A = C I D.3.8 A Power Dissipation R JA (Notes, 2, 4) Continuous Drain Current R JC (Notes, 3, 4) Power Dissipation R JC (Notes, 3, 4) Steady State T A = 2 C P D 3. W T A = C. T C = 2 C I D 47 A T C = C 33 T C = 2 C P D 28 W T C = C 4 W Pulsed Drain Current T A = 2 C, t p = s I DM 96 A Operating Junction and Storage Temperature T J, T stg to +7 C Source Current (Body Diode) I S 3 A Single Pulse Drain to Source Avalanche Energy (, V GS = V, I L =.2 A, L =. mh) Lead Temperature for Soldering Purposes (/8 from case for s) E AS 26 mj T L 26 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction to Case (Drain) (Notes, 3) R JC.4 Junction to Ambient Steady State (Notes, 2) R JA C/W. The entire application environment impacts the thermal resistance values shown; they are not constants and are valid for the specific conditions noted. 2. Surface mounted on FR4 board using 6 mm 2, 2 oz. Cu Pad. 3. Assumes heat sink sufficiently large to maintain constant case temperature independent of device power. 4. Continuous DC current rating. Maximum current for pulses as long as one second is higher but dependent on pulse duration and duty cycle. V (BR)DSS R DS(on) MAX I D MAX 3 V G (4) WDFN8 ( 8FL) CASE AB 4C WF A Y WW 7.4 V 4. V N Channel MOSFET D ( 8) S (,2,3) 47 A MARKING DIAGRAM S D S XXXX D S AYWW D G D = Specific Device Code for NVMTS4CN = Specific Device Code of NVTFS4CNWF = Assembly Location = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page of this data sheet. Semiconductor Components Industries, LLC, 24 July, 24 Rev. 2 Publication Order Number: NVTFS4CN/D

2 NVTFS4CN ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = 2 A 3 V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS / T J 4. Zero Gate Voltage Drain Current I DSS V GS = V,. V DS = 24 V A Gate to Source Leakage Current I GSS V DS = V, V GS = ±2 V ± na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = 2 A V Threshold Temperature Coefficient V GS(TH) /T J 4. mv/ C Drain to Source On Resistance R DS(on) V GS = V I D = 3 A V GS = 4. V I D = A 8.8 m Forward Transconductance g FS V DS =. V, I D = A 43 S Gate Resistance R G T A = 2 C. CHARGES AND CAPACITANCES Input Capacitance C ISS 993 Output Capacitance C OSS V GS = V, f = MHz, V DS = V 74 pf Reverse Transfer Capacitance C RSS 63 Capacitance Ratio C RSS /C ISS V GS = V, V DS = V, f = MHz.64 Total Gate Charge Q G(TOT). Threshold Gate Charge Q G(TH).8 Gate to Source Charge Q GS V GS = 4. V, V DS = V; I D = 3 A 2.6 nc Gate to Drain Charge Q GD 6. Gate Plateau Voltage V GP 3.2 V Total Gate Charge Q G(TOT) V GS = V, V DS = V; I D = 3 A 9.3 nc SWITCHING CHARACTERISTICS (Note 6) Turn On Delay Time t d(on) 9. Rise Time t r V GS = 4. V, V DS = V, 3 Turn Off Delay Time t d(off) I D = A, R G = 3. 4 ns Fall Time t f 7. Turn On Delay Time t d(on) Rise Time t r V GS = V, V DS = V, 2 Turn Off Delay Time t d(off) I D = A, R G = 3. 8 Fall Time t f 4. DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD VGS = V, I S = A Reverse Recovery Time t RR 23.3 Charge Time t a V GS = V, dis/dt = A/ s, 2.7 Discharge Time t b I S = 3 A.6 Reverse Recovery Charge Q RR 8.3 nc. Pulse Test: pulse width 3 s, duty cycle 2%. 6. Switching characteristics are independent of operating junction temperatures. mv/ C ns V ns 2

3 NVTFS4CN TYPICAL CHARACTERISTICS V 4.2 V to V V 3.6 V 3.4 V 3.2 V 3. V 2.8 V 2.6 V V DS = V.. T J = C V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On Resistance vs. V GS I D = 3 A R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS = 4. V V GS = V Figure 4. On Resistance vs. Drain Current and Gate Voltage 7 R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) I D = 3 A V GS = V I DSS, LEAKAGE (na) V GS = V T J = C T J = 8 C T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature Figure 6. Drain to Source Leakage Current vs. Voltage 3

4 NVTFS4CN TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) C iss C oss C rss V GS = V V GS, GATE TO SOURCE VOLTAGE (V) Q gs Q gd Q T 2 V DD = V V GS = V I D = 3 A Q g, TOTAL GATE CHARGE (nc) Figure 7. Capacitance Variation Figure 8. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = V I D = A V GS = V R G, GATE RESISTANCE ( ) t d(on) t r t d(off) Figure 9. Resistive Switching Time Variation vs. Gate Resistance t f I S, SOURCE CURRENT (A) V GS = V V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current. V GS = V T C = 2 C R DS(on) Limit Thermal Limit Package Limit.. Figure. Maximum Rated Forward Biased Safe Operating Area. ms. ms ms ms dc 4

5 NVTFS4CN TYPICAL CHARACTERISTICS TRANSIENT THERMAL RESISTANCE ( C/W). Duty Cycle = % 2% % % 2% % R JA Single Pulse R JC Single Pulse JC, Infinite Heat Sink Assumption JA, 6 mm 2, 2 oz Cu Pad, Single Layer on FR4. t, PULSE TIME (s) Figure 2. Thermal Response 6 G FS (S) I PEAK, DRAIN CURRENT (A) T J(initial) = 8 C T J(initial) = 2 C I D (A) T AV, TIME IN AVALANCHE (s) Figure 3. G FS vs. I D Figure 4. Avalanche Characteristics ORDERING INFORMATION NVTFS4CNTAG NVTFS4CNWFTAG Device Package Shipping WDFN8 (Pb Free) WDFN8 (Pb Free) / Tape & Reel / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D.

6 NVTFS4CN PACKAGE DIMENSIONS. C. C 8X b. C A B. C 4X L E2 E3 2X.2 C D A B 2X D E E c TOP VIEW A SIDE VIEW DETAIL A e/2 4 K M.2 C WDFN8 3.3x3.3,.6P CASE AB ISSUE D 6X e DETAIL A 4X A C SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. PACKAGE OUTLINE MILLIMETERS DIM MIN NOM MAX A A.. b c..2.2 D D BSC D E E BSC E e.6 BSC G.3.4 K.6.8 L.3.43 L.6.3 M SOLDERING FOOTPRINT* 8X.42 MIN BSC BSC E BSC PITCH INCHES NOM 4X.66 MAX G 8 D2 BOTTOM VIEW L DIMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada [email protected] N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NVTFS4CN/D

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