Optimization on Re-sputtering of Barrier layer on Metallization for Cu interconnect

Transcription

1 Optimization on Re-sputtering of Barrier layer on Metallization for Cu interconnect Abstract Re-sputtering is applied in the deposition of barrier process for copper interconnect, and controlling its process stability is very important to improve the layers quality. The factors which influence the re-sputtering process are analyzed and discussed. Followed by discussion on the re-sputtering function, the experiments results show that the impedance of sputtering chamber is the key factor which determines the re-sputtering performance. Based on this conclusion, a scheme is proposed to improve the performance of the barrier and seed process. Keywords: Re-sputtering, metallization, copper interconnect, barrier, copper seed layer, impedance 1. Introduction As the width of metal line decreased, aluminum (Al) began to show the bottleneck to IC technical performance. So copper (Cu) stepped into the consideration of metal line interconnect. [1] In 1997, damascene structures came out and made the copper process into a road of rapid development. [2] In the copper metallization scheme, barrier and seed (B/S) are the key processes to deposit metal film. [3] Conformal step coverage with minimal thickness at bottom of via or line is not easy to obtain by using traditional Physical Vapor Deposition(PVD) technique through plasma zone. [4] Re-sputtering then was developed and applied to metal barrier deposition. In process, DC bias is used to make positive particle bombard Ta film to reduce thickness of the film. Using Re-sputtering process, via resistance can be tunable according to device performance specification. However until now there is no effective technique to control the stability of the re-sputtering. This paper disclosed the main factors that influenced the re-sputtering effect and summarized the techniques to improve the performance of the re-sputtering process.

2 2. Experimental Experimental Method (a) (b) DC bias normal (c) DC bias abnormal Figure 1: (a) DC bias trend chart ; (b) WAT OOC with TEM; (c) TEM pictures of via bottom for normal and abnormal DC bias AMAT ENDURA PVD system was used to prepare the Ta film.4-point probe (RS75) was used to measure the sheet resistance of the barrier. Transmission Electron Microscope (TEM) was used to analyze film thickness. Wafer Acceptance Testing (WAT) was performed to measure the electrical parameters. After data collection, DC bias has been found having great effect on the re-sputtering. Figure shown that Bigger fluctuation of DC bias (Fig.1a) can cause corresponding unstable via resistance which lead to WAT out of control (Fig.1 b). This can be confirmed as via bottom coverage shift of barrier metal (Fig.1c) Figure 2: The feed through of AC bias During process, AC bias is applied to wafer through pedestal as shown in Fig.2, and it has two phases of negative and positive. Because plasma includes negative electrons and positive ions, in positive cycle, AC will attract electrons to pedestal and wafer; whereas it will attract positive ions in negative cycle. But since the mass of electrons is much less than that of positive ions, electrons can get higher speed to move to pedestal and wafer than positive ions by same force of electric field. With the accumulation of lots of electrons, the negative potential will be formed on the wafer surface. That is DC bias. It is the result of AC

3 bias power and chamber impedance. Effect of AC power AC power is defined as RF power which is used to enhance the directivity of metal ions deposited into via or trench. With the normal re-sputtering condition, the effect of AC power on re-sputtering process was studied. The experiment was conducted in this way: change the AC power from 0w to 400w while keeping other parameters invariable, corresponding film property and re-sputtering performance were collected. Effect of chamber impedance Figure 3: scheme of PVD chambers circuit As shown in Fig.3, chamber impedance is a function of several factors. In order to investigate impedance character, AC bias is kept invariable and data of DC bias, impedance and etch rate(sputtering rate) could be got. 3. Result and Discussion Effect of AC bias 6 R s (Ω.cm) Rs EtchRate Sputtering Rate (A/sec) AC Power (V) Figure 4: AC Bias vs. sputtering rate and R s. Fig.4 shows that Rs and sputtering rate trend up while the AC power increases. Rs is measured by RS75 for film sheet resistance. During the measurement, the test length is invariable. 4-point probes are for measurement. Two of them provide source of current and another two are probes for voltage measurement. With current and voltage, Rs is retained through calculation. The resistance is the character of material which can be calculated by the following formula: R=ρ L/S (1)

4 Where R is the electrical resistance of test chain, and ρ is the electrical resistivity of the tested film, L is the length of test chain and S is the area of cross section of tested film. Rs proportion to R. Both ρ and L are invariable, and S is determined by thickness of metal film. Thicker thickness can lead to bigger S and then smaller Rs. As shown in Fig.4, RS trends up with the AC power increasing. Based on above description and formula, it can be got that thickness will be thinner when S decreases.during re-sputter process, AC power induces DC bias on wafer surface. It drives the positive metal particle to bombard surface of metal film. The action can sputter off some metal film and reduce the thickness of the film. So higher AC power will cause thinner thickness of metal film. Sputtering rate can be used to analyze the efficiency of AC power as shown in Fig.4 too. So the thinner the thickness, the higher sputtering rate; and the higher AC power, the higher sputtering rate. So AC power can affects the thickness and determine the sputtering rate. Usually sputtering rate is the standard parameter to measure the re-sputter, and RS is the result to see the performance of the re-sputter. Experiment shows that AC power can effectively affects RS and determines the performance of re-sputter. Effect of the impedance of the chamber AC power was set at 400W in different chamber, and DC bias displayed on the control screen of tool was recorded as listed on Table 1. Impedance can not be obtained directly, but it is a invariable parameter of chamber once a AC power is applied to chamber. It can be calculated by using the following formula. R=U 2 /P (2) Where R is the impedance of sputtering chamber, U is DC bias and P is AC power. Then the effect of chamber impedance on the sputtering rate was shown in Fig. 5. Table 1: Sputtering rate variation with the change of chamber impedance of DC bias. AC DC Bias Impedance of Sputtering Power (V) chamber (Ω) rate (A/sec) (W)

5 5.6 SputteringR 5 point AA Smoothing of Data2_SputteringR Sputtering Rate (A/sec) Impedance of Sputtering Chamber (Ω) Figure 5: Effect of chamber impedance on sputtering rate The result in Fig.5 shows that sputtering rate trends down with the impedance increases. Sputtering rate is obtained by ionized atoms sputtering the metal film. The density of ionized atoms modulates the thickness of metal layer which has been sputtered away. Higher density causes more loss. During the sputtering, the ionized atoms movement induces current. So higher density of ionized atoms can cause higher current and higher sputtering rate. Thus current can be used to check the sputtering rate. I = P / R (3) Where I is sputtering current, P is AC power and R is the impedance of sputtering chamber. If the AC power (P) is unchanged, the current is determined by R, which is chamber impedance. So in the circuit, chamber impedance is equal to the load resistance in the DC circuit, which influences the current of the whole circuit. For chamber it determines the sputtering rate and efficiency of the AC power. In Fig.3 the chamber impedance includes wafer pedestal gap, gap between plasma and wafer, the plasma and RF return assembly. Wafer pedestal gap is determined by the voltage which chucks the wafer. The dimension of wafer and pedestal is unchanged and the distance determines the value of the capacity. High voltage can reduce the gap between wafer and pedestal in theory. Gap between plasma and wafer, plasma and RF return assembly have the factors of spacing from target to wafer and process kits. DC voltage is added to target. With the help of RF, it ionizes the Ar to form plasma. And process kits control the shape of plasma. So suitable spacing can give a good capacity. then good impedance can be obtained. 4. Summary Experiment proved that chamber impedance is the key factor which decides the re-sputtering performance for the deposition of barrier layer in copper interconnect. Through adjusting wafer-chuck-voltage and space from target to wafer, and applying process kits with good quality, the impedance can be improved and then good re-sputtering performance can be achieved to improve the process quality for the deposition for barrier layer. Reference [1] Wang Yangyuan, Kang Jinfeng. Development of VLSI Interconnect Integration Technology 一 Copper Interconnect with Low k Dielectrics J.Chinese Journal of Semiconductors, 2002, 23( 11): [2] Application of Copper Interconnect and Damascene Technology in Deep Submicron IC. RESEARCH&PROGRESS OF SSE V 01.21_No.4 Nov 2001

6 [3] S. M. Rossnagel, Directional and ionized physical deposition for microelectronics applications, J. Voc, Sci, Techool,1998; (5); B16. [4] Prabu Gopalraja, Suraj Rengarajan, John Forster. Advanced Engineering of PVD and ALD based Barriers for Submicron Device Generations in Dual Damascene Copper Interconnects. SEMICONDUCTOR TECHNOLOGY, 2003 Vol.28 No.4 P.42-46