Simulation of Embedded Components in PCB Environment and Verification of Board Reliability
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1 Simulation of Embedded Components in PCB Environment and Verification of Board Reliability J. Stahr, M. Morianz AT&S Leoben, Austria M. Brizoux, A. Grivon, W. Maia Thales Global Services Meudon-la-Forêt, France
2 Contents Introduction Analysis of properties of embedded components FEM Stress Simulation of embedded components Analysis of embedded PCB mechanical behaviour Conclusions & perspectives 2
3 Process Flow embedded core 3
4 Project Idea Methodology for the simulation Characterization of component materials with mechanical stress testing Characterization of PCB process influences on dies and passive devices Finite element modeling of simple embedding build Validation of simulated build up Component stress evaluation Cracks occurred by embedding of ceramic capacitors related to build up technology To gain knowledge about behavior of Si-dies and passive devices under harsh process environment (high temperature and pressure) during lamination 4
5 Analysis of properties of embedded components Strength tests on 2x2 mm 2 plates with ball-on-three-balls (B3B) test (biaxial loading) and evaluation with Weibull statistics 5
6 Advantage of this test method 4 ball stress test for biaxial loading analysis is a proven method to determine stress forces High repeatability of measurement method Influence of measurement setup is very low (see Weibull graph) 6
7 Analysis of properties of embedded components 7
8 Different characteristic strength on Si-side and Metal side 8
9 Simplified model of an embedded component in a PCB build 9
10 FEM Stress Simulation of embedded components Embedded Si-chip Embedded ceramic component 10
11 Analysis of Embedded PCB Mechanical Behaviour Objective & Test Plan Characterize the incidence of the PCB build-up and base material on thermo-mechanical stresses Dedicated test vehicle assemblies with various constructions submitted to ATC -55 C/+125 C, continuous electrical monitoring Analysis of the PCB parameter effects on the time-tofailure of BGA/QFN components 11
12 Test Vehicle Overview PCB with embedded components and assembled daisy-chain BGA/QFN - 1.0mm-pitch BGA256, 17x17mm² 16/board - 0.5mm-pitch QFN68, 10x10mm² 16/board 12
13 Test Plan Variables 15 stack-up configurations Two halogen-free FR-4 materials Mat-C (Tg : 180 C), Mat-D (Tg : 155 C) Two resin contents 34% - 43% (Mat-C), 43% - 55% (Mat-D) Several PCB thicknesses Ranging from 1.2mm up to 2.4mm 13
14 Results (BGA) 15 plots grouped ±10% of thickness ± 5% on Nf(63,2%) Base material effect Less than 12% on Nf(63,2%) Resin-content effect Less than 5% on Nf(63,2%) Moderate impact of PCB buildup on BGA 2 nd -level reliability 14
15 Results (QFN) Incomplete test results ±10% of thickness Up to ± 45% on Nf(63,2%) Base material effect Up to 300% on Nf(63,2%) Resin-content effect Very few failures for 2116 Strong impact of PCB build-up on QFN 2 nd -level reliability 15
16 Summary of test results The PCB construction has a variable impact on the board-level reliability of components Moderate effect for 1.0mm-pitch BGA packages Strong effect for 0.5mm-pitch QFN packages On-going work Analysis of the incidence of embedded components 16
17 Conclusion of the simulation Differences in stress & bending behavior of ceramic and Si-dies during PCB lamination process Curing profile influences stress input Reduction of stresses & deformations Combination of Young s modulus and coefficient of thermal expansion of components Gap around the components Design of the core & geometry of the components Key parameters for the mechanical loading of the components can be shown. 17
18 Next steps & outlook Process simulation and validation with dedicated build up layers used for embedding technology Adding of micro via interconnects and layer structures to the simulation model Initial work has been done on thermo-mechanical board simulation and the validation of interconnect reliability of assembled components on PCB with embedded components. Further simulation work and the evaluation of the embedded component reliability is in progress to merge the results and extract guide lines for reliable design 18
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