Application Note AN-1160

Transcription

1 Application Note AN-60 Design of Resonant Half-Bidge convete using IRS795(,) Contol IC By Helen Ding Table of Contents. Intoduction & Device Oveview. LLC Resonant Half Bidge Convete Opeation 3. Tansfome and Resonant Cicuit Design 4. IRS795 Passive Components Design 5. IRS795 Powe Loss Calculation 6. MOSFET Selection Guide 7. Opeating Wavefoms and Efficiency 8. Layout Guidelines and Example 9. Appendix Symbol list Refeences AN-60

2 . Intoduction and Device Oveview The IRS795(,) is a self oscillating half-bidge dive IC fo esonant half-bidge DC-DC convete applications fo use up to 600V. It has a fixed 50% duty-cycle and vey wide opeating fequency ange. The maximum switching fequency can go up to 500kHz. The fequency can be pogammed extenally though the RT and CT pins. The IC offes flexibility to pogam the minimum opeating fequency, the maximum opeating fequency and the fequency sweep at powe up fo the softstat function. The dead time is pogammed by the CT capacito. The pogammable dead-time allows the use to optimize the system with the minimum body-diode conduction time fo highe efficiency unde full load, while keeping ZVS switching unde no load condition. The IC offes ove cuent potection using the on-state esistance of the low-side MOSFET. The potection theshold is V fo IRS795 and it is 3V fo IRS795 IC. The IC can be disabled by extenally pulling the voltage at the CT/SD pin below its enable voltage theshold. The IC entes sleep mode and only consumes mico-powe when disabled. IRS795(,) packing in a 8-pin package, it s easy to use, and dastically educes extenal component count fo a high efficiency low cost powe supply. Figue is the typical application schematic of IRS795(,): VIN DC BUS R R Dbs Rcc D3 Rmax Dss Rss Css RT CDC CT 3 4 U VCC RT CT/SD COM IRS795 VB 8 HO 7 VS 6 LO 5 Cbs Rg Rg M M L Lm D COUT LOAD C D RTN Rled U Rbias Cf Cf Rf Rs U3 TL43 Rs Figue : IRS795(,) typical application cicuit AN-60

3 The pinout of IRS795(,) is shown below. Lead Assignment Pin# Symbol Desciption VCC Supply voltage VCC VB 8 3 RT CT/SD Oscillato timing esisto Oscillato timing capacito/shutdown 3 RT CT/SD IRS795 HO VS COM LO Gound Low-side gate dive 4 COM LO VS HO High-side gate dive etun/ HV Cuent Sense High-side gate dive 8 VB High-side floating supply voltage Figue : IRS795(,) IC pin assignment. LLC Resonant Half-Bidge Convete Opeation The inceasing populaity of the LLC esonant convete in its half-bidge implementation is due to its high efficiency, low switching noise and ability to achieve high powe density. This topology is also the most attactive topology fo font-end DC bus convesion. It utilizes the magnetizing inductance of the tansfome to constuct a complex esonant tank with Buck Boost tansfe chaacteistics in the soft-switching egion. The typical powe stage schematic fo this topology is shown below. M D Vin HO VS L n:: M Lm LO COUT LOAD C D Figue 3: Typical schematic of a DC-DC half-bidge esonant convete Devices M and M opeate at 50% duty cycle and the output voltage is egulated by vaying the switching fequency of the convete. The convete has two esonant fequencies a lowe esonant fequency (given by L m, L, C and the load) and a fixed highe seies esonant fequency F (given by L and C only). The two bidge devices M and M can be soft-switched fo the entie AN-60 3

4 load ange by opeating the convete unde inductive load mode (ZVS egion). It can be eithe above o below the esonant fequency F. The typical AC tansfe chaacteistics fo a LLC tank esonant convete ae shown in Figue 4. The goup of cuve indicates the gain unde diffeent load conditions. Figue 4: Typical fequency esponse of a LLC esonant convete The chaacteistics of a LLC esonant convete can be divided into thee egions based on the 3 diffeent modes of opeation. The fist egion is fo switching fequency above the esonant fequency F. F π L C In egion (the puple shaded aea) the switching fequency is highe than esonant fequency F. The convete opeation is vey simila to a seies esonant convete. Hee L m neve esonates with esonant capacito C ; it is clamped by the output voltage and acts as the load of the seies esonant tank. This is the inductive load egion and the convete is always unde ZVS opeation egadless of the load condition. In the nd egion, the switching fequency is highe than the lowe esonant fequency but lowe than F. Region is in the pink shaded aea in Figue 4. The lowe esonant fequency vaies with load, so the bounday of egion and egion 3 taces the peak of the family load vs. gain cuves. In this complex egion, the LLC esonant opeation can be divided into two time intevals. In the fist time inteval, L esonates with C and L m is clamped by output voltage. When the cuent in the esonant Fo this AC analysis, only the fundamental component of the squae-wave voltage input to the esonant netwok contibutes to the powe tansfe to output. The tansfome, ectifie and filte ae eplaced by an equivalent AC esistance, Rac. AN-60 4

5 inducto L esonates back to the same level as the magnetizing cuent, L and C stop esonating. L m now paticipates in the esonant opeation and the second time inteval begins. Duing this time inteval, dominate esonant components change to C and L m in seies with L. The ZVS opeation in egion is guaantees by opeating the convete to the ight side of the load gain cuve. Fo a switching fequency below esonant F, it could falls in eithe egion o egion 3 depends on the load condition. In the ZCS ange 3 below f, the LLC esonant convete opeates in capacitive mode; M and M ae unde had switching and have high switching losses. So ZCS opeation should always be avoided. The typical opeating wavefoms of the 3 modes ae demonstated in Figue 5 to Figue 7. Figue 5: Typical wavefom of above esonant ZVS switching Figue 6: Typical wavefom of below esonant ZVS switching AN-60 5

6 The wavefoms indicate that the cuent in seconday ectifie diodes moves fom continuous cuent mode (CCM) to discontinuous cuent mode (DCM) when the switching fequency vaies fom above esonant ZVS to below esonant ZVS due to load inceasing. The ipple voltage on the esonant capacito C also inceases in the below esonant ZVS mode. Figue 7: Typical wavefom of below esonant ZCS switching In ZCS mode, the two switching devices M and M ae tuned off unde zeo cuent condition. The tun-on of the two switches is had switching (none ZVS). The tun-on switching loss is high especially unde high voltage bus voltage. The esonant capacito C also has high voltage stess. ZCS opeation should always be avoided. The typical voltage convesion atio of a LLC esonant convete is shown in Figue 8. Q - Low (no load) nvout Vin Q - High (full load) Fequency modulation low line Fequency modulation high line nvout Vinmin nvout Vinmax Ove load o Shot Cicuit fmin F fmax Fequency Figue 8: Typical voltage convesion atio of a LLC esonant convete AN-60 6

7 With a fixed input voltage, the convete vaies switching fequency to egulate the output voltage ove load ange keeping the same convesion atio ove the family of cuves with diffeent Q. Given a fixed load condition, the convete vaies switching fequency along that load line to egulate output voltage ove input voltage ange the convesion atio inceases when input voltage deceases. To design the LLC esonant half-bidge convete, we use the Fist Hamonic Appoximation (FHA) to get equivalent cicuit. All the components ae put to pimay side to simply the analysis. The load equals to a esisto R ac that is in paallel with tansfome pimay inductance L m. M D Vin C L n:: M Lm COUT LOAD D Vin π C L 4 n Vout π Vf und Lm Rac Rac n 8 RLOAD π Figue 9: The FHA equivalent cicuit The input voltage of the esonant tank is a squae wave with amplitude equals to the input DC voltage Vin. The fundamental component of the squae wavefom is: Vin sin( ϖ t) π The output voltage of the esonant tank is the voltage acoss L m. It is vey close to a squae wavefom with amplitude swinging fom n Vout to + n Vout. So the fundamental component of the output squae wavefom is: 4 n Vout sin( ϖ t) π AN-60 7

8 The powe dissipation on the equivalent AC esisto is equal to the powe dissipation of R LOAD esisto, thus it can be witten as: Vout R LOAD 4 n Vout π Rac Reaange the fomula and get the equivalent AC esisto: 8 n Rac π R LOAD The tansfe atio of the equivalent cicuit can be obtained as following: j ω Lm Rac M j ω L + j ω Lm+ Rac j ω Lm Rac + j ω C j ω Lm + Rac Re-wite the fomula, M + L Lm ω Lm C + jω L Rac j ω C Rac With the following definitions, M can be simplified. F π L C, Fsw x, F x ϖ πfsw π x F, L C Lm n R k, Rac LOAD L 8, π πf L Q Rac πf C Rac M + + j Q k x x x O, M + k x + Q x x AN-60 8

9 Pe Figue 9, M is also equals to the output voltage to input voltage atio: M 4 n Vout Vout π n Vin Vin π So we have the convesion atio of output voltage Vout to input voltage Vin: Vout Vin M n 3. Tansfome and Resonant Cicuit Design This section povides the details of how to calculate the key components of a LLC convete, take a 4V output 40W powe supply as an example. The system input data Paamete Unit Desciption Value Vin max V The maximum DC bus voltage 430 Vin min V The minimum DC bus voltage 350 Vin nom V The nominal DC bus voltage 390 Vout V The DC output voltage 4 Iout A The output load cuent 0 F KHz The esonant fequency 00 Fmax KHz The maximum switching fequency 50 Dmax The maximum duty-cycle 0.5 Tss ms The soft stat time 0 Fss KHz The soft stat fequency 300 Tansfome ETD49 Note: Typically set Fmax < xf as the paasitic capacitance in the system intoduced a 3d esonant fequency which could cause the output voltage to incease with switching fequency at no load if the maximum switching fequency is highe than the limit. Step : Calculate the tansfome tuns atio Vinmax n, Vout 430 n The tansfome tuns atio is calculated with the maximum input voltage to make sue the output is always unde egulation, including the wost case - high-line voltage and no load condition. AN-60 9

10 Usually the tansfe atio of the powe stage is highe than the theoetical calculated value. This is because of the paasitic capacitance in the system (the coupling capacito between tansfome windings and the junction capacitos of output diodes) affects the esonance, especially at zeo load whee the switching fequency is much highe than the esonant fequency. So it s ecommended to choose the n to be slightly highe than the calculated value especially if the contolle has no bust mode to keep egulation at high line and zeo load condition. n 9 Step : Choose k value k is the atio between the tansfome magnetic inductance and the esonant inductance. Smalle k value gives steepe Gain cuve, especially at the below esonant ZVS egion as shown in Figue 0. The output voltage is moe sensitive to fequency vaiation with smalle k facto. 3.5 k5.5 k Figue 0: k facto A highe k value esults in highe magnetic inductance and thus lowe magnetizing cuent in the tansfome pimay winding that means lowe ciculating powe losses. Howeve, highe magnetic inductance could also cause non-zvs switching at high line and zeo load condition whee the ciculating cuent is too small to fully chage / dischage the VS node duing dead-time. The ecommend ange of k is fom 3 to 0. Hee k 5 is chosen. Step 3: Calculate Qmax to stay in ZVS opeation at the maximum load unde the minimum input voltage The input impedance of the equivalent esonant cicuit (Figue 9) is given by: AN-60 0

11 Zin j ω L + + j ω C j ω Lm Rac j ω Lm + Rac Zin Q Rac k x Q + k x Q x k + j x + x + k x Q To keep the convete woking in soft switching mode, the opeating point should always in the ZVS egion as shown in Figue 4. The ZVS ZCS bounday line is defined by the phase angle of Zin Ф(Zin) 0 (the bounday condition between capacitive and inductive load), i.e. the imaginay pat of Zin is zeo. With this condition we can calculate the maximum Q which allows the convete to stay in ZVS. The maximum Q happens at the minimum input voltage and the maximum load. Qmax k + k Mmax Mmax k + k Vout n Vinmin Vout n Vinmin Whee Mmax is the maximum convesion atio at the minimum input voltage, Q max Step 4: Calculate the minimum switching fequency The minimum switching fequency happens at the maximum load and minimum input voltage with the pevious calculated maximum Qmax. As Qmax is defined by Im(Zin)0, The Fmin can be calculated with: x k x + x + k x Qmax 0 xmin + k Mmax + k n Vout Vinmin x min F min x min F KHz Step 5: Calculate L, C and L m As Qmax happens at the maximum load, so the esonant components L, C and L m can be calculated pe the Qmax value that had obtained in step 3: AN-60

12 C R LOAD Vout 4V. 4Ω Iout 0A 8 n R Rac LOAD Ω π π Q max Rac L uh π F π 00K 4. Q max Rac π 00K π F nf Choose the neaest standad capacito value fo C, C nf Recalculate F to keep the same Qmax with the selected C capacito. F 00. Khz C Q max Rac 7 Recalculate L with the selected C and F. Q max Rac L 3uH F π The actual L value should be lowe than the calculated value to stay in ZVS egion. Now calculate L m value based on L and the k facto that peset in step : π Lm L k uH Please note that L m is the magnetizing inductance of the tansfome. The total pimay inductance value L p is the sum of L m and L. L p Lm + L 678uH To simplify the powe stage, the esonant inducto can be integated into the powe tansfome by using slotted bobbin, also called two-section o two-chambe bobbin. By sepaate the pimay winding and the seconday winding in the two chambes, the coupling between pimay and seconday is much wose than the single section bobbin. Thus the leakage inductance is high and can be used as esonant inducto. The component count is lowe and the coppe loss is also smalle. Figue is the pictue of a two-section bobbin. Figue : -section Tansfome AN-60

13 When measue the inductance of a tansfome, the pimay inductance L p is measued with all seconday windings opened. And the leakage inductance is measued with all the seconday windings shoted. Step 6: Calculate tansfome pimay and seconday tuns The standad half-bidge equation fo the tansfome tuns numbe calculation is used hee: Vin min D max Np B Ae F min With B 0. T, Ae.cm (ETD49), F 60KHz min, Vinmin 350V, D max Np Np 35 Ns 3.89 n 9 The numbe of tuns must be an intege and should be highe than the calculated value, so choose Ns 4 Then ecalculate Np: Np Ns n Step 7: Calculate tansfome pimay and seconday cuent Most LLC convetes design the minimum switching fequency to be below the esonant fequency F, in ode to maintain output voltage egulation at low line and full load. When the switching fequency is lowe than the esonant fequency F, the cuent wavefom is shown as in Figue. Figue : Tansfome pimay cuent at full load and minimum input voltage I is the cuent whee the esonant cuent in L meets the magnetizing cuent in L m. This is also the point whee C and L finish esonance fo the fist half-peiod of F. At this point, thee is no moe enegy deliveed to the load and the output diodes ae off. The C stats to esonate with L + L m until the switching MOSFETs change states. I can be calculated as: AN-60 3

14 n Vout I 0. 95A Lm F The peak and RMS value of pimay cuent can be estimated as: Iout π Ipi( pk) + I. 99A n Ipi( pk) IpiRMS. 4A The RMS cuent is calculated by assuming pue sinusoid cuent wavefom. So the actual pimay RMS cuent is highe than the calculated value. The cuent in each seconday winding is vey close to half-sinusoid, thus the peak and RMS cuent can be estimated by: Iout π Ispk 5. 7A Iout π Isms 7. 85A 4 The wie gauge of pimay and seconday windings should be selected popely accoding to the calculated RMS cuent. Step 8: Calculate esonant capacito voltage The C wavefom is shown as in Figue 3: Figue 3: Typical esonant tank voltage and cuent wavefoms IL m is the magnetizing cuent of tansfome pimay, not including the cuent which is deliveed to the seconday load though an ideal tansfome in paallel with L m. The diffeence between IL and IL m is the output cuent. AN-60 4

15 M Ideal Tansfome D C L M IL ILm Lm COUT LOAD Iout/n D Figue 4: L m and ideal tansfome The VC voltage eaches its peak when L cuent is cossing zeo and it is at the mid of input voltage when L cuent eached its peak. The C voltage is at the maximum value when VS node is zeo and it is at the minimum value when VS node is equals to Vin. So VC min and VC max can be calculated as: VC n Vout + Ipi( pk) min max VC Vin n Vout Ipi( pk) The peak to peak voltage ipple of VC is VC max -VC min. VC pk _ pk n Vout + Ipi( pk) L C L C L C Vin It can be seen that the maximum peak-to-peak voltage happens at the maximum load and the minimum DC input Vinmin, the switching fequency is at the minimum Fmin. In this example: 3uH Vcpk _ pk 9 4V +.99A 350V 368V nf The esonant capacito C can be selected accoding to the capacitance value, togethe with its voltage and cuent ating. Polypopylene film capacito is pefeed to use fo lowe powe loss. Please note the polypopylene film capacito is ated unde DC voltage o 50Hz AC voltage and has voltage deating at high fequency and high ambient tempeatue. The ability of withstanding high fequency voltage is limited by themal (powe dissipation) and peak cuent capability. Usually the deating stats at 85~90C ambient and is not a concen. But a capacito with highe voltage ating AN-60 5

16 should be chosen if the ambient tempeatue is highe than 85C. Below is an example of EPCOS MKP capacito B36 (630Vdc/400Vac). Figue 5: Vms vs. fequency cuve of MKP capacito Ta<90 C 4. IRS795 Passive Components Design Step 9: Calculate the minimum dead-time to keep ZVS switching at zeo load at the maximum input voltage Fo esonant half-bidge convete, the switching fequency goes to the maximum unde no load at the maximum input voltage. Theoetically when the switching fequency is above the esonant fequency F, the opeation is ZVS switching. Howeve, above esonance is only one of the necessay conditions fo ZVS. The othe condition is the equivalent paasitic capacito of the halfbidge midpoint (junction capacito of VS node) to be fully (dis-)chaged within the dead-time peiod. Figue 6 demonstates if the dead-time is not sufficient, the tun-on of the MOSFET has hadswitching even though the convete is woking unde the below esonant ZVS mode. AN-60 6

17 Figue 6: ZVS and none-zvs wavefom of egion opeation To keep the convete always woking unde ZVS condition, it is necessay to calculate the minimum time that equied to fully (dis-)chaging the VS equivalent capacito duing the two switches inteleaving peiod (dead-time). As the equivalent capacito is (dis-)chaged by the ciculating cuent in the tansfome pimay winding, so the wost case happens at the maximum input voltage and zeo load condition whee the tansfome cuent is at minimum. At zeo load, thee is no cuent tansfe to the seconday side and the cuent in the tank is just the magnetizing cuent of tansfome. In each half-cycle, it is a linea staight line as shown in Figue 7. VS Pimay cuent Figue 7: Tansfome pimay cuent at zeo load So the pimay cuent unde this condition can be calculated as: n Vout I ' pi( pk) 4F max ( L + Lm) I ' pi( pk) 0. 53A AN-60 7

18 The total equivalent junction capacito C HB of VS node is shown in Figue 8. IRS795 VB HO M Coss_eff_ VCC VS C L Cw ell Css_eff M Lm LO Coss_eff_ Cs COM Figue 8: VS Equivalent junction capacito CHB Coss _ eff + Css _ eff + CWell + Cs It includes: The effective Coss of the two MOSFETs (both high-side and low-side); The Coss_eff as defined in the MOSFET datasheet is the effective capacitance of MOSFET that gives the same chaging time as a fixed capacito while V DS is ising fom 0 to 80% of V DS. So the Coss_eff of a 500V MOSFET is defined unde 0 to 400V V DS which fits to this application. The effective Css of the low-side MOSFET; The Css of MOSFET is typically defined at VDS5V. The Css capacitance value educes as VDS voltage inceasing. So the effective Css can be chose as ½ o /3 of Css. The stay capacitance Cwell of IRS795(,); The stay capacitance of IRS795(,) is the high-side well capacitance of the 600V dive. The value of the stay capacito is aound 5pF. The snubbe capacito Cs (if any) that is connected to the VS node. Fo example, the Coss_eff of MOSFET STF3NM50N is 0pF, Css is 5pF, and thee is no snubbe capacito to the VS node, the (dis-)chaging time of VS node can be calculated as: Coss _ eff 0 pf, Css _ eff. 5 pf, C Well 5pF, Cs 0 pf C Vin max Tch I' pi( pk) HB Tch 85ns The dead-time calculation should also include the gate dive falling time. The MOSFET tun-off timing diagam is shown in Figue 9, which using LO and M as an example. In the fist time inteval t, gate voltage dischages to a plateau voltage V m, and both VDS voltage and I D cuent AN-60 8

19 stay unchanged in t. As long as MOSFET gate voltage eaches the mille plateau V m, mille cap Cgd is dischaged and VDS voltage stats inceasing. Due to the nonlineaity of Coss capacito, VDS voltage incease slowly at the beginning, then the slope becomes steepe at highe VDS voltage. The mille plateau is the flat potion of gate dive cuve. It vaies with dain cuent. MOSFET tuns off at a elative low cuent level in LLC application, the mille plateau is vey close to the gate tun off theshold Vgs(th). The timing that is inteested fo the dead time calculation is t, as the chaging time of the VS node (i.e. VDS of M) stating fom t is aleady included in the Tch calculation. In t, VDS voltage is 0V, and MOSFET gate equals to a constant capacito load to the IC. So the dischage time t can be calculated based on the RC time constant of the gate dive loop. V ' m t RC geq ln V Whee, R + R + R Rdown _ eff C geq g gfet ( Qg Qgd Qgs), Please efe to Figue. Vgs Vm V ' m Vgs( th) V G Vcc, IRS795(,) gate output voltage is clamped to Vcc voltage R down_eff : IRS795(,) gate dive effective pull down esistance (6Ω) R g :is the extenal MOSFET gate dive esisto R gfet: MOSFET gate input esistance G Figue 9: MOSFET tun-off equivalent cicuit and timing diagam STF3NM50 gate equivalent capacito is.3nf, MOSFET intenal gate esisto is 5Ω, Vgs(th) is 3V. Thus if Vcc5V, Rg0Ω, gate dischage time t is: t 78. 4ns The dead-time should be longe than the sum of Tch and t. Fo expeience, it is ecommended to add 50ns to the calculated value. The minimum dead-time T DT is then given by: T DT Tch + t + 50ns 33ns Fo most of the design, it s not ecommended to have a dead-time that is longe than us, as longe dead-time leads to highe body-diode powe losses at full load. So if the calculated dead-time is too long, go back to step and choose a smalle k value. Once the system paametes ae defined, the passive components aound the IRS795(,) as shown in Figue 0 can be calculated. AN-60 9

20 Figue 0: IRS795(,) two-pin Oscillato 3 TDT CT 3pF C T capacito should be equal o bigge than the calculated value fo ZVS opeation. Choose a standad capacito value fo C T. C T 390 pf Calculate the actual dead-time pe the selected C T value: V t DT ( 0.85CT + 40 pf) 37. 5ns ma Calculate R T pe the minimum switching fequency Fmin and C T : R kω 3 F min t 0 T R T esisto should be smalle than the calculated value to keep ZVS opeation. DT Calculate Rmax pe the maximum switching fequency Fmax and C T, R T : Re q kω, 3 F max t 0 Calculate Rss with the desied soft-stat fequency: DT Rsseq kω, 3 Fss t 0 Calculate Css based on the desied soft-stat time: Tss Css 3 Rss DT R R max R T T Re q Re q RT Rsseq Rss RT Rsseq In sleep mode o fault mode, RT pin is dischaged to 0V. A diode Dss is put in paallel with Rss to fast dischage Css when IC is shutdown o in fault mode. This is to make sue the system still has soft stat when IRS795(,) estats quickly. Dss can be any geneal pupose low voltage (0V) and low cuent (00mA) diode. The bootstap capacito C BS is used to hold V BS supply voltage fo the high-side dive. The value of C BS is ecommended to be 00nF to 0nF. Bigge C BS capacito causes highe chaging cuent AN-60 0

21 duing statup and should be avoid. IRS795(,) doesn t have integated bootstap MOSFET. A 600V/A fast ecovey diode is equied fo bootstap. 5. IRS795 Powe Loss Calculation 5. Low voltage static loss that caused by quiescent cuent Pd Vcc Iqcc whee Iqcc is.5ma maximum pe IRS795(,) datasheet. 5. The gate dive powe losses The gate dive losses of IRS795(,) ae the losses when diving the two extenal MOSFETs M and M. In ZVS mode, MOSFET V DS voltage is 0V pio to the gate tuns on, so the Mille chage Qgd should be subtacted fom the total gate chage. Futhe, at ZVS opeation, the MOSFET is as a constant capacito load to the dive. The equivalent capacito value equals to the Cgs+Cgd at VDS0V condition, which can be obtained fom the gate chage cuve in a MOSFET data sheet. It is indeed the slope facto of the gate chage cuve whee VGS is above the mille plateau voltage Vm, as shown in Figue. C geq ( Qg Qgd Qgs) Vgs Vm Figue : MOSFET gate chage cuve and equivalent gate capacitance at ZVS mode Typically the Qg, Qgd and Qgs value ae specified unde 0V V GS voltage, Vm is the flat potion voltage of the gate chage cuve. Fo example, STF3NM50 Qg30nC, Qgd5nC, Qgs5nC, Vm5.7V, its gate equivalent capacito in ZVS is.3nf. The total gate chage in ZVS mode is popotional to the gate voltage: Qgz Cgeq V G AN-60

22 IRS795(,) gate output voltage is clamped to Vcc voltage. So the total gate dive losses of both high-side and low-side can be calculated by: Pd Pd + Pd Cgeq Vcc Fsw The total gate dive losses ae dissipated in dive IC IRS795(,) and the extenal gate dive esisto including the MOSFET intenal gate esisto. The powe loss in IRS795(,) is popotional to the esisto divide value: Rup _ eff Pd ( Rup _ eff + Rg + R g FET Whee, R g :is the extenal MOSFET gate dive esisto Rdown _ eff + Rdown _ eff + Rg + R R up_eff : IRS795(,) gate dive effective pull up esistance (40Ω) R down_eff : IRS795(,) gate dive effective pull down esistance (6Ω) R gfet: MOSFET gate input esistance gfet Pd ) The gate dive pull-up and pull-down esistance used fo powe loss calculation ae given below: Rup 40Ω, Rdown 6Ω. They ae bigge than datasheet specification (with is defined unde 0mA cuent) as they ae the equivalent pull-up and pull-down esistance unde high gate cuent. 5.3 The CMOS switching losses The switching loss in low voltage logic cicuit is popotional to the switching fequency and supply voltage Vcc: Pd 3 Vcc Fsw Qcmos Fo IRS795(,), Qcmos 6nC ~ 0nC 5.4 The high voltage switching losses The switching losses in high voltage level-shift cicuit: Pd 4 ( Vcc + Vin) Fsw Qp Vin is the input bus voltage. Qp is the chage absobed by the level shifte. Fo IRS795(,), Qp is nc unde 300V to 430V bus voltage. 5.5 An example of powe loss calculation The total powe loss in IRS795(,) is the sum of Pd to Pd4. Pd _ total Pd+ Pd + Pd3+ Pd4 An example of powe loss calculation with Vcc5V, maximum switching fequency 50KHz, MOSFETs STF3NM50N, input bus voltage 400V, extenal gate esisto 0ohm: Pd 37.5mW Pd 57mW, Pd 79.5mW Pd3 8mW Pd 4 4.5mW Pd _ total 59.5mW AN-60

23 It can be seen that the high voltage switching loss Pd4 and gate dive loss Pd ae the main souce of total powe losses. Pd4 is popotional to switching fequency and HV bus voltage. Fo 400V DC BUS voltage, IRS795(,) can diectly dives big MOSFETs (Cgeq 4.7nF) up to 50KHz switching fequency. It is necessay to clamp the Vcc supply voltage to 5V o lowe to educe gate dive losses when the fequency goes to 300KHz while diving big MOSFETs. Fo 300KHz to 500KHz switching fequency and 400V applications, it is ecommended to use extenal dive. IC opeation cuent Icc can be obtained by the total low-voltage powe loss and Vcc voltage: Icc ( Pd+ Pd + Pd3) / Vcc 6. MOSFET Selection Guide The powe MOSFET should be selected pe the beakdown voltage and R DSON value. In addition, the body diode evese ecovey chaacteistic also plays impotant ole to the selection. The convete usually has a few switching cycles that is unde had switching at the beginning of statup. This is because the esonant capacito and output capacitos ae fully dischaged. In this case, longe evese ecovey time could cause shoot though between the two MOSFETs. Thus a MOSFET with fast evese ecovey diode is pefeed. As the esonant half-bidge has ZVS switching, the tun-on loss is negligible. If not switching unde vey high fequency ( 50Khz), the majo powe loss in MOSFET comes fom the conduction loss. The maximum conduction loss can be calculated as: Pcon Iqms Rdson Ipi( pk) Whee Iqms, and is the MOSFET on-state esistance at the system maximum allowable junction tempeatue. The calculation of the tun-off loss of MOSFET is complicated due to none lineaity of Coss unde diffeent VDS voltage. Thus we use the estimated fomula: C HB Vin Fsw Poff 4 The total powe loss in each MOSFET equals to Pcon + Poff. IRS795(,) uses the Rdson of low side MOSFET fo cuent sensing and ove cuent potection. The poduct family povides two choices on diffeent ove cuent potection level: the OCP theshold of IRS795 is V and IRS795 is 3V. Typically the IRS795 is good fo ovesized MOSFET whee a lowe Rdson fo bette efficiency and the IRS795 is good fo cost effective MOSFET whee the Rdson is bigge. A quick estimation fo OCP theshold is to use.5 to 3 times of the maximum dain cuent times the Rdson of MOSFET. At statup, the MOSFET cuent could be a few times highe than the nomal woking cuent. To pevent false tiggeing of ove cuent potection when using lage Rdson MOSFET, it is ecommended to extend the soft-stat time to tens of Tj AN-60 3

24 7. Opeating Wavefoms and Efficiency of the Refeence Design The specification of the efeence design: Paamete Desciption Value Vin max The maximum DC bus voltage 430V Vin min The minimum DC bus voltage 350V Vin nom The nominal DC bus voltage 390V Vout The DC output voltage 4V Iout The output load cuent 6A Vout The DC output voltage V Iout The output load cuent 6A F The esonant fequency 00KHz Fmax The maximum switching fequency 50KHz Dmax The maximum duty-cycle 0.5 Tss The soft stat time 30ms Fss The soft stat fequency 300KHz Tansfome ETD49 Design analysis esult: Resonant tank components CnF, L5uH, Lm500uH, k4 Tansfome Np36, N4V4, NV, n9 IRS795 components CT390pF, RT8k, Rmax4k, Rss3.9k, Css3.3uF AN-60 4

25 7. Schematic JP Heade 3 F 5A/50V C 0.uF/75V-X 65VAC N RNTC 5 t L C Cs DNP R C 0.uF/75V-X B 4 GBU4J-BPMS-ND C3 0.33uF/630V + C4 70uF/450V Rdisch 50K Rstat 70k VCC JP3 Heade COM 33uF/35V Rstat 70k CDC VCC uf Rstat3 70k CVcc Dz 8V 00nF CVcc 5k Rvcc RMAX 3.9k RT RSS 3.3uF CSS N448 D5 N448 DSS RT 8k 390pF CT CT Dbs MURS60 U VCC VB RT HO CT/SD VS COM LO IRS795 COM HO LO Cbs 0nF Dg N448 Dg N448 Rg Rg Rx 4.7 Rx 4.7 DNP STF3NM50N Q Rgs DNP Do Not Populate DNP STF3NM50N Q Rgs Vbus VS nf/kv COM W Jumpe 60uH.nF/50V U TLP6 VTR TX D STPS3000 D STPS3000 COMP DNPDo not Populate U3 TL43 DNP Rled 5.6k Rbias D3 0TQ040 D4 0TQ040 Rbias.k Cf 00nF Cout Cout6 Rled.k Cf DNP Rf 47k.5mF/5V mf/35v.5mf/5v mf/35v Cout Cout7 Rs5 3.9k Rs4 5k mf/35v Cout3 Rs 33k Rs 0 Rs3 3.74k Lf Lf 000uF/5V 3.3uH/0A 3.3uH/0A Cout8 FB mf/35v Cout4 00nF 00nF 470 Cout5 Cout9 560 Rpl Rpl 4V COM V COM JP4 Heade 6 JP5 Heade 6 Figue IRS795 Refeence Design Schematic The efeence boad has input ectifie and filte, so it can take eithe DC o AC input. The DC input ange is 350V~430V, the AC input voltage ange is 50Vac~300Vac. The dummy loads at 4V and V output ae fo coss-egulation pupose. AN-60 5

26 7. BOM Designato Desciption Quantity Value/Rating Vendo Pat# B Single Phase Bidge Rectifie 600V/4A DIGIKEY GBU4J-BPMS-ND C, C X Safety Capacito 00nF/75VAC DIGIKEY P054-ND C3 Metal Poly Capacito 0.33uF/630V DIGIKEY P45-ND C4 Electolytic Bulk Capacito TS-HC 70uF/450V DIGIKEY EET-HCW7LA Cbs 06 Geneal Pupose Ceamic SMD 0nF/50V DIGIKEY ND Cf, Cout5, Cout9, CVcc 06 Geneal Pupose Ceamic SMD 4 00nF/50V DIGIKEY ND CDC Electolytic Capacito FM Radial 33uF/35V DIGIKEY P3475-ND Cf Not Used Cout, Cout, Cout3, Cout4 Aluminium Electolytic Capacito 05 C 4 000uF/35V DIGIKEY ND Cout6, Cout7 Aluminium Electolytic Capacito 05 C 500uF/5V DIGIKEY ND Cout8 Aluminium Electolytic Capacito 05 C 000uF/ 5V DIGIKEY ND C Polypopylene Capacito High Ripple nf/kv DIGIKEY ND Cs 50VAC Y Safety Ceamic Disc Capacito.nF/50V DIGIKEY ND CSS 06 Geneal Pupose Ceamic SMD 3.3uF/6V DIGIKEY ND CVcc 06 Geneal Pupose Ceamic SMD uf/5v DIGIKEY ND CT 06 Geneal Pupose Ceamic SMD ±5% 390pF/50V DIGIKEY ND D, D TO0AB Powe Schottky Rectifie 00V/30A DIGIKEY STPS3000CT D3, D4 TO0AC Powe Schottky Rectifie 40V/0A DIGIKEY 0TQ040PBF-ND D5, Dg, Dg, DSS Fast Recovey Diode DO V/0.3A DIGIKEY N448DICT-ND Dbs Fast Recttifie diode SMB 600V/A DIGIKEY MURS60-FDICT-ND Dz Zene Diode SMD 8V/0.5W DIGIKEY FLZ8VCCT-ND F FUSE IEC FA LBC 5x0 50V/5A DIGIKEY F395-ND JP CONN HEADER 3POS 0.56 VERT TIN DIGIKEY WM46-ND JP3 CONN HEADER POS 0. VERT TIN DIGIKEY WM400-ND JP4, JP5 CONN HEADER 6POS 0.56 VERT TIN DIGIKEY WM464-ND L EMI Common Mode Choke 6mH/.6A DIGIKEY ND Lf, Lf PCV Seies Dum Coe Inducto 0mm 4.7uH/A COILCRAFT PCV L Q, Q TO-0FP N-Channel Powe MOSFET 500V/A DIGIKEY STF3NM50N R, Rbias, Rgs, Rgs Not Used Rbias, Rled 06 SMD Film RED /4W %.k DIGIKEY RHM.0kFCT-ND Rdisch Metal Film Powe Resisto W 5% 50k DIGIKEY BC50KW-CT-ND Rf 06 SMD Film RED /4W % 47k DIGIKEY RHM47.0kFCT-ND Rg, Rg 06 SMD Film RED /4W 5% 0 DIGIKEY RHM0ERCT-ND Rled 06 SMD Film RED /4W % 5.6k DIGIKEY RHM5.60kFCT-ND RMAX 06 SMD Film RED /4W % 5k DIGIKEY RHM5.0kFCT-ND RNTC Inush Cuent Limite 5 DIGIKEY ND Rpl Metal Film Powe Resisto W 5% 560 DIGIKEY PPC560W-CT-ND Rpl Metal Film Powe Resisto W 5% 470 DIGIKEY PPC470W-CT-ND Rs 06 SMD Film RED /4W % 33k DIGIKEY RHM33.0KFCT-ND Rs 06 SMD Film RED /4W % 0 DIGIKEY P0.0ECT-ND Rs3 06 SMD Film RED /4W % 3.74k DIGIKEY RHM3.74KFCT-ND Rs4 06 SMD Film RED /4W % 5k DIGIKEY RHM5.0KFCT-ND Rs5, RSS 06 SMD Film RED /4W % 3.9k DIGIKEY RHM3.90KFCT-ND Rstat, Rstat, Rstat3 06 SMD Film RED /4W % 3 70k DIGIKEY RHM70KFCT-ND RT 06 SMD Film RED /4W % 8k DIGIKEY RHM8.0KFCT-ND Rvcc 06 SMD Film RED /4W 5% 56 DIGIKEY RHM56ERCT-ND Rx, Rx 06 SMD Film RED /4W 5% 4.7 DIGIKEY RHM4.7ERCT-ND TX Resonant Powe Tansfome ETD49 PRECISION INC R U IRS795 Contol IC IR IRS795S U Photocouple TRANS-OUT 4-DIP TLP6 DIGIKEY TLP6FT-ND U3 Pogammable Voltage Regulato SOT3-3 TL43 DIGIKEY ND W Jumpe fo Pimay Cuent Sensing Loop AWG, multi stands AN-60 6

27 7.3 Typical Opeating Wavefoms Figue 3 400Vdc input, 0W load statup Figue 4-400Vdc input, 0W load statup Figue 5-400Vdc input, 0W load opeation AN-60 7

28 Figue 6 350Vdc input, 0W load opeation Figue 7 40Vdc input, 0W load opeation Figue 8 40Vdc input, 0W load opeation AN-60 8

29 7.4 Shot cicuit potection Figue 9 60Vac input, shot V, IC latched shut down 7.5 Efficiency The aveage efficiency of the boad at 5%, 50%, 75% and 00% load is 9% at 70Vac input: 70Vac 400Vdc 4Vout 4V Iout(A) Vout V Iout(A) Pout(W) Efficiency Efficiency % 9.0% % 9.6% % 9.9% % 9.7% % % AN-60 9

30 Efficieny vs. Output Powe Efficiency 93.5% 93.0% 9.5% 9.0% 9.5% 9.0% 90.5% 400Vdc input 70Vac input Output Powe (W) Figue 30 Efficiency Plot 8. Layout guidelines and example Gound Plane: In ode to minimize noise coupling, the gound plane should not be placed unde o nea the high voltage floating side. Gate Dive Loops: Cuent loops behave like antennas and ae able to eceive and tansmit EM noise. In ode to educe the EM coupling and impove the powe switch tun on/off pefomance, the gate dive loops must be educed as much as possible. Fo the low-side dive, the etun of the dive loop must be diectly connected to the COM pin of the IC and sepaate with signal gound (powe gound and signal gound have sta connection at COM pin). Supply Capacito: It is ecommended to place a bypass capacito (CVCC) between the VCC and COM pins. A µf ceamic capacito is suitable fo most applications. This component should be placed as close as possible to the pins in ode to educe paasitic elements. CBS Capacito: The CBS capacito should be placed as close as possible to the VB and VS pins. Routing and Placement: ) The 8-pin IC has only one COM pin fo both signal etun and powe etun, so it is stongly ecommended to oute the signal gound and powe gound sepaately with a sta connection at the COM pin. AN-60 30

31 ) The RT pin povides a cuent efeence fo the intenal oscillato and needs to be kept as clean as possible to avoid fequency jitteing o duty-cycle mismatch between high-side and low-side. The components connected to this pin must keep away fom the high fequency switching loop such as the gate dive loop and the VS node. The PCB taces connected to RT pin also need to be kept away fom any switching node. 3) Connect CT capacito diectly to COM pin, don t shae the etun with any othe signal gound. Layout examples VS node Signal components ae kept away fom switching nodes Supply bypass capacitos ae close to IC pins. Sta connection at COM pin Figue 3: Single laye boad example 9. Appendix Symbols list L : pimay esonant inductance. It is the pimay leakage inductance of tansfome when thee is no extenal added esonant inducto. L m : tansfome pimay magnetic inductance. It is the measued tansfome pimay inductance minus the leakage inductance. C : pimay esonant capacito and DC blocking capacito f : the esonant fequency between L and C Rac: Equivalent AC esistance fo esonant tank AC analysis R DSon : MOSFET channel ON esistance AN-60 3

32 f max : convete maximum opeating switching fequency f min : convete minimum opeating switching fequency Q g : MOSFET total gate chage Q gd : MOSFET gate to dain (Mille) chage Q gs : MOSFET gate to souce chage I QCC : IRS795(,) quiescent cuent R g : MOSFET gate dive esistance extenal to IRS795(,) R up : IRS795(,) gate dive pull up esistance R down : IRS795(,) gate dive pull down esistance R gfet: MOSFET gate input esistance P ICmax : IRS795(,) maximum powe dissipation V CC : Supply voltage on IRS795(,) Vcc pin I CC : IRS795(,) IC supply cuent Refeences [] IRS795(,) datasheet AN-60 3