Quasi Resonant DC Link Converters

Transcription

1 Quasi Resonant DC Link Convetes Analysis and Design fo a Battey Chage Application Pe Kalsson Lund 1999

2 Cove pictue Measuement of the esonant link voltage fo the quasi esonant DC link battey chage implemented. See futhe page 159. Depatment of Industial Electical Engineeing and Automation (IEA) Lund Institute of Technology (LTH) P.O. Box 118 S-1 LUND SWEDEN ISBN CODEN:LUTEDX/(TEIE-1)/1-16/(1999) 1999 Pe Kalsson Pinted in Sweden by Univesitetstyckeiet, Lund Univesity Lund 1999 ii

3 Abstact Envionmental aspects have duing the last yeas made electic vehicles an inteesting competito to the pesent intenal combustion engine diven vehicles. Fo a boad intoduction of pue electic vehicles, a battey chaging infastuctue is deemed necessay. Howeve, to build and maintain such an infastuctue is costly. Active powe line conditioning capabilities could be included in the battey chage, making the infastuctue advantageous fom the distibution netwok point of view. Anothe option is that the battey chage could be able to suppot the gid with peak powe duing peiods of stability poblems o emegency situations. This means that enegy is boowed fom the batteies of vehicles connected to a chage. The pice fo enegy supplied by the batteies is likely to be seveal times highe than the nomal electic enegy pice, due to the wea costs of the batteies. Theefoe, the battey chage losses also epesents a high cost. It is often stated that esonant convetes have a high efficiency compaed to had switched. Since caie based pulse width modulation is employed, quasi esonant DC link convetes ae of inteest. Fou of the most pomising quasi esonant DC link topologies epoted in the liteatue ae compaed. A fai compaison is obtained by designing them to meet cetain common design citeia, in this case the duation of the zeo voltage inteval and the maximum output voltage time deivative. The deivation of the design expessions ae given, and also the simulation esults, by means of efficiency. A 1 kw battey chage, equipped with one of the quasi esonant DC links investigated is implemented. A had switched battey chage with the same ating is also tested to compae the measued efficiency with the simulated. Both the simulations and measuements shows that the efficiency decease fo quasi esonant battey chages compaed to the had switched case. Futhemoe, low fequency hamonics appea in the battey chage input and output cuents. Howeve, full contol of the output voltage deivatives is obtained.

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5 Acknowledgements Fist of all I would like to thank my fiend and oommate Matin Bojup, who also is the pefect poject companion. Togethe, we have spent many late evenings in the laboatoy, testing battey chages. I also would like to expess my sincee gatitude to my supevisos, Pofesso Mats Alaküla and Pofesso Las Getma. Thei suppot and encouagement have been to geat help along the way. Las Getma also has pomoted seveal valuable contacts, which is stongly appeciated. The steeing committee also consists of the extenal membes Andes Lasson, Volvo Technological Development, and Ulf Thoén, Sydkaft AB. Besides the inteesting discussions held at the committee meetings, they neve hesitate to answe questions o give a helping hand, which of couse is geatly acknowledged. I am also vey gateful to all my colleagues and the staff of IEA, who makes the wok enjoyable. Special thanks to Getachew Dage and Bengt Simonsson fo thei help egading pactical issues. Bengt Simonsson has a lot of valuable contacts which lowes the costs and shotens delivey times. Special thanks also to D Ulf Jeppsson, fo maintaining the UNIXsystem, with the softwaes SABER and ACE. I am also vey thankful to the ecently etied Associate Pofesso at IEA, Stig Lindquist, who bought me to the depatment as a laboatoy assistant in I thank my paents fo thei love, suppot and tust. I also thank my fiends back in Helsingbog, fo thei suppot. This wok is pat of the poject Battey Chages fo Electic Vehicles which has been financially suppoted by Elfosk AB as a poject unde the Elekta eseach and development pogam. This suppot is gatefully acknowledged. Pe Kalsson

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7 Contents 1 Intoduction Backgound Fast chaging Chage infastuctue Battey chage topology Resonant convetes Outline of the thesis... 5 Resonant convetes 7.1 The RCD chage-dischage snubbe Load esonant convetes The esonant DC link convete Quasi esonant DC link convetes Analysis and design of quasi esonant DC link convetes The passively clamped two switch quasi esonant cicuit The passively clamped one switch quasi esonant cicuit The paallel quasi esonant cicuit The actively clamped quasi esonant cicuit Devices fo esonant convetes Powe diodes IGBTs Inductive elements Capacitos...11

8 Contents 5 Simulation Geneal simulation model Simulation of the two switch passively clamped quasi esonant DC link Simulation of the one switch passively clamped quasi esonant DC link Simulation of the paallel quasi esonant DC link Simulation of the actively clamped quasi esonant DC link Simulation conclusions Implementation Powe electonic main cicuit Quasi esonant DC link contolle Measuements Conclusions Results Futue wok Refeences 167 A Modulation 175 A.1 Caie based PWM A. Discete pulse modulation B Contol 181 B.1 Battey side cuent contolle B. AC side vecto cuent contolle...18 B.3 DC link voltage contolle C Diffeential equations 187 C.1 Method C. Application to the esonant DC link convete C.3 Integation of the voltage equation D Inducto design 197 D.1 Inductance D. Inducto coe size selection D.3 Inducto design example...1 viii

9 1 Intoduction This chapte intoduces electic vehicles and battey chages fo electic vehicles. Then, an intoduction to the investigated concept is povided. Finally an oveview of the thesis is given. 1.1 Backgound Envionmental aspects have made electic vehicles (EVs) an inteesting challenge of the pesent Intenal Combustion Engine (ICE) diven vehicles. Pesent electical dives offes a eliable and envionmentally sustainable solution to the pollution poblems caused by the ICE diven vehicles. Almost all of the commecial automobile companies do indeed have a poduct ange that also coves EVs. Anyway, today thee is only a limited use of EVs fo pesonal taffic. In Sweden, most of the EVs ae used fo community puposes such as postal delivey. Howeve, also in these cases the EVs constitutes only a mino pat of the vehicle fleet of these companies. The main poblem with EVs is that the batteies limit the maximum diving ange, since pesent electo-chemical batteies do have a by fa lowe enegy to weight atio than gasolin. Pesent EVs ae equipped with an on-boad battey chage. The onboad chage nomally has a athe low powe ating, since it is pimaily intended fo night-time battey chaging at the ownes esidence. Usually, Swedish households ae equipped with 16 A fuses, which limits the chaging powe to appoximately 1 kw. Today, this poblem can be solved by the use of electo-hybid systems, wee an ICE is mechanically connected to an electical geneato chaging the vehicle batteies. Some of these electical hybid vehicles (EHVs) also uses a pat of the enegy geneated by the ICE fo taction of the vehicle [38]. The idea is to chage the batteies when diving outside city aea. The chaging stategy can be optimised in such a way that the ICE is contolled to give minimum emissions o to minimise the fuel

10 1. Intoduction consumption o othe citeia [1]. Howeve it is obvious that the pollution poblem is only deceased, not eliminated by such a solution. 1. Fast chaging As peviously mentioned, pesent EVs ae equipped with on-boad battey chages, but in ode to be able to compete with the ICE diven vehicles by means of daily diving ange, a fast chaging infastuctue is needed. Thee ae howeve poblems with the building of a fast chage infastuctue as well. Fist, the cost of chages is high and second, designs based on diode o thyisto technology could esult in cuent hamonics and voltage distotion [49]. Instead of diode o thyisto technology, fully contollable semiconducto devices, i.e. powe tansistos, should be used. Tansisto equipped voltage souce convetes (VSCs) ae often used fo eliably opeating speed contol of electical dives. The tansistos ae contolled by pulse width modulation (PWM) which gives a well defined output cuent spectum [44]. If PWM contolled VSCs ae used fo battey chages, the poblem of gid fequency elated distotion can be cicumvented. Howeve, the cost of the chages and contolles inceases since they become moe complicated. Anyway, a boad intoduction of electic vehicles opens a new maket fo the powe semiconducto industy which pobably esults in a lowe pice fo these devices. In [36] it is stated that fast chaging should be avoided in uban aeas due to the fact that the deegulation of the powe distibution maket has esulted in etiement of seveal enegy plants neaby cities, since it is cheape to buy powe than to un these plants. The electical powe bought on the maket is geneated at lage hydo o nuclea powe plants, which esults in a low pice. The poblem is that stability poblems might aise since such plants usually ae located fa away fom uban aea. Fast chaging futhe inceases this poblem since the loading of the tansmission lines becomes heavie, at all times duing the day, thus esulting in highe peak powe demands. 1.3 Chage infastuctue One way to cope with the poblem of the initial high cost of the chaging infastuctue, is to make it advantageous both fo the powe deliveing company and fo the EV ownes. It was peviously mentioned that a

11 1. Intoduction battey chage using a diode o thyisto based gid inteface usually consumes non-sinusoidal cuent and thus injects hamonics into the gid. If a battey chage infastuctue is built solely on such chages thee would typically be poblems like themal oveloading of tansfomes and shunt capacitos [39]. Futhemoe, malfunction of equipment sensitive to distubances is going to be a poblem [39], [5]. If, on the othe hand, battey chages with a powe tansisto gid inteface ae used, they can be contolled to inject o consume cuents of abitay wavefom. This means that the powe gid inteface can be used to consume hamonics in ode to cancel hamonics injected by othe loads. Also, eactive powe can be geneated o consumed by such a powe gid inteface. Single phase loads can be compensated fo, which means that the cuent can be contolled in a manne wee the highe voltage levels will expeience the lowe as consuming a balanced, hamonic fee thee phase cuent with powe facto equal to one. These featues foms what usually is called an active powe line conditione o active filte [4], [37]. Thee is one futhe possibility of such a system, which might be slightly povocative; the battey chage can be used to delive powe fom the batteies back to the powe gid. This is not likely to be used fo the high powe chaging stations (gas station countepat) except at emegency situations like duing powe system stability poblems. This is due to the fact that, at the chaging station the EV should be chaged as fast as possible, without any delays, o thee might be an queue situation. Fo low powe battey chages at paking lots o office buildings etc., this active powe capability can be inteesting. At such places thee will be occasions when the vehicle is connected to the battey chage fo longe time than it takes to chage its batteies. Fo these occasions, an ageement between the EV owne and the payment system of the battey chage can be set. Fo instance, the ageement can say that the batteies might be dischaged duing the day but at a cetain time they should be chaged to a cetain level and the chaging enegy pice should be educed to a cetain level. Dischaging the batteies shotens thei lifetime which can be costly fo the EV owne. This can be solved by a leasing ageement whee the powe deliveing company owns the batteies, and the EV owne leases the batteies. The ageement pocedue indicated above esults in no futhe complexity, since a payment system is needed anyway [39]. The payment system is based on communication between the battey management system (BMS) of the EV, the battey chage and a supevisoy unit 3

12 1. Intoduction which is needed both fo billing and fo opeation of the battey chage as an active powe line conditione. 1.4 Battey chage topology A wide vaiety of diffeent convete topologies used fo battey chages do indeed exist. Howeve, in ode to meet the capabilities stated in the pevious section, the ange of cicuits is educed. Since this is a, fom powe electonic point of view, low to medium powe application a voltage souce convete is consideed. The eason fo this is that most tansisto valves fo this powe ange ae designed fo voltage souce convetes. Also, the simplicity of the voltage souce convete compaed to the cuent souce convete (CSC) is an advantage. In Figue 1.1 a voltage souce battey chage is shown. Hee, the chage is connected to the powe gid via a LCL-filte. The line side stage of the battey chage is a thee phase voltage souce convete, acting as a contolled ectifie. The capacito C dc is efeed to as the DC link capacito, poviding the voltage souce featue. On the battey side, a half bidge convete is used to contol the chaging cuent fed to the vehicle batteies, via anothe LCL-filte. 3Φ 4 V 5 Hz V dc C dc V batt Figue 1.1 Voltage souce battey chage. Note that the line and battey side filtes ae composed fom LCL-combinations, foming thid ode filtes. The advantages of LCL-filtes compaed to the nomally used L-filtes ae thooughly discussed in [4]. In Appendix D.3 design of a LCL-filte inducto fo a 75 kw battey chage accoding to Figue 1.1, implemented in [3], is discussed. 1.5 Resonant convetes A consequence of the peviously mentioned active powe delivey capability is that the efficiency of the battey chage becomes vey impotant, since the enegy pice fo enegy deliveed fom the batteies to the powe gid becomes consideably highe than the nomal enegy pice, due to the wea cost of the batteies. It is often stated in the 4

13 1. Intoduction liteatue [5], [13], [14], [3], that an inceased efficiency can be achieved by using a esonant convete which povides educed switching losses at the expense of an inceased numbe of passive and in some cases also active devices. Futhemoe, it is often pointed out that the device stess fo the active devices ae educed fo esonant convetes [16], [8], [3]. Thee ae seveal diffeent types of esonant convetes but the basic idea is that that the switch state should be changed only at low voltage acoss o at low cuent though the semiconducto devices, thus esulting in educed switching losses. The ising and falling edges of these quantities can also be contolled to educe intefeence poblems. Fo esonant powe convetes with low semiconducto device count, the esonant cicuit is often compised patly by the load [8], [3], [3], [35], [45], [59]. Hee, these ae efeed to as load esonant convetes. Fo bidge applications on the othe hand, often one esonant cicuit, inseted in between the passive enegy stoage device and the semiconducto bidge, is used to seve the entie bidge. This type of esonant convetes ae efeed to as esonant DC link convetes [13], [14], [], [3], [43], [46], [47]. Fo the basic esonant convetes the possible switching instants, i.e. when low device voltage o cuent is obtained, cannot be contolled. This means that caie based PWM cannot be used fo this type of convetes. Only a sub-class of the esonant convetes can be tigged on demand, efeed to as quasi esonant convetes [1], [], [7], [9], [11], [15], [19], [41], [55], [56]. Fo a quasi esonant convete, the oscillation is inteupted in between two consecutive switching instants and is only stated when a change of convete switch state is commanded. Fo a battey chage with active powe line conditioning capabilities, caie based PWM is pefeed due to its well known output cuent spectum [44]. This means that if esonant powe convete technology is to be used, quasi esonant DC link convetes ae the most inteesting. 1.6 Outline of the thesis In Chapte, basic popeties of soft switching ae discussed, stating fom capacitive snubbes. The design expessions fo quasi esonant DC link convete passive component selection ae developed in Chapte 3. The design expessions ae deived though thoough mathematical analysis of fou diffeent quasi esonant DC links. In Chapte 4, powe electonic semiconducto devices in soft switching applications ae 5

14 1. Intoduction eviewed. Also, the simulation passive component models used in Chapte 5 ae discussed. In Chapte 5, battey chages equipped with the quasi esonant DC links investigated, ae simulated. The quasi esonant convetes simulated, ae designed to have equal popeties, at least in some aspects. The simulations ae intended to veify the design expessions and also fo calculation of the efficiency of the diffeent battey chages. In Chapte 6, one of the simulated battey chages is implemented and tested. Chapte 7 concludes the thesis. Note that this thesis is one of two, evolved fom the battey chage poject. The accompanying thesis [4], teats contol and functional aspects of the battey chage, while this thesis focuses on hadwae elated aspects. 6

15 Resonant convetes The pesent esonant convete topologies do indeed exist in a wide vaiety of foms. Howeve, they all oiginate fom attempts to avoid simultaneously high voltage acoss and high cuent though the semiconducto devices when the device taveses fom conducting to blocking state o vice vesa. Anothe advantage of esonant convetes often addessed in the liteatue, is the ability to contol the time deivative of the voltage and/o the cuent. On the othe hand, esonant convetes intoduces new poblems. This chapte gives an intoduction to the evolution of esonant convetes, fom load esonant convetes to quasi esonant DC link convetes. Though not esonant, this pesentation stats with a shot intoduction of a cetain kind of snubbe, the RCD chage-dischage snubbe, which exhibits some of the featues of esonant convetes..1 The RCD chage-dischage snubbe In this section the RCD chage-dischage snubbe is investigated. This is mainly done in ode to intoduce the tem soft switching. The investigation stats with a pesentation of the had switched step down convete. Then, a capacitive snubbe is intoduced. This is followed by the intoduction of the full RCD chage-dischage snubbe applied both fo the step down convete and a tansisto half bidge. Had switching One of the most basic tansisto bidge configuations fo powe electonic applications is the step down convete. It consists of a voltage souce (DC link capacito), a powe tansisto (IGBT in this case) and a feewheeling diode, see Figue.1. Since this is a voltage souce convete, the load is a cuent souce, i.e. inductive. When the state of the switch is changed fom on to off (tun-off) o fom off to on (tunon), the tansition will take a finite time in the non-ideal case. Futhemoe, fo non-ideal cicuits thee ae paasitic components, fo

16 . Resonant convetes example stay inductance that can cause ovevoltage acoss the semiconducto devices at tun-off. i C v CE V dc I load Figue.1 Basic step down convete used in the analysis. Figue. shows typical collecto cuent and collecto-emitte voltage fo a powe tansisto (IGBT in this case), when used in the step down convete above. Note that the collecto cuent and collecto-emitte voltage is expessed in p.u., whee the nomalisation values ae selected as the ated maximum continuos collecto cuent, I C, and maximum collecto-emitte voltage that can be sustained acoss the device, V CES. In the simulation of the step down convete the DC link voltage V dc and load cuent I load ae selected as I V load dc = 8. I = 6. V C CES (.1) v CE i C v CE i C 1 1 Figue. 1 (a) t [µs] 1 (b) t [µs] Time-signals showing nomalised tansisto cuent (black) and voltage (gey) at (a) tun-on and (b) tun-off of the powe tansisto in the step down convete. In Figue., the powe tansisto is exposed to a cuent spike at tunon which is due to evese ecovey of the feewheeling diode. Futhemoe, it is clealy seen that the IGBT is exposed to simultaneously high cuent and voltage at the switching instants. This leads to high switching losses, especially at tun-off since the IGBT exhibits a collecto 8

17 . Resonant convetes cuent tail hee. The physics of evese ecovey of a powe diode and the IGBT cuent tail ae discussed in Chapte 4. A common way to visualise the stess levels imposed on a powe electonic semiconducto device is to plot the switching tajectoies, i.e. cuent vesus voltage, on top of the safe opeating aea (SOA) of the device. The powe semiconducto manufactues specify the SOA on absolute maximum values that must not be exceeded. Howeve, in some cases thee ae two SOAs, the second valid only fo vey shot pulses (tansients). Figue.3 shows the switching tajectoies coesponding to the time signals in Figue. on top of the SOA fo the paticula IGBT used in the simulation of the step down convete above. i C v CE Figue.3 Switching tajectoies (tun-on black and tun-off gey) of an IGBT in a step down convete application. The total aea coesponds to the safe opeating aea valid fo shot pulses. The switching tajectoies in Figue.3 shows that thee ae no poblems with ovevoltage o ovecuent extending outside the SOA. The duation of the time intevals whee the powe tansisto is exposed to high cuent and voltage simultaneously, causing high losses, is howeve not seen. This can only be seen in Figue.. Both these plots ae valuable since eithe of them ae delimiting to what extent, by means of tansfeed powe, the powe convete can be used. In some cases, the cicuit stay inductance can be high causing a high ovevoltage at tun-off, which means that thee must be a lage magin between the DC link voltage used and the ated voltage. In othe cases the switching losses can be high causing a low value of ated convete cuent in ode to keep the junction tempeatue of the powe tansisto at an acceptable level. To patly ovecome this poblem and be able to use the semiconducto devices in a moe efficient way, snubbe cicuits ae intoduced [44], [6], 9

18 . Resonant convetes [63]. Thee ae seveal diffeent snubbe cicuits used fo diffeent puposes, fo example to educe the ovevoltage caused by stay inductance, at tun-off. Thee ae also snubbe cicuits whee the aim is to move the switching loci futhe into the SOA, which means lowe losses, at least if the duation of the switching intevals ae not polonged. One such snubbe is the RCD (esisto, capacito, diode) chage-dischage snubbe. The capacitive snubbe Fom now on the RCD chage-dischage-snubbe is efeed to only as RCD snubbe, even though thee ae seveal types of RCD snubbes fo diffeent puposes. At tun-off, this snubbe behaves as a pue capacito. Theefoe, in ode to simplify the peliminay analysis, the snubbe is consideed as consisting only of a single capacito denoted C s in Figue.4. i C v CE C s V dc I load Figue.4 The step down convete with a puely capacitive tun-off snubbe. By intoducing a capacito acoss the powe tansisto output teminals, the voltage deivative with espect to time can be contolled, see fo example [44]. This is possible since at tun-off, a pat of the tansisto cuent finds an altenative path though the capacito, which means that the tansisto collecto cuent falls and the collecto-emitte voltage ises simultaneously, see Figue.5. This is not possible in the pevious case, i.e. without a snubbe, since hee the only altenative way fo the load cuent is though the feewheeling diode. The feewheeling diode only caies substantial cuent when fowad biased, which means that the tansisto collecto-emitte voltage must be appoximately equal to the DC link voltage, V dc, befoe the collecto cuent can begin to decline at tun-off fo the case without a snubbe. It is sometimes stated that this type of snubbe cicuit povides tun-off unde zeo voltage switching (ZVS) conditions, o soft switched conditions [5]. This efes to the fact that when the tun-off sequence is initiated, the collecto-emitte voltage is appoximately zeo. Howeve, at 1

19 . Resonant convetes the end of the cuent fall inteval the collecto-emitte voltage is high, ideally equal to the DC link voltage V dc, accoding to [44]. Convetes not using snubbes poviding soft tansitions neithe at tunon o tun-off, ae often temed had switched [3], [5]. Anothe chaacteisation of soft switching is also used in this context, zeo cuent switching (ZCS), which efes to that eithe o both the tun-on and tunoff tansitions take place at vitually zeo cuent [35], [44]. v CE i C 3 v CE i C Figue.5 1 (a) t [µs] 1 (b) t [µs] Time-signals showing tansisto cuent (black) and voltage (gey) at (a) tun-on and (b) tun-off of the powe tansisto in the step down convete with a capacitive snubbe acoss the powe tansisto. Note the high collecto cuent peak at tun-on, and that the collecto cuent and collecto-emitte voltage changes simultaneously at tun-off. Fom Figue.5 it is seen that the snubbe capacito is affecting the tunoff wavefoms in such a way that the tun-off losses do decease. Also, the collecto-emitte voltage deivative is contolled which can be an impotant aspect by means of electomagnetic compatibility (EMC) [51]. On the othe hand, it is also seen that the tun-on wavefoms becomes less favouable. Fo the had switched step down convete thee was a shot collecto cuent spike due to evese ecovey of the feewheeling diode at tunon of the powe tansisto. Fo the case with a capacitive snubbe the cuent spike is even highe, thus adding stess to the tansisto at tunon. Pio to tun-on, the snubbe capacito is fully chaged, i.e. the capacito voltage equals V dc. The voltage acoss the feewheeling diode emains close to zeo as long as its junction is fowad biased, which implies that 11

20 . Resonant convetes the capacito voltage, and theeby the collecto-emitte voltage, cannot decease befoe the pn-junction of the feewheeling diode becomes evese biased. The feewheeling diode becomes evese biased exactly when the evese ecovey cuent eaches its peak value. Revese ecovey is due to stoed minoity chage caies close to the pn-junction of the diode, causing the junction to be fowad biased even though the diode cuent is negative. The negative cuent sweeps out the minoity caies and eventually the junction becomes evese biased. As mentioned ealie, powe electonic diodes and IGBTs ae investigated futhe in Chapte 4. The discussion above implies that the capacito dischage stats when the evese ecovey cuent eaches its peak. Even if the diode ecoves fast, the tansisto has to cay an excessive cuent fo quite some time since the only dischage path fo the capacito is though the powe tansisto. The RCD snubbe In ode to cope with the poblem of the capacitive snubbe, a esisto is added. The intention with the esisto is to limit the capacito dischage cuent at tansisto tun-on. A diode is placed in paallel with the esisto since at tun-off, the capacito gives the desied behaviou and the esisto would only cause inceased losses. This completes the RCD snubbe, see Figue.6. V dc i C D s R s v CE C s I load Figue.6 The step down convete with the full RCD chage-dischage snubbe placed acoss the output teminals of the device. The esisto value is chosen in such a way that the capacito peak dischage cuent do not exceed the peak evese ecovey cuent of the feewheeling diode [44]. Figue.7 shows the time signals of the tansisto collecto cuent and collecto-emitte voltage. It is clealy seen that the tun-off sequence is simila to the one fo the puely capacitive snubbe, but the stess levels at tun-on is only slightly highe than it was fo the had switched step down convete. 1

21 . Resonant convetes v CE i C v CE i C 1 1 Figue.7 1 (a) t [µs] 1 (b) t [µs] Time-signals showing tansisto cuent (black) and voltage (gey) at (a) tun-on and (b) tun-off of the powe tansisto in the step down convete with a full RCD chage-dischage snubbe acoss the powe tansisto. The RCD chage-dischage snubbe in bidge applications The battey chage poposed consists of fou half bidges with two IGBTs and two feewheeling diodes each, see Figue 1.1. To investigate the switching wavefoms fo a battey chage implemented with RCD snubbes, one acoss each IGBT, an entie half bidge has to be consideed. In Figue.8 a half bidge with a RCD snubbe acoss each tansisto is shown. V dc i C D s1 v CE R s1 C s1 D s R s C s I load Figue.8 A half bidge with one RCD snubbe connected acoss each tansisto. The uppe RCD snubbe is intended to povide soft tun-off fo the uppe IGBT. The lowe RCD snubbe is intended to povide soft tun-off fo the lowe IGBT. The simulated collecto cuent and collecto-emitte voltage ae shown in Figue.9. Note the vey high cuent peak at tansisto tun-on. The occuence of this cuent peak is due to the capacitive cuent path seen fom the IGBT output teminals, [44]. At tun-on of the uppe IGBT, the collecto-emitte voltage should decease fo the uppe IGBT and incease fo the lowe. This means that the uppe snubbe capacito in 13

22 . Resonant convetes Figue.8, denoted C s1, should be dischaged and the lowe, denoted C s, should be chaged. v CE i C 4 v CE i C Figue.9 1 (a) t [µs] 1 (b) t [µs] Time-signals showing tansisto collecto cuent (black) and collectoemitte voltage (gey) at (a) tun-on and (b) tun-off of the uppe IGBT in the convete consisting of a bidge leg. One RCD snubbe is used acoss each IGBT. Note the high collecto cuent peak at tun-on. Also note the poo behaviou at tun-off. The dischage cuent of C s1 is limited by the snubbe esisto R s1 as pevious but the chaging cuent of C s is not limited by any othe component. Futhemoe, the only path possible fo the chaging cuent, is though the uppe IGBT. In this way, the chaging cuent of the lowe snubbe capacito gives a lage contibution to the collecto cuent of the uppe IGBT, at tun-on. The same poblem appeas fo the lowe tansisto. Anothe poblem seen in Figue.9 is that the tun-off is not soft, i.e. the collecto cuent fall and the collecto-emitte voltage ise do not occu simultaneously. Instead, the collecto cuent falls somewhat, then inceases and eventually the cuent falls again. This is efeed to as a cuent tail bump, which is discussed in Chapte 4. The switching loci fo the convete consisting of a bidge leg with RCD snubbes acoss the tansistos is shown in Figue.1. Note that the switching tajectoy is outside the SOA valid fo vey shot pulses, which is vey dangeous, since this can lead to device failue. 14

23 . Resonant convetes Small vaiations of the snubbe cicuit can be used to patly solve this poblem. Fist, the snubbe diodes in paallel with the esistos can be emoved. In this way the capacitive path is boken but soft tun-off is also lost. Howeve, EMC elated poblems can still be educed [44]. i C v CE Figue.1 Switching loci (tun-on black and tun-off dak gey) of the bidge leg with RCD snubbes. Note that the tun-on collecto cuent is beyond the cuent limit of the dynamic SOA (light gey), valid fo shot pulses. Anothe way to solve this poblem is by intoducing inductos in seies with the snubbes, thus educing the cuent deivative with espect to time [63]. This woks, but gives a bulky snubbe. This is not desiable, especially not since eight such snubbes ae needed fo the battey chage consideed.. Load esonant convetes The next step is to investigate load esonant convetes. The name load esonant convete efes to the fact that fo this type of convetes, the load is pat of the esonant cicuit. Thee ae basically two diffeent types, the seies and the paallel esonant convetes. In this section both these, also efeed to as class D convetes, ae discussed. Accoding to [8] the class D esonant convetes wee invented by P.J. Baxandall in The idea of esonant convetes is to povide soft switching in ode to be able to incease the switching fequency. An inceased switching fequency means that the passive filte equiements and/o the output cuent ipple ae deceased. Also, switching fequencies beyond the 15

24 . Resonant convetes audible limit of the human ea can be used, thus educing the distubing noise of the convete. The seies esonant convete The seies esonant convete consist of one o two half bidges foming a half o full bidge convete. Between the output teminals, a seies esonant cicuit is connected. This seies esonant cicuit consists of an inducto, a capacito and a esisto, with one o moe of these elements actually being pat of the load. Usually, at least the esisto is pat of the load. Howeve, fo this basic cicuit only AC-powe can be deliveed to the load, due to the esonant behaviou of the cicuit. If a DC-load is used, the esisto can be eplaced by a ectifie connected to the DC load. If the load is diectly connected to the esonant cicuit, i.e. without a ectifie in between, it is efeed to as a seies esonant DC to AC convete. If the load is connected to the convete via a ectifie, it is efeed to as a seies esonant DC to DC convete. The basic seies esonant DC to DC full-bidge convete is shown in Figue.11. L C i load V dc v conv i L v ect V load Figue.11 Seies esonant DC-DC full-bidge convete. In this case the load consist of a constant voltage souce, i.e. an ideal battey. Besides the basic components peviously discussed, the convete in Figue.11 is also equipped with loss-less snubbes, i.e. capacitive snubbes, which ae discussed late. The ectifie is connected in seies with the esonant cicuit which acts as a cuent souce fo the ectifie. Since the ectifie is cuent fed, the ectifie output should appea as a voltage souce. Load esonant cicuits ae often [8], [44] chaacteised upon the fundamental of the excitation fequency fed by the convete. The behaviou of the cicuit is vaying depending on whethe the convete output fequency is below, at o above the esonance fequency of the LC cicuit [8], [44]. The esonance fequency is given by ω = π f = 1 LC (.) 16

25 . Resonant convetes Figue.1 shows the wavefoms of the seies esonant convete opeating at switching fequency above the esonance fequency. v conv v ect t [µs] (a) i load i L t [µs] (b) Figue.1 Nomalised voltages (a), convete output voltage (black) and ectifie input voltage (gey). Nomalised cuents (b), load cuent (black) and esonant cuent (gey). Note that the esonant cuent is lagging the fundamental of the convete output voltage. The quantities in Figue.1 ae nomalised to a p.u. system with base values selected accoding to I V base base = I = V load, avg dc (.3) The shape of the wavefoms, especially the esonant cuent in the case of a seies esonant convete, ae stongly dependent on the loaded quality facto, Q L, defined as 17

26 . Resonant convetes Q L Z = (.4) R eq whee Z L = (.5) C In [8] it is stated that the esonant cuent i L is almost sinusoidal if Q L is lage than.5. Fo a non-linea load, an equivalent loaded quality facto have to be calculated. Fo the convete in Figue.11, with wavefoms as in Figue.1, an equivalent load esistance is calculated based on the amplitude of the fundamental of the ectifie input voltage, which is popotional to the battey voltage. It is also assumed that the esonant cuent is sinusoidal. In this example, a Q L of 1.5 and a esonance fequency of 66.7 khz ae desied. These two paametes togethe with the equivalent seies esistance gives the component values of L and C. The eason fo selecting a low Q L is that this gives a low esonant cuent and a low esonant capacito voltage v C [8], [35]. Fo the seies esonant convete, a switching fequency lowe than the esonance fequency means that the esonant cicuit behaves like a capacitive load. Switching fequency highe than the esonant fequency means that the esonant cicuit appeas as an inductive load fo the convete. Thus, at switching fequencies below esonance, the esonant cuent i L leads the fundamental of the convete output voltage. Consequently, i L lags the fundamental of the convete voltage when the esonant cicuit is excited above the esonance fequency. Fo continuos load cuent this means that below esonance fequency the convete switches ae tuned on in a had switched manne and tuned off unde ZVS and ZCS conditions. Above esonance the convete switches ae tuned on unde ZVS and ZCS conditions and tuned off unde had switched conditions. Loss-less tun-off above esonance is povided by the individual snubbe capacitos in paallel with each convete switch, as shown in Figue.11. Peviously when ZVS tun-off snubbes wee discussed, it was found that the use of capacitive snubbes mounted acoss each tansisto in a half bidge, esulted in high collecto cuent peaks at tun-on. Howeve, in the case of a seies esonant convete this poblem is not obseved due to 18

27 . Resonant convetes the fact that the tansistos tun-on at ZVS and ZCS conditions since the diode in paallel with the tansisto is caying the esonant cuent, pio to tun-on. The esonant cuent commutates to the tansistos when its sign changes. This implies that tansisto tun-on do not change the chage state of the snubbe capacitos, and consequently no snubbe capacito chaging cuent is caied by the tansistos. Although this cicuit was invented aleady in 1959, the seies esonant convete is still a eseach object [8], [45]. Also vaiants of this cicuit togethe with the cicuit discussed in the next section, the paallel esonant convete, is gaining a lot of inteest [8], [3], [44]. In [35], [45] the seies esonant convete is used in a somewhat diffeent way than peviously descibed. Hee, the seies esonant cicuit is opeated well below esonant fequency and with discontinuous esonant cuent. Although the cicuit pesented in [35] do not look exactly as a seies esonant in Figue.11, it is still a seies esonant DC to DC convete. The idea of opeating the seies esonant convete below esonance and with discontinuous cuent is that tun-on and tun-off is pefomed unde (vitually) ZCS conditions. The eason fo this is that the esonant cuent is only piecewise sinusoidal, with intevals appoximately equal to zeo in between. In [35] it is stated that these intevals ae not equal to zeo, since a tansfome is connected between the esonant cicuit and the ectifie, which gives ise to a small magnetising cuent duing the discontinuous cuent intevals. Anyway, the convete switches ae opeated at low cuent. The paallel esonant convete The paallel load esonant convete is simila to the peviously investigated seies esonant convete. Howeve, in the case of a paallel esonant convete, the output ectifie is connected in paallel with the esonant capacito, see Figue.13. Since the esonant capacito epesents a voltage souce to the ectifie, the output filte of the ectifie must be a cuent souce, i.e. inductive. The ectifie epesents a non-linea load, also in this case. Usually, a tansfome is connected between the esonant cicuit and the ectifie in ode to adapt the load voltage to the DC link voltage used. A tansfome can also be used to povide a galvanically isolated output voltage, which is desied in some applications. 19

28 . Resonant convetes L f L i ect V dc v conv i L C v C V load Figue.13 The paallel esonant convete with a constant voltage load. Note the capacitive snubbes connected acoss the convete switches poviding loss-less tun-off. Often a tansfome is connected between the esonant cicuit and the ectifie. The esonant wavefoms of the paallel esonant convete in Figue.13, opeating at switching fequency above esonance ae shown in Figue.14. Hee, the wavefoms ae nomalised accoding to (.3). v conv v C t [µs] (a) i ect i L t [µs] (b) Figue.14 Nomalised voltages (a), convete output voltage (black) and esonant capacito voltage (gey). Nomalised cuents (b), load cuent (black) and esonant inducto cuent (gey).

29 . Resonant convetes Unlike the case with the seies esonant convete, the esonant inducto cuent is not detemined by the ectifie output cuent fo the paallel esonant convete. On the othe hand, the ectifie output voltage is dependent on the esonant capacito voltage fo the paallel esonant convete. Fo the paallel esonant convete, continuos cuent opeation above esonance esults in tun-on at ZCS conditions since the esonant cuent commutates fom the feewheeling diodes to the powe tansistos natually. In this case, natual commutation means that the commutation takes place at the zeo cossing of the esonant inducto cuent. Tansisto tun-off howeve, is not pefomed unde neithe ZCS o ZVS conditions, unless loss-less tun-off snubbes ae used. As befoe, the capacitive snubbes povide tun-off at low voltage. Simila to the case fo the seies esonant convete, thee is no cuent peak occuing with such snubbes at tun-on of the convete switches fo the paallel esonant convete. The main poblem of both the seies and the paallel esonant convetes, is that the esonant cuents and voltages can be seveal times highe than the aveage load cuent and DC link voltage espectively, depending on the load. If lage load vaiations ae likely, the components of the esonant convete must be designed fo the wost case stess. Seveal vaiations and combinations of the seies and paallel esonant convetes do exist [8], [44]. Thee ae also completely diffeent esonant convetes like the class E esonant convetes [8], [44] and the zeo voltage tansition (ZVT) convetes [4]. Howeve, thee ae so many esonant convete topologies that a complete eview would be vey extensive. Futhemoe, the eseach on esonant convetes is widespead which also makes a complete suvey difficult..3 The esonant DC link convete A huge step in esonant convete technology was taken in 1986 when the esonant DC link convete was invented [13], [14]. Fo the esonant DC link convete, one esonant cicuit is used to povide soft switching fo the entie convete. As the name esonant DC link hints, it is the DC link which is foced to oscillate. This means that the esonance cicuit is located on the DC link side and not on the load side of the convete. This is vey useful, especially fo thee (o moe) phase convetes since othewise, one esonant cicuit fo each half bidge would be equied. 1

30 . Resonant convetes The basic thee phase esonant DC link convete is shown in Figue.15. If a thee phase back-to-back convete [6] is to be implemented with a esonant DC link, this is done by connecting the six half bidges in paallel [13]. In [13] anothe solution fo the esonant back-to-back convete is also pesented whee a cuent fed H-bidge is used. This cicuit equies fou exta switches and is not consideed hee. L v L i L i conv i C V dc C dc C v C Figue.15 The basic thee phase esonant DC link convete. In ode to investigate the esonant DC link convete, a simplification of the convete in Figue.15 is done. Instead of the thee phase convete, a piecewise constant cuent souce is connected acoss the DC link epesenting the cuent fed to the convete. Howeve, one switch must be kept acoss the DC link since a path fo the ciculating esonant cuent has to be povided. The simplified esonant DC link convete is shown in Figue.16. The idea of the esonant DC link convete is that the switch state of the convete only should be changed at o close to zeo link voltage. This implies that the cuent dawn by the cuent souce in Figue.16, should change only at low DC link voltage. The esonant cicuit is fomed by the esonant inducto L and the esonant capacito C. Since the DC link capacito C dc has a much highe capacitance than C, it does not affect the esonance behaviou. In othe wods, the DC link capacito can be egaded as a constant voltage souce. L v L i L V dc C dc i C C v C i o Figue.16 Simplified esonant DC link convete.

31 . Resonant convetes Assume that a esonant cycle stats at a capacito voltage equal to twice the DC link voltage V dc. Due to the esonant popeties of this cicuit the capacito voltage deceases towads zeo. When the voltage acoss C passes the level of the DC link voltage the inducto cuent is close to its minimum value. When the capacito voltage eaches zeo, it will be clamped to this level due to the fact that the load cuent feewheels though the feewheeling diodes, at least if the esonant inducto cuent is lowe than the load cuent which is the case if no switching is pefomed. As soon as the inducto cuent eaches the level of the load cuent, the capacito voltage stats to amp up. When the voltage acoss C passes the level of the DC link voltage the inducto cuent is at its maximum value. Fo the case whee the output cuent is not changed, the capacito voltage eaches the stating point of the analysis which equals twice the DC link voltage. The esonant DC link convete is mathematically analysed in Appendix C.. The nomalised esonant wavefoms fo the case of changing output cuent ae shown in Figue.17. Fom Figue.17 some inteesting obsevations ae made. Fist, when the output cuent i o is deceased due to a change of the convete switch state, the esonant DC link voltage esonates to a peak value highe than twice the DC link voltage V dc. Second, when the output cuent is inceased, the zeo voltage inteval is polonged and the esonant capacito voltage inceases with a modeate deivative, to a peak value close to twice the DC link voltage V dc. v C i L i o t [µs] Figue.17 Nomalised inducto cuent (black) and esonant link voltage (gey) fo a esonant DC link convete. The cuent fed to the convete is also shown (dashed). Note the esonant link voltage peak esulting fom a decease of the convete cuent. 3

32 . Resonant convetes In the fist case, thee is excess enegy stoed in the esonant inducto due to the peviously high cuent though L, coesponding to the load cuent. This enegy must decease to meet the new output cuent, which implies that the enegy must be tansfeed to the esonant capacito C. This excess enegy thus esults in a high voltage acoss the capacito. By inceasing the capacitance and deceasing the inductance, the peak capacito voltage is deceased. Howeve, the same action inceases the magnitude of the esonant cuent though L. Also the deivative of the voltage amp up inteval can be contolled by selection of the inductance and capacitance of the esonant cicuit. This is impotant in moto dive applications since it has been found that high voltage deivatives shotens the lifetime of the winding insulation of motos [46], [47], [53]. In the second case, a too small amount of enegy is stoed in the inducto, which esults in a polonged zeo voltage inteval. The length of the zeo voltage inteval is detemined by the time needed fo the inducto cuent to each the same level as the convete cuent. When the inducto cuent eaches the level of the convete cuent, the esonant capacito is being chaged, since the inducto cuent continues to ise. Since the capacito chaging cuent is low and contolled by the inducto in this case, the voltage is inceasing with a modeate deivative. The capacito voltage only eaches about twice the DC link voltage, which is due to the fact the voltage ise inteval stats at zeo voltage with zeo chaging cuent. If the esonance fequency of the DC link is much highe than the switching fequency the oscillation might be damped which means that afte some esonance cycles, zeo voltage will not be eached. This damping is due to losses of the passive components. One way to cope with this poblem is to maintain the zeo voltage inteval somewhat longe by shot cicuiting the esonant capacito with the convete switches. This foces stoage of moe enegy in the esonant inducto which in tun esults in highe capacito peak voltage. Anothe poblem of this cicuit is that caie wave PWM can not be used since the possible switching instants ae detemined by the esonant cicuit. Instead othe modulation stategies must be applied [13]. One such modulation stategy is eviewed in Appendix A. Howeve, these modulation stategies equie that the esonance fequency is much highe than the switching fequency, in ode to get a esult compaable to caie based PWM by means of output cuent spectum [46], [47]. 4

33 . Resonant convetes Seveal othe esonant link cicuits ae pesented in the liteatue. Both AC and DC link cicuits ae developed and also ZVS and ZCS esonant cicuits ae available. Anyway, the est of this epot only deals with esonant DC link cicuits intended fo poviding ZVS condition at tansisto switching. Clamp cicuits Thee ae mainly two poblems associated with the esonant DC link convetes. One poblem is that PWM cannot be used, which as peviously mentioned can be solved by inceasing the esonant link fequency. The othe poblem is the capacito voltage oveshoot following a change of switch state that deceases the cuent fed fom the DC link to the convete. This can be solved by allowing the change of switch state at a slightly highe voltage than zeo [46], [47], see Appendix C.. By using this voltage peak contol (VPC), a capacito peak voltage only slightly highe than twice the DC link voltage is obtained, even at convete switchings esulting in a decease of the esonant link output cuent. The othe way is to use a clamp cicuit, which assues that the maximum capacito voltage is limited to a cetain level by an extenal cicuit. Two methods of clamping ae poposed in the liteatue, active and passive clamping. Active clamping [14], [], utilises a capacito and an auxiliay switch to povide clamp action, see Figue.18. Hee, the esonant DC link voltage is limited to a level detemined by the voltage acoss the clamp capacito C c. When v C eaches K V dc, the anti-paallel diode of S aux stats to conduct. Thus, the esonant link voltage is clamped to this value. The paamete K is called clamping facto. (K-1) V dc C c S aux L V dc C dc C v C Figue.18 Active clamp cicuit fo the esonant DC link convete. Note that duing clamp action, the capacito C c is chaged, implying that the clamping voltage will incease if no pecautions ae made. To solve 5

34 . Resonant convetes this poblem the contollable pat of S aux has to be opeated duing the off-clamping intevals of the esonant cycle. If this is done appopiately the clamping voltage can be contolled to be almost constant. The idea is to tun on the tansisto of S aux while the diode is conducting, which means that this occus at zeo voltage. Then, S aux is kept on in ode to dischage the clamp capacito in such a way that the voltage acoss C c etuns to the value detemined by the clamp facto. Accoding to [14], a suitable value fo the clamp facto is between 1. and 1.4. In the case of passive clamping [14], a tansfome is used to achieve the desied limitation of the esonant link voltage, see Figue.19. In this case the idea is that the clamp diode D should be evese biased fo esonant link voltages less than the clamp level. When the esonant link voltage eaches the clamp level, D should be a the edge of fowad biasing. This is obtained by a pope selection of the clamping tansfome tuns atio, since at this point the seconday voltage equals V dc and the pimay voltage equals (K-1) V dc. Thus, the clamp tansfome winding tuns atio should be selected accoding to N N 1 1 = K 1 (.6) whee N 1 and N ae the numbe of winding tuns fo the clamp tansfome pimay and seconday, espectively. The clamping facto can howeve not be chosen abitaily, since it has to be ganted that the esonant link voltage fulfils the oscillation all the way down to zeo voltage. This implies that the clamping facto can not be less than two [14], fo the passively clamped esonant DC link. L 1 L V dc C dc D C v C Figue.19 A passively clamped esonant DC link convete. One majo poblem with this cicuit is that D has to sustain a high evese voltage duing the esonant DC link zeo voltage inteval. This voltage equals 6

35 . Resonant convetes V RM N = 1 + N V 1 dc (.7) Thus, fo a clamping voltage equal to two, the diode has to be able to withstand a evese voltage equal to thee times V dc. Thee ae also othe poblems associated with passive clamping, which ae discussed in late chaptes. Passive clamping is closely elated to egeneative snubbes. In fact, the passive clamping netwok is identical to a egeneative snubbe found in [63]..4 Quasi esonant DC link convetes In this section quasi esonant DC link convetes ae intoduced. The wods quasi esonant efes to the fact that these cicuits ae not continuously oscillating, but can be tiggeed by active components to pefom a esonant cycle. Hee, the cicuits ae pesented in a basic manne, which in this case means that no mathematical deivation is pefomed and no wavefoms ae shown. Instead this is shown in the next chapte. Of couse, thee ae seveal quasi esonant DC link convetes not discussed hee. Fo example, cicuits whee moe than two auxiliay switches ae needed [19], [], ae not consideed. The cicuit pesented in [11], [31] is not discussed hee since it is simila to the one pesented in [4], [41], which is discussed hee. The cicuit investigated in [1], [56], [57], [58] is not discussed hee due to its high passive component count. The passively clamped two switch quasi esonant DC link convete The fist cicuit investigated is a passively clamped two switch quasi esonant convete pesented in [7], see Figue.. Futhe wok have been caied out, focusing on implementation [8] and modulation issues [17]. The cicuit has also been futhe developed esulting in a new cicuit [9], which is discussed late on. The passive clamping cicuity is ecognised fom the pevious section. Howeve, the inducto L and the tansistos S 1 and S togethe with the diodes D 1 and D ae added. Actually, the tig on demand ability is fomed by these components. 7

36 . Resonant convetes L 1 i 1 L 3 D 1 S 1 V dc C dc i 3 D 3 L i C v C S D Figue. The passively clamped two switch quasi esonant DC link thee phase convete. When a change in convete switch state is commanded by the modulato, S 1 and S ae simultaneously tuned on. Since these tansistos ae connected in seies with L, acoss the esonant link capacito C, a dischage path fo C esults. Note that S 1 and S ae tuned on in a ZCS manne, since the cuent i is zeo initially. As the link voltage amps down, the enegy stoed in C is tansfeed to L, causing an incease of the cuent though this inducto. When C is dischaged to zeo voltage, i satuates but i 1 continues its incease since the full DC link voltage is applied acoss L 1. As long as the tansistos S 1 and S ae kept on, zeo voltage is maintained and i 1 is inceasing at a constant ate. As soon as zeo link voltage is obtained, the commanded switching state is set (ZVS). The duation of the zeo voltage inteval is selected to fulfil safe opeation, i.e. to avoid shoot though of the main cicuit tansistos. Howeve, a vey long duation of the zeo voltage inteval esults in a high cuent though L 1, which not only esults in high losses but also implies that a lage amount of enegy is stoed in the esonant cicuit. The latte poblem is discussed in late sections. When the tansistos S 1 and S ae tuned off, the cuent i commutates fom these tansistos to the diodes D 1 and D. This commutation occus unde ZVS conditions. The enegy stoed in the inducto L is tansfeed to the capacito C, which implies that the esonant link voltage begins to amp up. When the capacito voltage eaches the clamp level, detemined by the tuns atio of L 1 /L 3, it becomes clamped and the esonant excess enegy is tansfeed to the seconday winding of the clamping tansfome, i.e. L 3. Duing the clamping inteval, the cuent i 3 deceases at a constant ate detemined by the clamp tansfome seconday side self inductance, L 3, and the DC link voltage. When i 3 has declined to zeo, the clamping 8

37 . Resonant convetes inteval ends. Thus, the duation of the clamping inteval is detemined by the amount of esonant excess enegy at the stat of the inteval. Fo this quasi esonant convete, a suitable choice of clamping facto is between 1.1 and 1.3, accoding to [7]. This is consideably lowe than the value necessay fo the passively clamped esonant DC link convete descibed in the pevious section. Fo the quasi esonant countepat, the ability to each zeo voltage is guaanteed despite the low clamping facto, since the tansistos S 1 and S actually shot cicuits the esonant link capacito C, when conducting. The passively clamped one switch quasi esonant DC link convete The quasi esonant cicuit discussed in the pevious section have been futhe developed, to obtain a quasi esonant convete with low auxiliay device count. Fo the cicuit peviously descibed this is done by incopoating the esonant inducto L on the vey same coe as the clamping tansfome L 1 /L 3. An obvious advantage in doing this is that only one coe is needed. Howeve, thee is anothe advantage due to the fact that only one esonant link tansisto is needed, if mutual coupling between L and the clamping tansfome is obtained. The passively clamped one switch quasi esonant DC link is pesented in [9] and a cicuit diagam fo this cicuit used fo a thee phase convete is shown in Figue.1. L 1 i 1 L 3 M L Vdc C dc D 3 i C v C i 3 D S Figue.1 The passively clamped one switch quasi esonant DC link thee phase convete. Accoding to [9], a suitable magnetic coupling facto between inducto L and the clamping tansfome L 1 /L 3, is between.75 and.95. Essentially, this cicuit opeates simila to the peviously descibed but thee ae some diffeences egading mainly the zeo voltage inteval. Fist, due to magnetic coupling between L and L 1 /L 3 the cuent i is not constant duing the zeo voltage inteval. Second, zeo voltage is not 9

38 . Resonant convetes maintained by the tansisto S but instead by the main cicuit feewheeling diodes as fo the esonant DC link convete. Thus, fo this cicuit the duation of the zeo voltage inteval is detemined by the change of cuent fed fom the DC link to the thee phase bidge at the switching instant. It was peviously mentioned that i is not constant duing the zeo voltage inteval. Accoding to [9], a pope choice of the passive component values even esults in a change of diection of i duing the zeo voltage inteval. Fo such component values, i commutates fom the tansisto S to the diode D natually (ZCS). The paallel quasi esonant DC link convete The paallel quasi esonant DC link cicuit shown in Figue. is pesented in [41]. As seen in Figue., this cicuit has no actual clamping cicuity but instead a tansisto, S s, and its anti-paallel diode, D s, ae connected between the esonant cicuit and the DC link. In Figue., the esonant capacito is split among all the main cicuit switches, foming individual tun-off snubbes. This is due to the fact that the esonant link is only opeated fo tun-on of the convete tansistos, that actually will cay cuent. Tun-on of all these tansistos occus at the same instant. Fo tun-off of the tansistos caying cuent, i.e. cuent commutation to a feewheeling diode, soft tun-off ae povided by the snubbe capacitos. The modulation stategy adopted fo this esonant cicuit is pesented in [4], [41]. D s S s S D C s C s C s V dc C dc i L L V e C e Figue. The paallel quasi esonant DC link thee phase convete. Note the individual snubbe capacitos foming the esonant DC link capacito. One way of undestanding the modulation stategy given in [4], [41], is that it coesponds to saw-tooth caie modulation, see Appendix A, with individual caies. Whethe the steep flank of each caie is positive o negative is detemined by the diection of the output cuent fo the paticula half bidge. In this way, a modulation stategy is obtained, whee the tansistos that will cay cuent ae tuned on simultaneously. C s C s C s 3

39 . Resonant convetes Each tansisto is individually tuned off and the output cuent commutates to the coesponding feewheeling diode. Soft tun-off is povided by the coesponding snubbe capacito. The eason fo tuning on the tansistos that is going to conduct cuent is pobably that the othe tansistos should be kept off duing the entie caie peiod in ode to avoid the cuent spike poblems associated with snubbe capacito chaging, discussed peviously in this chapte. If common saw-tooth caie modulation is used, eithe tansisto of each half bidge has to be tiggeed (except duing the commutation), if the diection of the coesponding output cuent is not consideed. At tun-on, the equivalent esonant capacito is given by [41] C = 3 C (.8) s Actually, fo the simulation in Chapte 5, the esonant cicuit shown in Figue.3 is used instead, in ode to give a fai compaison among the cicuits investigated. This is due to the fact that the othe cicuits investigated uses tiangula caie modulation PWM, which theefoe should be used also fo the battey chage using this quasi esonant DC link. This means that a esonant cycle is stated when a change of switch state is commanded, independent of switching state patten and output cuent. D s S s S D V dc C dc i L C L v C V e C e Figue.3 The paallel quasi esonant DC link convete when the individual snubbe capacitos have been eplaced with an equivalent esonant link capacito. Accoding to [41], the capacito C e should be contolled to keep a voltage close to V e = 6. V (.9) To ensue that the esonant link voltage etuns to V dc afte a esonant cycle, V e must be highe than half the DC link voltage V dc, which is shown in the next chapte. dc 31

40 . Resonant convetes The esonant cycle stats with tun-on of the esonant tansisto S. Since the esonant cuent, i L, equals zeo pio to tun-on of S, this opeation takes place at ZCS conditions. As soon as the esonant cuent eaches a pe-calculated value efeed to as the tip cuent level, I 1, the tansisto S s is tuned-off (ZVS), causing dischage of the esonant link equivalent capacito. The tip cuent is selected in such a way that the capacito is completely dischaged. Thus, zeo voltage is eached. When zeo voltage is obtained, the esonant cuent i L commutates to the convete feewheeling diodes, which in effect means that the esonant link voltage is clamped to zeo by the feewheeling diodes. Also, when zeo esonant link voltage is established the main cicuit tansistos ae simultaneously tuned on. This is done to povide a path fo the esonant cuent i L, since eventually its diection will change. The esonant cuent continues to decease until the second tip cuent level I is eached. At this level the new switch state is set, esulting in the fact that the path fo the esonant cuent though the tansistos is boken. Instead, the esonant cuent begins to chage the equivalent esonant link capacito, esulting in esonant link voltage amp up. The amp up inteval continues until the esonant link voltage eaches the level of the DC link voltage V dc, whee D s becomes fowad biased and the excess esonant enegy is tansfeed back to the DC link capacito. When D s is conducting, S s is tuned on at both ZCS and ZVS conditions. As peviously mentioned, the cicuit discussed above is simila to the one pesented in [11], [31]. Howeve in the latte case, the capacitance of the enegy stoage capacito C e is much lowe. In fact, it can not be consideed as a enegy stoage capacito, since the voltage acoss it etuns to zeo afte each esonant cycle. As a esult, the esonant cuent i L must be consideably highe in ode to stoe the enegy needed to complete the esonant cycle. This cicuit is not consideed heeafte. The actively clamped quasi esonant DC link convete The last quasi esonant convete to be discussed, is efeed to as an actively clamped quasi esonant DC link convete. A thee phase convete using this quasi esonant DC link is pesented in [55], and also shown in Figue.4. 3

41 . Resonant convetes Fo quasi esonant opeation, two tansisto-diode couples, S /D and S c /D c, and a clamp capacito C c ae added to the oiginal esonant DC link cicuit. The clamp capacito is contolled to keep a constant clamp voltage. Accoding to [55], an appopiate clamp facto is 1., which means that the voltage acoss C c should equal 1. V dc. Note that the esonant link capacito C is connected between the esonant switches and the negative supply ail. L S D V dc C dc S c v Cc D c C C c v C Figue.4 The actively clamped quasi esonant DC link thee phase convete. The esonant cycle is stated with simultaneous tun-on of S and S c, esulting in a sudden incease of the voltage acoss the convete half bidges, since the clamping capacito is connected to the convete bidge via these tansistos. Also, since the clamping capacito voltage is % highe than the DC link voltage, a linealy inceasing esonant cuent stats to flow though the inducto L. When the esonant pat of the inducto cuent eaches the pe-calculated tip cuent level I 1, the tansisto S c is tuned off (ZVS), focing a dischage of the esonant capacito C. Thus, the esonant link voltage amps down. Fo this to wok, the capacitance of C must be consideably lowe than the capacitance of C c. If the tip cuent is high enough, it is ensued that the esonant capacito becomes fully dischaged and thus zeo voltage acoss the convete bidge is obtained. As the link voltage eaches zeo, the cuent though L commutates fom C to the feewheeling diodes, clamping the esonant link voltage to zeo. At this point, the convete switch state is set accoding to the modulato command. Eventually, the esonant cuent changes diection and eaches the level accoding to the new switch state. When this occus, the link voltage is no longe clamped by the feewheeling diodes. Consequently, the esonant cuent commutates to D, chaging the esonant capacito C. As a esult, the esonant link voltage amps up. When the esonant link voltage appoaches the clamp voltage level, D c becomes fowad biased. Since the capacitance of C c is much lage than 33

42 . Resonant convetes the one of C, the esonant link voltage becomes clamped to a level detemined by the voltage acoss C c. At the clamping inteval, the excess enegy emaining in L afte the amp up inteval, is fed to the clamping capacito C c. This implies that the clamping voltage will incease slightly afte each esonant cycle. On the othe hand, at the stat of each esonant cycle C c is dischaged to some extent. To compensate fo these vaiations of the clamping voltage, contol is needed. To decease the clamp voltage, the tip cuent level is slightly inceased esulting in a somewhat lage dischage of C c. Accoding to [55], the clamp voltage is inceased by shot cicuiting the thee phase bidge fo a shot while at the end of the zeo voltage inteval. In this way, moe excess enegy is held by L at the stat of the clamping inteval. The thee phase bidge is shot cicuited by tuning on both tansistos of each half bidge simultaneously. 34

43 3 Analysis and design of quasi esonant DC link convetes In this chapte, the esonant cicuits intoduced in the pevious subsection on quasi esonant DC link convetes, ae thooughly examined. Design expessions based on analytical solutions to the diffeential equations coesponding to the diffeent modes of the esonant cycle, ae deived. Each of the quasi esonant DC links ae teated sepaately, even though thee ae some similaities. Methods to select passive component values to meet specific design citeia ae also given. In Chapte 5, whee the diffeent topologies ae compaed, these methods ae then used to give an, in some aspects, simila behaviou of the diffeent quasi esonant DC link cicuits. The design citeia common to all these topologies ae, the maximum duation of the zeo voltage inteval and the maximum esonant link voltage deivative, i.e. the maximum output voltage deivative. An appopiate duation of the zeo voltage inteval is detemined by the semiconducto devices used. It must be long enough to ensue safe commutation, without an excessive shot cicuit cuent appeaing though the semiconductos of the convete. The maximum output voltage deivative is limited fo mainly two easons. Fist, a high voltage deivative with espect to time can esult in EMC poblems causing malfunction of othe electonic equipment [51]. Second, the insulation of moto o output choke windings ae subject to inceased ageing, if exposed fo continuously high voltage deivatives [9], [46], [47]. One shotcoming of the design citeia used, is that none of them takes the maximum obtainable switching fequency into consideation. Of couse, this is also an impotant design paamete since esonant convetes ae often designed to opeate at high switching fequencies, whee the switching losses othewise would be too dominating.

44 3. Analysis and design 3.1 The passively clamped two switch quasi esonant cicuit As mentioned in Chapte, the passively clamped two switch quasi esonant DC link, peviously shown in Figue., is well investigated in the liteatue [7], [8], [17]. Nevetheless, thee ae still issues to be investigated. Fo example, selection of passive component values to obtain cetain opeational citeia, which is coveed in this section. Fist, the diffeential equations and thei solutions ae deived. To some extent this is aleady done in [7], but thee ae diffeences compaed with the deivations given hee. In [8] design and implementation of this quasi esonant DC link fo an invete application, is investigated. In [17] modulation issues fo this invete, using individual snubbe capacitos as in [41], ae discussed. Nevetheless, the explicit design expessions found hee, ae not found in any of the papes [7], [8], [17]. The simplified cicuit, used in the analysis is shown in Figue 3.1, whee the convete is epesented by an ideal cuent souce and an equivalent feewheeling diode epesenting the convete feewheeling diodes. The total esonant cuent though the convete feewheeling diodes is denoted i FD. L 1 i 1 L 3 D 1 S 1 i C i o V dc C dc i 3 D 3 L i C v C i FD i o I o I o1 t 1 t S D Figue 3.1 The simplified passively clamped two switch quasi esonant DC link convete, whee the convete is epesented as an ideal cuent souce. To the ight, the esonant link output cuent change is shown. Both in Figue 3.1 and in the mathematical deivations, L 1 and L 3 denotes the clamping tansfome self inductance of the pimay and seconday, espectively. In this section, the clamping tansfome is consideed as ideal, i.e. it is consideed having pefect magnetic coupling and as being loss-less. In Figue 3., nomalised wavefoms of the main quantities of the esonant cicuit ae shown. The esonant link voltage v C is nomalised with espect to the DC link voltage V dc and the cuents ae nomalised to the maximum esonant link output cuent i o incease. 36

45 3. Analysis and design v C (a) t [µs] i 1, i, i t [µs] (b) Figue 3. Nomalised esonant link voltage (a) and inducto cuents (b). In (b), the cuent i 1 is black, i is dak gey and i 3 is light gey. The eason fo the amplitude of i 3 being low in this case is that only a small amount of excess enegy is stoed in L 1 at the end of the esonant link voltage amp up inteval. Resonant link voltage amp down inteval This inteval, efeed to as mode 1, stats with tun-on of the switches S 1 and S, following a modulato command equesting a change of the convete switch state. The system of diffeential equations is thus witten di1 L1 + vc = Vdc dt di L vc = dt dv C ic = C dt i1 i ic Io1 = (3.1) 37

46 3. Analysis and design The system is eaanged to fom a second ode odinay diffeential equation though the steps shown below. di dt di d v C = (3.) dt dt 1 C Vdc L 1 d v 1 vc + C vc L dt = (3.3) C C d v dt = LL 1 C v C L1C V dc (3.4) L + L 1 The solution to the second ode diffeential equation is L vc ( t) = Acos ω1( t t) + Bsin ω1( t t) + V L + L 1 dc (3.5) whee 1 C L + L ω 1 = LL 1 1 (3.6) By the use of (3.1), it follows that the capacito cuent is witten ic ( t) = ω CAsin ω ( t t ) + ω CBcos ω ( t t ) (3.7) Duing the off esonance inteval, i.e. when the cicuit is not in the esonant cycle, the esonant link voltage is anyway oscillating. This is due to poo damping in the L 1 -C cicuit, which means that a esonant cycle can stat fom a esonant link voltage level not equal to V dc. Fo a clamping facto K=1., v C is oscillating between.8 and 1. times V dc, see Figue 3., which makes any of the values in between equally possible as stating point. Howeve, by assuming that the esonant cycle stats at est, the initial conditions fo the esonant link capacito voltage and cuent ae witten L v ( t ) = A+ V = V L1 + L ic ( t) = ω 1CB= C dc dc (3.8) 38

47 3. Analysis and design This means that the esonant link capacito voltage and cuent ae witten as v i C C Vdc ( t) = L + L1 cos ω 1( t t) L + L 1 ( ) Vdc ( t) = sin ω 1( t t) ω L 1 (3.9) The inducto cuents ae found by integation, see Appendix C, of the diffeential equations in (3.1), i.e. 1 i1() t = i1( t) + Vdc vc ( ) d L τ τ = Io1 + ω t 1 t Vdc 1( t t) sin 1( t t) ( L + L ) ( ω ω ) 1 1 ( ) = 1 i() t = i( t) + vc ( ) d = L τ τ t t Vdc L1 = 1( t t) sin 1( t t) ( L + L ) + L ω ω ω 1 1 (3.1) (3.11) The esonant link voltage amp down inteval is finished when the esonant link capacito voltage v C equals zeo. The coesponding time instant is efeed to as t 1, hence Substitution into (3.9) and eaanging gives vc ( t1 ) = (3.1) L cos ω 1 ( t 1 t ) = (3.13) L The coesponding sine tem is found with aid of the tigonometic identity, see Appendix C. It should be clea that the sine tem is positive, since this coesponds to the shotest time, i.e. smallest agument of the sine tem. Thus 1 L sin ω 1 ( t 1 t ) = 1 L 1 (3.14) 39

48 3. Analysis and design Accoding to this, the esonant inducto cuents at the end of mode 1, ae witten V dc L L i1( t1) = Io1 + accos 1( L1 + L) L1 1 ω L1 V dc L L1 L i( t1) = accos 1( L1 + L) + L1 L 1 ω L1 (3.15) It is impotant to calculate the final values of the voltage amp down inteval since they seve as initial conditions fo the next mode of opeation, the zeo voltage inteval. Zeo voltage inteval As soon as the quasi esonant DC link entes the zeo voltage inteval, mode, the new convete switch state accoding to the modulato command is set, causing i o to change level, see Figue 3.1. The cuent equation fo mode is witten i 1 i + i FD I o = (3.16) Since the feewheeling diodes of the convete has a low fowad voltage dop (ideally zeo), it is assumed that v C ()= t (3.17) which is a easonable assumption as long as the equivalent feewheeling diode cuent, i FD, is positive. Anyway, also fo the case when i FD equals zeo this is in pinciple tue, which is due to the fact that the capacito cuent will emain low since L 1 is lage. This implies only a small capacito voltage incease, at least fo a shot duation of the zeo voltage inteval. This also means that the following diffeential equations ae valid fo the entie inteval. L L 1 di 1 dt di dt = V = dc (3.18) 4

49 3. Analysis and design The solution to the uppe of these diffeential equations ae found diectly by integation. The lowe diffeential equation states that the cuent i is constant thoughout the entie zeo voltage inteval, see Figue 3.. t 1 Vdc i1( t) = i1( t1) + Vdcd = i1( t1) + ( t t1) L τ (3.19) L 1 t 1 At the end of the zeo voltage inteval, t=t, the cuent though L 1 is given by 1 i ( t ) = I + 1 o1 V dc L L Vdc + accos ( t t1) 1( L1 + L) L1 1 ω L1 + L 1 (3.) This ends the discussion about the zeo voltage inteval, fo this cicuit. Resonant link voltage amp up inteval The esonant link voltage amp up inteval, mode 3, is the most complicated, by means of solving diffeential equations. This is due to the fact that none of the constants of the solution to the diffeential equations ae equal to zeo, as B is fo mode 1. Nevetheless, mode 3 is the most impotant since hee it is detemined whethe the capacito voltage amps up in a contolled manne o not, i.e. without a voltage dip in the intemediate sections of the inteval. Also, the maximum esonant link voltage deivative, which is an impotant design paamete, appeas in this mode. Mode 3 stats when S 1 and S ae tuned off by application of pope gate signals. Since S 1 and S ae tuned off, the esonant inducto cuent i is foced to commutate to the diodes D 1 and D. The voltage v C amps up with a high deivative, since both i 1 and i contibutes to the capacito cuent i C, which is not the case when the esonant pat of the feewheeling diode cuent i FD becomes zeo in the zeo voltage inteval. The system of diffeential equations is simila to the one of mode 1, except that the cuent i has changed diection, thus 41

50 3. Analysis and design di1 L1 + vc = Vdc dt di L + vc = dt dvc ic = C dt i1 + i ic Io = (3.1) Also in mode 3, substitution gives a second ode diffeential equation C d v dt = LL 1 C v C L1C V dc (3.) L + L 1 Note that the diffeential equation is the same as the one found fo mode 1. Theefoe, the solution is witten L vc ( t) = Acos ω1( t t) + Bsin ω1( t t) + V L + L 1 dc (3.3) which gives the coesponding capacito cuent accoding to (3.1), i.e. i ( t) = ω CAsin ω ( t t ) + ω CB cos ω ( t t ) C (3.4) The constants A and B ae found by identifying the initial capacito voltage and cuent, fo the mode. The initial capacito voltage is witten L vc ( t ) = A+ V L + L 1 dc = (3.5) and the initial capacito cuent i ( t ) = ω CB = i ( t ) + i ( t ) I = C o V dc L L1 L = accos 1( L1 + L) + L1 L 1 1 ω L1 Vdc + ( t t ) Io I L 1 ( ) 1 o1 + (3.6) 4

51 3. Analysis and design This gives an expession fo the constant B valid fo the esonant link voltage amp up inteval, which is used late on when the design citeia ae developed. The esonant inducto cuents ae found by integation 1 i1() t = i1( t) + Vdc vc ( ) d L τ τ t 1 t Vdc = i1( t) + ω 1( t t) ω L + L Asin ω1( t t) + B1 cos ω1( t t) ω L 1 1 ( ) = ( ) ( ( )) 1 i() t = i( t) vc ( ) d = L τ τ t t Vdc = i( t) ω 1( t t) ω L + L Asin ω1( t t) + B1 cos ω1( t t) ω L 1 ( ) ( ( )) (3.7) (3.8) This means that the link voltage amp up inteval is chaacteised. Anyway, the complicated expessions deived, can hadly be used fo design puposes. Fo the discussion on final values valid fo this mode, it is assumed that clamping occus befoe the esonant inducto cuent i has declined to zeo. This is not always the case but when component values accoding to the late deived design expessions ae used, the opposite occus only fo a lage esonant link output cuent incease. Fo such a lage incease, clamping will not occu anyway, with the component values selected. Fo the case when clamping do appea, the final esonant capacito voltage is whee K is the clamping facto, which is given by v ()= t KV (3.9) C dc N1 L1 K = 1+ = 1 + (3.3) N L 3 whee N 1 and N 3 denotes the clamping tansfome numbe of winding tuns fo the pimay and seconday, espectively. 3 43

52 3. Analysis and design The pevious two expessions ae deived, based on the fact that clamping occus when the voltage acoss the tansfome seconday (index 3) equals the DC link voltage V dc. The constants A and B valid fo mode 3 togethe with esonant the DC link clamping voltage given above, ae substituted into the design ule given in Appendix C.1, esulting in L ic ( t3 ) = ω 1C KVdc K + B (3.31) L + L 1 As discussed in the section on the clamping inteval, this final value is enough fo chaacteising the inteval, by means of initial conditions. Clamping inteval When clamping occus, the excess enegy stoed in the clamping tansfome pimay (index 1) is tansfeed to the seconday (index 3). Thus, the pimay cuent is given by i 1 = i + I o (3.3) The pevious expession togethe with the cuent constaint of (3.1), diectly gives the initial value of the seconday cuent i + N1 t N i t i t + N1 ( ) 1( 3 ) 1( 3 ) N i C ( t = ( )= 3 ) (3.33) The voltages acoss the esonant DC link components ae constant duing the clamping inteval, esulting in 3 L L 3 di dt di + vc = L + KVdc = dt di3 + Vdc = dt (3.34) The esonant inducto cuent i is deived by integation t 1 KVdc i( t) = i( t3) KVdcd = i( t3) ( t t3) L τ (3.35) L t The clamping cuent i 3 is also found by integation 3 44

53 3. Analysis and design t Vdc i3( t) = i3( t3 ) Vdcd = i3( t3 ) ( t t3 ) L τ (3.36) L 3 t 3 The clamping inteval is finished when i 3 has declined to zeo. The coesponding time instant is denoted as t 4, i.e. i 3 ( t )= (3.37) 3 4 which gives the duation of the clamping inteval L3 tclamp = t t = V i t ( 3 ) (3.38) Afte a completed clamping inteval, a new esonant cycle can be initiated immediately. Howeve, if the clamping inteval is not completed, the enegy stoed in the seconday of the tansfome (index 3) is tansfeed to the pimay, esulting in a high magnitude of the esonant inducto cuent i. This is not allowed, since the cuent stess on the tansistos S 1 and S is inceased in such a case. Off esonance inteval Afte a completed clamping inteval, the off esonance inteval commences. The name is somewhat misleading fo this cicuit, since even though i equals zeo, L 1 and C still foms a esonant cicuit. This implies that the oscillation of the esonant link voltage will continue. The amplitude of the oscillating voltage is detemined by the clamping facto, as descibed in this section. The system is in this case descibed by dc di1 L1 + vc = V dt dvc ic = C dt i1 ic Io = dc (3.39) By eaanging the system of diffeential equations, a second ode diffeential equation is obtained The solution is witten C d v = dt L C v C L C V dc (3.4)

54 3. Analysis and design vc ( t) = Acos ω( t t4 ) + Bsin ω( t t4 ) + V (3.41) whee A and B ae constants and dc 1 C ω = L1 (3.4) The capacito cuent is found by substituting (3.41) into (3.39), which gives ic ( t) = ω CAsin ω ( t t ) + ω CB cos ω ( t t ) 4 4 (3.43) Since clamping in most cases occus pio to the off esonance inteval, the initial conditions ae v ( t4) = A+ V = KV ic ( t4 ) = ω CB= C dc dc (3.44) The initial capacito cuent is equal to zeo accoding to (3.39), since at the end of the clamping inteval i 1 equals I o. The capacito voltage and cuent fo the off esonance inteval ae thus witten vc ( t) = Vdc ( 1+ ( K 1) cos ω ( t t4 )) C ic ( t) = ( K 1) V dc sin ω ( t t 4 ) L1 (3.45) Hee it is clealy seen that fo the off esonance inteval, the esonant DC link voltage will oscillate between ( K) V v () t KV (3.46) dc C dc if damping is neglected. The clamping facto used thoughout the entie text equals 1., which means that the esonant link capacito voltage will vay between.8 and 1. times V dc, see Figue 3.. Note that fo the next esonant cycle, any initial voltage in between is equally pobable, which was also stated in the deivation made fo the esonant link voltage amp down inteval. Design expessions The design citeia ae based on thee diffeent constaints, since thee ae thee component values to be selected, L 1, L and C. The fist two 46

55 3. Analysis and design design constaints ae the duation of the zeo voltage inteval and the maximum esonant DC link voltage deivative obtained. These two ae used fo all the quasi-esonant cicuits investigated. The thid constaint used fo this cicuit, aims fo limitation of the cuent i. To stat with, L 1 is calculated in such a way that the esonant cycle is completed in an acceptable manne. Fo the maximum incease of the output cuent, i o, the capacito cuent should not be negative when i 1 has inceased to I o at the end of the esonant link voltage amp up inteval. If the esonant capacito cuent is negative at this point, the capacito voltage is deceasing instead of inceasing. The limiting case is thus given by i ( t ) = Io ic ( t3) = 1 3 (3.47) Togethe with the expession fo the cuents of equation system (3.1), it is also found that i ( t )= (3.48) 3 fo this case. Since the capacito cuent should equal zeo at the end of the amp up inteval fo the limiting case, (3.4) gives Reaanging this equation gives Asin ω ( t t ) = Bcos ω ( t t ) (3.49) B= Atan ω 1 ( t 3 t ) (3.5) Substitution into (3.8) and using the final value fo i accoding to (3.48) gives Assume i ( V t ) dc ( ω1 t3 t 1 t3 t L + L ( ) tan ω ω ( ))= (3.51) ( ) 1 1 sin ω1( t3 t) = 1 α cos ω1( t3 t) = α (3.5) which gives 47

56 3. Analysis and design tan ω ( t t ) = α α (3.53) Substitution into expession (3.51) above gives i ( V t ) dc = 1 L1 + L accos( α ω ) ( ) + 1 α α (3.54) The coesponding cuent found in the investigation of the zeo voltage inteval, i.e. equation (3.15), states that i ( t ) = i ( t ) = 1 V dc L = accos 1( L1 + L) ω L L1 L + 1 L 1 L1 (3.55) By compaing the pevious two expessions fo i, it is found that α = L L1 (3.56) which means that in this case, the esonant link voltage amp down and amp up intevals have the same duation. To get a moe compact desciption, (3.56) is substituted into all the expessions heeafte. As peviously mentioned, it is not the output cuent level but the change of the output cuent level that detemines the wost case. Also, the cuent i 1 inceases most fo a zeo voltage inteval of maximum duation. Inseting this into equation (3.7) and using the limiting value fo i 1 in (3.47) above, gives Vdc i1( t3) = Io1 + accos( α) 1 α ω L ( 1 + α) 1 1 Vdc + ( t t ) = I L 1 1 max o ( ) + (3.57) Reaanging the pevious expession gives the uppe limit fo the inductance L 1 accoding to 48

57 3. Analysis and design V dc L 1 = ω1( Io Io1) max Vdc ( t t ) + I I 1 max ( ) o o1 max ( ) + accos( α) 1 α 1 + α (3.58) This value of L 1 is calculated upon the maximum duation of the zeo voltage inteval. The next constaint to be fulfilled is to limit the maximum esonant link voltage deivative, i.e. the maximum output voltage deivative. By assuming the maximum negative output cuent change fo a esonant cycle to equal the maximum positive, by means of magnitude, i.e. ( I I ) = ( I I ) (3.59) o o1 min o o1 max the maximum value of the constant B fo mode 3 is found by inseting (3.58) into equation (3.6) and eaanging. Hence α 3 α Bmax = 4Vdc accos( α) Vdc ( 1 + α) ( 1 + α) α + Vdc ( 1 t t1 max + 1 t t1 ) 1 + α ω ( ) ω ( ) 1 α + If the duation of the zeo voltage inteval is held constant, i.e. it is found that α Bmax = 4Vdc accos( α) V ( 1 + α) α + Vdc 1 t t1 max 1 + α ω ( ) (3.6) ω ( t t ) = ω ( t t ) (3.61) max 3 α ( 1 + α) dc 1 α + (3.6) The maximum esonant link voltage deivative is calculated fom expession (3.3). With the value fo the constant A fom (3.5), substituted into this deivative it is found that dv dt C max = ω 1 dc + Bmax α V 1 + α (3.63) The last design constaint is used to limit the cuent i in ode to keep the cuent ating of the esonant link semiconductos, S 1 /S and D 1 /D, at 49

58 3. Analysis and design an acceptable level. Accoding to expession (3.15), the peak value of i is given by V i t dc ( 1 ) = 1L accos( ) 1( + ) + 1 α ω α α 1 α (3.64) The design expessions (3.58), (3.63) and (3.64) togethe detemines L 1, ω 1 and α, which in effect means that L 1, L and C ae detemined. Howeve, to find the pope values, the calculation of these thee expessions have to be iteated. 3. The passively clamped one switch quasi esonant cicuit The passively clamped one switch quasi esonant cicuit descibed hee is a futhe development of the two switch countepat descibed in the pevious section. A simplified convete using the passively clamped one switch quasi esonant DC link is shown in Figue 3.3. Since the cicuit has only one additional switch, the esonant inducto cuent i can not be foced to commutate fom S to D to initiate the esonant DC link voltage amp up inteval. Instead, mutual magnetic coupling between L 1 /L 3 and L is employed in ode to obtain inheent evesal of i. To obtain mutual magnetic coupling, L 1 /L 3 and L ae wound upon the same ion coe. In Figue 3.3 the mutual coupling is shown by the M located between L 1 /L 3 and L. L 1 i 1 L 3 D 3 M i L i C V dc Cdc C v C i o i o I o i 3 D i FD I o1 t 1 t S Figue 3.3 The passively clamped one switch quasi esonant DC link with a simplified convete equivalent consisting of a cuent souce and an equivalent feewheeling diode. To the ight, a esonant link output cuent change is shown. Due to the magnetic coupling between the pimay (index 1) and the seconday (index ) windings, the voltages acoss the coesponding windings ae witten 5

59 3. Analysis and design v v d di1 di = ( Li + Mi )= L + M dt dt dt d di1 = ( Mi +L i )= M +L dt dt 1 di dt (3.65) The mutual inductance is given by M = k LL 1 (3.66) whee k is the magnetic coupling facto, fo the pimay and seconday windings. Note that the tetiay winding also should be included in the expessions fo the winding voltages. Thee ae mainly two easons fo not doing this hee. Fist, the magnetic coupling facto is assumed to be equal to one fo the pimay and tetiay windings, i.e. the clamp tansfome is egaded as being ideal. Second, the seconday and tetiay windings do not cay cuent simultaneously fo this cicuit. The passively clamped one switch quasi esonant cicuit is pesented in [9], togethe with the diffeential equations and thei solutions fo each mode. Howeve, selection of appopiate passive component values is not discussed in [9]. In this section, the diffeential equations and thei solutions ae given fo each mode of opeation. Futhemoe, design expessions developed to meet cetain constaints ae pesented. In Figue 3.4 nomalised wavefoms of the quantities of main inteest fo this cicuit ae shown. The esonant link voltage v C is nomalised with espect to the DC link voltage V dc. The esonant link cuents in Figue 3.4 ae nomalised with espect to the maximum incease of the esonant link output cuent i o, which the esonant link is designed to meet. Seveal inteesting obsevations ae made fom Figue 3.4. The high magnitude of the esonant inducto cuent i is clealy seen. The magnitude of this cuent is actually seveal times highe than the output cuent, implying that the esonant link semiconductos must have a cuent ating seveal times highe than the convete semiconductos. Also note that the esonant link voltage amp up inteval is divided into two pats, with lage diffeences in the deivative which the voltage inceases with. Also, between these two pats, the esonant link voltage is actually deceasing fo a shot while. The oigin of this decease is discussed in Chapte 5. 51

60 3. Analysis and design v C (a) t [µs] i 1, i, i (b) t [µs] Figue 3.4 Nomalised esonant link voltage (a) and inducto cuents (b). In (b), the cuent i 1 is black, i is dak gey and i 3 is light gey. Fo the esonant cycle shown in Figue 3.4 it should be noted that the shot duation of the clamping inteval at the end of the cycle, is because only a small of amount of excess enegy has to be etuned to the DC link capacito, since the esonant link output cuent incease is elatively high. This also esults in a low clamp tansfome cuent i 3 duing the clamping inteval. The duation of the clamping inteval depends on the magnitude of the esonant link output cuent change, fo the paticula esonant cycle, which is discussed late on in this section. Resonant link voltage amp down inteval The esonant link voltage amp down inteval, is initiated with tun-on of the esonant tansisto S, following a modulato command. The esulting system of diffeential equations valid fo mode 1, which this inteval is temed, is given below. 5

61 3. Analysis and design di1 di L1 + M + vc = V dt dt di1 di M + L vc = dt dt dvc ic = C dt i1 i ic Io1 = dc (3.67) By eaanging the system of diffeential equations above, two diffeential equations ae obtained di dt L + LL M L v C = Vdc (3.68) M LL M d 1 d v ( L1 + M) i MC + v C = Vdc (3.69) dt dt which ae substituted to fom a second ode diffeential equation C 1 C d v dt 1 L + M + v = ( LL 1 M ) C C ( LL 1 M ) C Vdc (3.7) L + L + M 1 The solution to the second ode diffeential equation is L + M vc( t) = Acos ω1( t t) + Bsin ω1( t t) + L + L + M V 1 dc (3.71) whee the chaacteistic angula fequency, ω 1, is given by ω 1 = LL 1 L 1 M + L + M C 1 (3.7) Accoding to (3.67), the esonant link capacito cuent is expessed as ic( t) = ω CA sin ω ( t t ) + ω CB cos ω ( t t ) (3.73) The constants A and B ae given by the initial conditions of the esonant link capacito voltage and cuent, espectively, accoding to 53

62 3. Analysis and design L + M v ( t ) = A + L M V 1 + L + ic( t) = ω1cb = = V C dc dc (3.74) Note that it is assumed that the esonant link stats at est. Late on it is shown that this is not necessaily tue, simila to the case fo the two switch countepat discussed in the pevious section. With the initial conditions stated above, the capacito voltage and cuent ae given by v i C C Vdc ( t) = ( L + M)+ ( L1 + M) cos ω1( t t) L + L + M 1 ( ) Vdc L1 + M ( t) = sin ω ( t t ) 1 ω LL M ( ) 1 1 ( ) (3.75) Integating (3.68) gives t ( ) = o1+ 1 i1() t = i1( t) + L Vdc L + M vc ( ) d I ( ) LL M τ τ 1 t Vdc L1 M L M + 1( t t) sin 1( t t) ( L + L + M) + ω ω ω LL M 1 1 ( )( + ) 1 (3.76) The algebaic cuent equation of (3.67) gives i () t = i () t i () t I = 1 C o1 ( ) Vdc L1 M = 1( t t) sin 1( t t) 1( L1 + L + M) + + ω ω ω LL 1 M (3.77) The esonant link voltage amp down inteval is finished when vc ( t1 ) = (3.78) which togethe with (3.75) gives L cos ( t t ) = L ω M + M (3.79) Accoding to the tigonometic identity it is found that 54

63 3. Analysis and design L sin ( t t ) = 1 L ω M + M (3.8) It should be clea that the last quantity is positive, since it should coespond to the shotest time. Substituting into (3.75) gives i C Vdc L ( t1) = LL + M 1 ω 1 1 M L + M 1 (3.81) L + M 1 Similaly, substituting into (3.76) and (3.77) gives the inducto cuents at the end of the esonant link voltage amp down inteval. Vdc i1( t1) = Io1 + accos ω L + L + M L 1( 1 ) + L1 Vdc L M ( L + L + M) + ω LL M ( ) 1 Vdc L M i( t1) = accos ( L + L + M) + + ω L + M Vdc L1 M + ( L + L + M) + ω LL M 1 1 ( ) 1 1 L 1 L M + M L L M + M M M 1 (3.8) (3.83) The final values of the esonant link voltage amp down inteval, by means of inducto cuents, ae used as initial conditions fo the zeo voltage inteval. Zeo voltage inteval As soon as the zeo voltage inteval (mode ) is enteed, the new switch state accoding to the modulato command should be set. Howeve, this do not affect the esonant link since the capacito voltage is clamped to zeo by the feewheeling diodes of the convete. In effect, this means that the esonant cuent flows though the feewheeling diodes which is the eason why an equivalent feewheeling diode must be included in the simplified convete equivalent. This implies that fo the zeo voltage inteval, the system of diffeential equations is given by 55

64 3. Analysis and design V v V L di 1 M di dc 1 = dc 1 = dt dt v = M di 1 + L di = dt dt i1 i + ifd Io = (3.84) The fist two equations ae eaanged to di1 L = dt M V dc LL 1 di M = dt LL M V 1 dc (3.85) Hence, the inducto cuents of mode ae found by integation L i1() t = i1( t1) + LL M 1 V dτ = L = i1( t1) + Vdc ( M t t 1) LL 1 M i() t = i( t1) LL M 1 t t 1 dc V dτ = M = i( t1) Vdc ( M t t 1) LL 1 t t 1 dc (3.86) (3.87) The cuent equation of the equation system (3.84), togethe with the esonant inducto cuents (3.86) and (3.87) with the final values (3.8) and (3.83) of the esonant link voltage amp down inteval substituted, gives the cuent though the equivalent feewheeling diode i () t = I i () t + i () t = FD o 1 Vdc = ω 1 ( L + L + M) L L + ( I I ) V 1 1 LL 1 M o o1 dc L + M ( M t t 1) LL 1 ( ) + (3.88) 56

65 3. Analysis and design In opposite to the two switch countepat, the zeo voltage inteval cannot be polonged by keeping the esonant link tansisto on. Instead, the zeo voltage inteval is finished when i FD has deceased to zeo, which means that the esonant cuent commutates fom the convete feewheeling diodes to the esonant link capacito C. The time instant when this occus is denoted t. Hence Actually, this is equivalent to i FD ( t ) = (3.89) i 1 ( t ) i ( t ) = I o (3.9) Any of the last two expessions gives the duation of the zeo voltage inteval 1 ( t t1) = ω 1 L L 1 + M M ( Io Io1) LL 1 M V L + M dc (3.91) If (3.8) and (3.91) ae substituted into (3.86), the esonant inducto cuent i 1 at the end of the zeo voltage inteval is found to be Vdc i1( t) = Io1 + accos ω L + L + M + ω L 1( 1 ) + L1 Vdc + L + M L1 1( L1 ) + L M + + M M L 1 + M M I o + L + I ( ) o1 (3.9) Simila, if (3.83) and (3.91) ae substituted into (3.87), the esonant inducto cuent i at the time instant t, is expessed by i Vdc ( t ) = accos ω L + L + M + ω L 1( 1 ) + L1 M + + M Vdc L1 1( L1 + L + M) + L M M 1 M M I o + L + I ( ) o1 (3.93) Thee is one impotant emak to be made hee, which is that the esonant inducto cuent i should change sign, i.e. become negative, duing the zeo voltage inteval, see Figue 3.4. This is impotant since it implies that the tansisto S tuns off natually, i.e. i commutates fom S to D by it self without emoval of the gating signal of S. Accoding to [9] this 57

66 3. Analysis and design is fulfilled if the magnetic coupling facto k, between L 1 and L is in the inteval [.75<k<.95]. The esonant link voltage amp up inteval Fo this cicuit, the esonant link voltage amp up inteval actually consists of two modes. The fist pat, mode 3, is the pat with non-zeo esonant cuent i. The second pat, mode 4, is when the cuent i equals zeo. As a matte of fact, thee is an quite lage diffeence between these two modes due to the change in chaacteistic angula fequency when tavesing fom mode 3 to 4, see Figue 3.4. Fo mode 3, the system of diffeential equations is witten di1 di L1 + M + vc = V dt dt di1 di M + L vc = dt dt dvc ic = C dt i1 i ic Io = dc (3.94) Note the similaities with the equation system of mode 1, (3.67). The equation system is eaanged into a second ode diffeential equation though the same steps as fo mode 1, which gives C d v dt 1 L + M + v = ( LL 1 M ) C C ( LL 1 M ) C Vdc (3.95) L + L + M 1 The geneal solution to the diffeential equation above is witten L + M vc( t) = Acos ω1( t t) + Bsin ω1( t t) + L + L + M V 1 dc (3.96) Which also implies that the capacito cuent is given by i ( t) = ω CA sin ω ( t t ) + ω CB cos ω ( t t ) C (3.97) The constants A and B ae detemined fom the initial conditions 58

67 3. Analysis and design L + M vc( t ) = A + L M V 1 + L + ic( t) = ω1cb = dc = (3.98) The esonant link capacito voltage and cuent ae thus expessed as v i C C L + M ( t) = M V dc 1 cos ω1( t t ) L + L + 1 ( ) ( ) Vdc L + M ( t) = sin ω ( t t ) 1 ω LL M ( ) 1 1 (3.99) Simila to the esonant link voltage amp down inteval, the equation system (3.94) is eaanged to get expessions whee the esonant inducto cuents ae calculated fom integation. This gives 1 i1() t = i1( t) + LVdc L + M vc ( ) d ( ) LL M τ τ 1 Vdc = i1( t) + ω 1( t t) + ω L + L + M 1 1 Vdc L M + ( L + L + M) + ω LL M 1 1 ( ) i () t = i () t i () t I = 1 C o t t ( ) = ( ) 1 sin ω ( t t ) 1 Vdc = i( t) + ω 1( t t) ω 1( L1 + L + M) Vdc ( L1 M L M sin 1( t t) ( L + L + M) + )( + ) ω ω LL M (3.1) (3.11) The fist pat of the esonant link voltage amp up inteval, i.e. mode 3, ends as peviously mentioned when i ( t )= (3.1) 3 Consequently, the duation of mode 3 must be calculated fom the nonlinea equation 59

68 3. Analysis and design L1 + M L M ω1( t3 t) sin ω1( t3 t) = LL M L = accos L M + + M L L ω1 L1 + L + M M V L M I I dc ( )( + ) ( ) M 1 + M ( ) o o1 (3.13) Since the expession above is non-linea, the final values of mode 3 fo the othe state vaiables can not be expessed with the time dependent tems substituted. The system of diffeential equations fo mode 4 is simila to the one of the pevious mode (3.94), with i and its time deivative set equal to zeo. di1 L1 + vc = V dt dvc ic = C dt i1 ic Io = dc (3.14) This is eaanged to fom a second ode diffeential equation C d v dt + 1 L = 1 C v C L C V dc (3.15) 1 1 The geneal solution to the diffeential equation is given by vc( t) = Acos ω( t t3) + Bsin ω( t t3 ) + V (3.16) whee the chaacteistic angula fequency ω equals dc 1 C ω = L1 (3.17) The esonant link capacito cuent, i C, is calculated accoding to (3.14), giving ic ( t) = ω CA sin ω ( t t3) + ω CB cos ω ( t t3 ) (3.18) 6

69 3. Analysis and design The algebaic cuent equation of (3.94) togethe with (3.1) and the cuent equation of (3.14), gives i ( t ) = i ( t ) I = i ( t ) I = i ( t ) (3.19) C o o C 3 + stating that the initial capacito cuent of mode 4 is equal to the ending capacito cuent of mode 3. This means that the constants of the geneal solution ae found fom the initial conditions accoding to L + M vc ( t3 ) = A+ Vdc = Vdc 1 cos ω 1( t3 t) L1 + L + M i t CB V dc L + M C ( 3) = ω = sin ω 1( t3 t) ω 1 LL 1 M ( ) (3.11) Reaanging gives the constants Vdc A = ( L1 + M)+ ( L + M) cos ω 1( t3 t) L1 + L + M ω 1 L + M B= Vdc sin ω 1( t3 t) ω L1 + L + M ( ) (3.111) The esonant link voltage amp up inteval is finished when the clamping voltage level is eached, i.e. when v ()= t KV (3.11) C The method used to calculate final values, see Appendix C, gives dc i ( t ) = C A + B ω V ( K 1 ) (3.113) C 4 Accoding to the cuent equation of (3.14) it is also found that The clamping inteval dc 1 4 C 4 o i ( t ) = i ( t ) + I (3.114) Since clamping occus when the diode D 3 becomes fowad biased, the clamping facto K is detemined by the tuns atio between the pimay and tetiay windings N1 L1 K= 1+ = 1+ (3.115) N L

70 3. Analysis and design whee N 1 and N 3 ae the numbe of winding tuns fo the pimay and tetiay winding, espectively. The excess magnetic enegy stoed in the pimay, is tansfeed to the tetiay winding, giving i o i = i ( t ) = I (3.116) + N1 t N i t i t + N1 ( ) 1( 4) 1( 4) N i C( t = ( )= 4 ) (3.117) 3 4 Neglecting the fowad voltage dop acoss D 3 gives 3 di3 L 3 dt 3 + V dc = (3.118) This fist ode diffeential equation is solved by diect integation t Vdc i3( t) = i3( t4) Vdcd = i3( t4) ( t t4 ) L τ (3.119) L 3 t The clamping inteval ends when i 3 has declined to zeo, i.e. 4 i 3 ( t )= (3.1) 3 5 Hence, the duation of the clamping inteval equals Off Resonance L3 tclamp = t t = V i t ( 4 ) (3.11) When the excess esonant enegy has been tansfeed back to the DC link capacito, i.e. when the clamping inteval is finished, the quasi esonant DC link cicuit is eady fo a new cycle. Howeve, the cicuit is not at est since an oscillation is stated in the esonant cicuit fomed by L 1 and C, see Figue 3.4. The system of diffeential equations fo the off esonance inteval is given by dc di1 L1 + vc = V dt dvc ic = C dt i1 ic Io = dc (3.1) 6

71 3. Analysis and design This is actually the same as the one valid fo mode 4 of the esonant link voltage amp up inteval. Consequently, substitution to obtain a second ode diffeential equation gives the same esult C d v = dt L C v C L C V dc (3.13) 1 1 The geneal solution to the diffeential equation above gives the esonant link capacito voltage vc( t) = Acos ω( t t5) + Bsin ω( t t5 ) + V (3.14) The coesponding cuent is found by deivation ic( t) = ωca sin ω( t t5) + ωcb cos ω( t t5 ) (3.15) The initial conditions fo the esonant capacito voltage and cuent ae used to detemine the constants A and B of the geneal solution v ( t5 ) = A+ V = KV ic ( t5 ) = ω CB= C dc dc dc (3.16) esulting in the following expessions fo the capacito voltage and cuent vc ( t) = Vdc ( 1+ ( K 1) cos ω ( t t5 )) C ic ( t) = ( K 1) V dc sin ω ( t t 5 ) L1 (3.17) As fo the two switch countepat, the esonant link voltage will oscillate between ( K) V v () t KV (3.18) dc C dc also fo the passively clamped one switch quasi esonant cicuit, duing the off esonance inteval. If the clamping facto K equals 1., the esonant link voltage is thus oscillating between.8 and 1. times the DC link voltage, see Figue

72 3. Analysis and design Design expessions Also fo this cicuit design expessions ae deived based upon the duation of the zeo voltage inteval and maximum esonant link voltage deivative. Nevetheless, the most impotant design objective is to ensue that the esonant cicuit is able to complete its cycle at the wost case loading. Theefoe, this is teated fist. Fo mode 3 of the esonant link voltage amp up inteval, it was peviously stated that it ends when i ( t )= (3.19) 3 Fo pope opeation it is also desiable that i ( t ) (3.13) C 3 If the last expession is not fulfilled, the esonant link voltage has aleady stated do decease. The esonant link capacito cuent is given by (3.99) which fo this case gives which is equivalent to sin ( t t ) (3.131) ω 1 3 ω ( t t ) π (3.13) 1 3 Also note that (3.19) and (3.13) togethe ae equivalent to To simplify the expessions, the substitution i 1 ( t 3 ) I o (3.133) α = L L1 (3.134) is used which gives the mutual inductance M = k LL 1 = L1k α (3.135) The limiting case substituted into (3.1) gives 64

73 3. Analysis and design Vdc α k i1( t3) = Io = Io1 + accos ω L 1+ α + k α 1 + k 1 1 ( ) + Vdc k + 1L1( + + k ) 1 + α 1 + ω 1 α α α + k α α Vdc + ( Io Io1)+ α + k α ω L 1+ α + k α π 1 1 ( ) α + α (3.136) Reaanging the tems, gives the maximum value of L 1 accoding to V dc L 1 = ω 1( Io Io1) max k α + k π + accos 1 + k α + k α α 1+ α + k α α + α ( ) 1 + α + k k α α 1 (3.137) Fo this cicuit, the duation of the zeo voltage inteval depends on the magnitude of the output cuent, i o, change duing the esonant cycle. Fo the maximum change, the duation of the zeo voltage inteval also becomes the longest. Accoding to (3.91) the maximum duation is 1 1+ k α ( t t1) max = 1 + ω 1 α + k α ( Io Io1) max α k α + V α + k α dc L 1 (3.138) The maximum esonant link voltage deivative fo mode 1, is calculated fom (3.75), which gives dv dt C max = ω V 1 dc L L1 + M = ω1v + L + M 1 dc 1 + k α 1+ α + k α (3.139) Fo mode 3, the maximum esonant link voltage deivative is calculated fom (3.99), which gives dv dt C max = ω V 1 dc L L + M α + k α = ω1vdc + L + M 1+ α + k α 1 (3.14) Since 65

74 3. Analysis and design α < 1 (3.141) accoding to [9], the maximum voltage deivative is obtained duing the esonant link voltage amp down inteval. In ode to select appopiate passive component values fo the passively clamped one switch quasi esonant DC link, the equations (3.137), (3.138) and (3.139) ae used. This gives appopiate values fo L 1, α and ω 1, which ae used to calculate the coesponding values of L 1, L and C. Note that the magnetic coupling facto, k, between the inductos L 1 and L is not used as a design vaiable. This could be used to minimise the peak value of esonant cuent i. Anyway, it is not that easy to design the esonant inductos L 1 and L on the same magnetic coe to obtain a cetain coupling facto. It is likely that the thee winding tansfome is designed to have an as high magnetic coupling facto as possible and then intoduce an additional inducto in seies with the seconday winding to tune the inductance of L. 3.3 The paallel quasi esonant cicuit The paallel quasi esonant DC link convete is descibed in [41]. In [4], modulation issues ae discussed. In both these papes the esonant link capacito is split among the half bidges of the convete to fom individual snubbe capacitos. This is needed due to the modulation stategy used, which was discussed in Chapte. Hee, this modulation stategy is not used. Instead, tiangula caie PWM, see Appendix A, is used to be able to give an as fai as possible compaison. In Figue 3.5, a simplified vesion of the convete using this quasi esonant DC link is shown. Hee, the individual snubbe capacitos ae eplaced by one single equivalent esonant link capacito C. This is also done in [41], but only to simplify the analysis. D s S s S D i C i o I o V dc C dc i L C L v C i o V e C e I o1 t3 t Figue 3.5 The paallel quasi esonant DC link cicuit with a simplified convete equivalent, containing one tansisto and one diode togethe with a cuent souce. To the ight, an output cuent change is shown. 66

75 3. Analysis and design The convete equivalent in Figue 3.5 consists of a cuent souce and also a tansisto and a feewheeling diode. Fo the pevious two quasi esonant DC links, the convete equivalent have not been equipped with a tansisto acoss the esonant link. The eason why it is needed hee, is the fact that the esonant cuent though the feewheeling diode must be allowed to change sign, i.e. commutate fom the convete feewheeling diodes to the tansistos. This implies that not only the feewheeling diodes ae clamping the link voltage to zeo, but also the tansistos. When the cuent though the equivalent tansisto equals the esonant link output cuent i o, accoding to the new switch state, this should be set, i.e. one tansisto of each convete half bidge is tuned off. By keeping the esonant link shot cicuited fo a longe time, moe enegy is tansfeed fom the enegy stoage capacito C e to the esonant inducto L, causing a decease of V e. To incease the voltage V e, the esonant link tansistos S s and S ae kept on simultaneously fo a slightly longe time than needed to ensue that the esonant link voltage amp down inteval is completed, at the beginning of the esonant cycle. Thus, moe enegy is tansfeed fom the DC link capacito to the enegy stoage capacito. To contol the enegy stoage capacito voltage V e, the magins intoduced fo the tip cuents ae vaied. This is discussed when the expessions fo the tip cuent levels ae deived, late on in this section. Howeve, fo the deivation of the diffeential equations and thei solutions, the voltage acoss the enegy stoage capacito C e is consideed as being constant. In ode to ensue completion of the esonant cycle, this voltage should be contolled to equal V e = 6. V (3.14) accoding to [41]. The eason fo this value being suitable is shown late on. In Figue 3.6 a esonant cycle is shown. The quantities shown in Figue 3.6 ae nomalised, whee the voltage base value is the DC link voltage V dc and the cuent base value is selected as the maximum esonant link output cuent incease duing one cycle, which the esonant link is designed to meet. dc 67

76 3. Analysis and design v C, V e (a) t [µs] i L, i C 1 Figue (b) t [µs] Nomalised wavefoms, (a) esonant link voltage v C (black) and enegy stoage capacito voltage V e (gey), and (b) esonant inducto cuent i L (black) and esonant capacito cuent i C (gey). Enegy stoage inteval Fo the paallel quasi esonant DC link, an enegy stoage inteval efeed to as mode 1, is needed in ode to stoe esonant enegy in the esonant inducto L to ensue that the esonant link voltage do decease down to zeo, duing the amp down inteval. The enegy stoage inteval stats with tun-on of the esonant link tansisto S. The esulting diffeential equation is witten dil Vdc L Ve = (3.143) dt This is eaanged to expess the inducto cuent time deivative, i.e. dil Vdc Ve = (3.144) dt By integating the last expession, the esonant inducto cuent is witten L 68

77 3. Analysis and design Vdc Ve V V i t i t dc e L ( ) = L ( t ) + ( t ) = ( t t ) (3.145) L L The enegy stoage inteval is finished when the inducto cuent eaches the mode 1 tip cuent level, denoted I 1. Hence i ( t )= I (3.146) L 1 1 Thus, the duation of the enegy stoage inteval is equal to L I1 ( t1 t) = V V dc e (3.147) Resonant link voltage amp down inteval The esonant link voltage amp down inteval (mode ), is initiated by tuning off the esonant link seies tansisto S s, focing a dischage of the esonant link capacito C. The system of diffeential equations valid fo this mode is given below. dil vc L Ve = dt dvc ic = C dt i + i + I = L C o1 (3.148) The equation system is ewitten to fom a second ode diffeential equation C d v = dt L C v C L C V e (3.149) The geneal solution to the second ode diffeential equation is witten vc ( t) = Acos ω ( t t1) + Bsin ω ( t t1 ) + Ve (3.15) whee the chaacteistic angula fequency ω is given by ω = 1 (3.151) C L 69

78 3. Analysis and design Accoding to the oiginal system of diffeential equations, (3.148), the esonant link capacito cuent is found fom the time deivative of the voltage. This gives ic ( t) = ωc Asin ω( t t1) + ωc Bcos ω( t t1 ) (3.15) The initial capacito voltage and cuent detemines the constants A and B, accoding to vc ( t1) = A+ Ve = Vdc ic ( t ) = ω C B= I I 1 1 o1 (3.153) The amp down inteval is finished when the esonant link voltage eaches zeo. The coesponding time instant is denoted t. Thus, A necessay condition fo this to occu is vc ( t ) = (3.154) ic ( t ) (3.155) Accoding to the method fo calculating final values given in Appendix C.1, the limiting case is witten ( ) + Ve = Vdc V ω C ( e ) + I 1 + I ω C o1 (3.156) The minimum tip cuent level of mode 1 is thus given by Intoducing a small cuent magin I 1 C = Io1 + L V dc ( V e V dc ) (3.157) which is added to the minimum tip cuent, giving I m1 > (3.158) C I1 = Im1 Io1 + L V dc ( V e V dc ) (3.159) If the tip cuent value calculated above is used, the initial esonant capacito cuent equals 7

79 3. Analysis and design C ic ( t1) max = ω C Bmax = Im1 L V dc ( V e V dc ) (3.16) and the capacito cuent at the stat of the zeo voltage inteval is given by C ic ( t ) max = Im1 + Im1 L V dc ( V e V dc ) (3.161) Note that the tip cuent must be positive. If a negative tip cuent is calculated, zeo is used. The wost case initial esonant capacito cuent thus equals i ( t ) = ω C B = I (3.16) C 1 min min o1,max The maximum dischage cuent, i.e. minimum capacito cuent, at the end of the esonant link voltage amp down inteval thus equals C ic ( t ) min = Io1,max + L V dc ( V e V dc ) (3.163) The inducto cuent at the end of the esonant link voltage amp down inteval is in any case given by i ( t ) = i ( t ) I (3.164) L C o1 Note that by inceasing the cuent magin I m1, moe enegy than necessay is tansfeed to the esonant cicuit. Futhemoe, the enegy stoage capacito voltage V e inceases somewhat, even if its capacitance is high. In Chapte 5 this is used fo contol puposes. Zeo voltage inteval Duing the zeo voltage inteval the esonant link voltage is clamped to zeo, fist by the convete feewheeling diodes and then by the convete tansistos. This implies v C () t = (3.165) which means that the diffeential equation valid fo this mode is given by L dil dt + V e = (3.166) 71

80 3. Analysis and design Though integation, the esonant inducto cuent is found to be Ve il () t = il ( t ) ( t t ) (3.167) L The zeo voltage inteval is finished when the mode 3 tip cuent level is eached, i.e. when i ( t )= I (3.168) L 3 Since the tansistos of the convete ae clamping the esonant link voltage immediately pio to the time instant t 3, this tip cuent has to be negative. Fo a positive esonant link output cuent it is thus given by I = I (3.169) o Howeve, fo a negative esonant link output cuent the tip cuent is selected accoding to I = I (3.17) m In both cases (3.167) gives Ve il ( t3 ) = I = Io1 ic ( t ) 3 L ( t t ) (3.171) The duation of the zeo voltage inteval is thus given by L ( t3 t) = ( I Io1 ic ( t )) (3.17) V e Also in this case the cuent magin, I m, is allowed to vay, in ode to contol the enegy stoage capacito voltage V e. This is possible due to the fact that fo a lage magin, the enegy stoage capacito C e is dischaged to a lage extent than fo small magin. In Chapte 5, whee the quasi esonant DC links ae simulated, the cuent magins discussed hee ae used to contol the voltage V e. If it is to low, the cuent magin of mode 1, I m1, is inceased and if it is to high, the cuent magin of mode 3, I m, is inceased. Resonant link voltage amp up inteval The system of diffeential equations valid fo the esonant link voltage amp up inteval is given below. 7

81 3. Analysis and design dil vc L Ve = dt dvc ic = C dt i + i + I = L C o (3.173) The coesponding second ode diffeential equation becomes C which has the geneal solution d v = dt L C v C L C V e (3.174) vc ( t) = Acos ω ( t t3 ) + Bsin ω ( t t3 ) + Ve (3.175) The coesponding esonant capacito cuent is thus witten ic ( t) = ωc Asin ω( t t3 ) + ωc Bcos ω( t t3 ) (3.176) The initial conditions fo this mode ae calculated fom the final values of the zeo voltage inteval, which also detemines the constants of the geneal solution vc ( t3 ) = A+ Ve = ic ( t ) = ω C B= I I 3 o (3.177) The constant B can also be expessed as L B = C i C ( t 3 ) (3.178) The esonant link voltage inteval is completed when vc ( t4 ) = V (3.179) The esonant capacito cuent must be non-negative at this time instant, i.e. dc ic ( t4 ) (3.18) Application of the method of calculating final values, given in Appendix C.1, gives 73

82 3. Analysis and design i C C t L V V V i ( 4) = dc ( e dc )+ C( t 3 ) (3.181) which shows that the constaint (3.18) is fulfilled as long as V e exceeds.5. Futhemoe, if the tip cuent is selected accoding to (3.169) it is found that i C Resonant enegy ecovey inteval C ( t4 ) min = L V dc ( V e V dc ) (3.18) Duing the esonant enegy ecovey inteval, mode 5, the excess enegy stoed in the esonant inducto L is tansfeed back to the DC link capacito C dc via the esonant link seies diode D s. Futhemoe, this also implies that the esonant link voltage is clamped to the DC link voltage level. Duing the enegy ecovey inteval the esonant link seies tansisto S s is tuned on, to be able suppot the cuent fed to the convete duing the off esonance peiod. The diffeential equation valid fo this mode is thus witten dil Vdc L Ve = (3.183) dt The esonant inducto cuent is deived by integation, giving Vdc Ve V V i t i t dc e L ( ) = L ( t4 ) + ( t4 ) = ( t t4 ) (3.184) L L The excess esonant enegy is fully estoed when i L ( t 5 )= (3.185) which gives that the duation of the esonant enegy ecovey inteval is expessed as L ( t5 t4) = L ( t4 ) = V V i dc e L = o + ( )+ ( 3 ) V V I C L V dc V V i e dc C t dc e (3.186) 74

83 3. Analysis and design Fo this cicuit, eithe the seies tansisto o diode of the esonant link, i.e. S s o D s, is conducting the cuent dawn by the convete duing the off esonance inteval. This also means that the esonant link voltage v C is clamped to the DC link voltage level V dc. Consequently, no oscillations ae obseved duing the off esonance inteval, i.e. in between the esonant cycles. Design expessions Fo the paallel quasi esonant DC link convete investigated hee, only two paamete values ae possible to use as design paametes, L and C. This means that the design constaints on the duation of the zeo voltage inteval and the maximum esonant link voltage deivative togethe detemines the esonant link passive components. The enegy stoage capacito C e is selected in such a way that its voltage vaiation duing one esonant cycle, does not become unacceptably high. The constaint to ensue completion of the esonant cycle is not guaanteed by pope passive component selection, as it was fo the passively clamped esonant cicuits. Instead, this is ensued by pope selection of the mode 1 tip cuent level I 1. Fist, the maximum duation of the zeo voltage inteval, encounteed fo the maximum esonant link output cuent incease, is detemined accoding to (3.17) L ( t3 t) max = o V I I e ( ) + o1 max L C + Im1 + Im1 V L V V V e ( ) dc e dc (3.187) In the expession above, the cuent magin I m is set to zeo, since this is only used fo contol puposes, i.e. the esonant link is able to complete its cycle even if I m is set equal to zeo. The mode 1 cuent magin I m1 is used both fo contol puposes and to ensue that zeo esonant link voltage is eached. Theefoe, I m1 is included in the expession above. The voltage deivative is analysed both fo the esonant link voltage amp down (mode ) and amp up (mode 4) intevals. Fo mode, the minimum value of the constant B is given by 75

84 3. Analysis and design B min L = C I o1,max (3.188) esulting in a maximum voltage deivative fo this mode accoding to dv dt C max A B ω A B = ω V V max o1,max ( dc e ) + ω C I min = ω +( ) = + = (3.189) Fo mode 4, the maximum value of the constant B in the geneal solution of the coesponding diffeential equation, is given by B L = C I I ( ) (3.19) max m o,min The maximum voltage deivative fo this mode thus equals dv dt C max = ω A + B = I = ω Ve + max m I ω C o,min (3.191) If it is assumed that the minimum value of the esonant link output cuent i o, equals the maximum with opposite sign, i.e. I o,min = I (3.19) o1,max it is found that the esonant link maximum voltage deivative is obtained fo the esonant link voltage amp up inteval, i.e. mode 4, since V = 6. V > V V = 4. V (3.193) e dc dc e dc In [41], a contol expession egading selection of the mode 1 tip cuent level, is pesented. This expession is also deived hee (3.159), by use of the method fo calculating final values, given in Appendix C.1. Unfotunately, the deivation of the expession fo selection of the esonant link voltage amp down tip cuent level is not pat of [41]. 76

85 3. Analysis and design 3.4 The actively clamped quasi esonant cicuit The actively clamped quasi esonant DC link convete is pesented in [55]. In Figue 3.7 this esonant link is shown togethe with a simplified convete equivalent, consisting of an ideal cuent souce and a tansisto and a diode connected acoss the esonant link. The tansisto and diode ae needed fo the analysis of the cicuit, since the esonant link inducto cuent i L flows though these components duing the zeo voltage inteval. In fact, the zeo voltage inteval is inhibited by setting the tansisto switch state accoding to the modulato command. Pio to this, the esonant link is shoted by keeping all the convete tansistos on, which was also the case fo the peviously investigated paallel quasi esonant DC link convete. L i L S D i o V dc C dc S c V Cc D c C C c i C v link i o I o I o1 t 3 t Figue 3.7 The simplified actively clamped quasi esonant DC link convete, whee the convete is epesented as an ideal cuent souce and an equivalent tansisto-diode combination connected acoss the esonant link. To the ight, a esonant link output cuent step is shown. Thoughout the entie analysis, the clamping voltage V Cc is consideed being constant, i.e. V Cc = KV (3.194) dc Hee, K denotes the clamping facto. Note that in the simulations, see Chapte 5, the clamping voltage has to be contolled. In Figue 3.8, nomalised wavefoms of the basic quantities fo this cicuit ae shown fo the case with a clamping facto equal to 1.. The DC link voltage V dc is the voltage nomalisation base value and the maximum output cuent change designed to meet, is the cuent base value. 77

86 3. Analysis and design v link, V Cc (a) t [µs] i L, i C t [µs] (b) Figue 3.8 Nomalised (a) esonant link voltage v link (black) and clamping voltage V Cc (gey), and (b) esonant inducto cuent i L (black) and esonant capacito cuent i C (gey). Note the oscillations at the end of the esonant cycle, see Figue 3.8. In [55], almost no mathematical deivations ae pesented. Consequently, no design expessions ae given. Hee, mathematical deivations fo the esonant link opeation of each mode is pesented togethe with the design expessions selected. Enegy stoage inteval Fo the actively clamped quasi esonant DC link, a esonant tansition is stated by tuning on both the esonant link tansistos, S and S c, causing the esonant link voltage v link to equal the clamping voltage V Cc. The diffeential equation valid fo this mode is thus witten dil Vdc L VCc = (3.195) dt Consequently, the esonant inducto cuent deivative is expessed as 78

87 3. Analysis and design di dt L V V ( K 1) V = = L L dc Cc dc (3.196) Integation gives ( K 1) Vdc ( K 1) Vdc il ( t) = il ( t ) ( t t) = Io1 ( t t ) L L (3.197) The enegy stoage inteval (mode 1) is finished when i ( t )= I (3.198) S 1 1 whee I 1 is the mode 1 tip cuent level. The esonant inducto cuent at this time instant is i ( t ) = I i ( t ) = I I (3.199) L 1 o1 S 1 o1 1 Substitution into (3.197) gives i ( K 1) Vdc ( t ) = I ( t t ) = I i ( t ) = I I L L 1 o1 1 o1 S 1 o1 1 (3.) Hence, the duation of the enegy stoage inteval is given by L I ( t1 t) = ( K 1) 1 V dc (3.1) When the tip cuent level is eached, the esonant link tansisto S c is tuned off, causing dischage of the esonant link capacito C. Hee it is impotant that C c is much lage than C, by means of capacitance. Othewise, the clamping voltage can not be egaded as constant. Resonant link voltage amp down inteval As soon as S c is tuned off the esonant link voltage will stat to decease, since a esonant inducto cuent is built up duing the enegy stoage inteval. Howeve, fo the esonant link voltage to each zeo, it is vey impotant that the tip cuent level I 1 is high enough. In this section an appopiate value fo the tip cuent is deived. The system of diffeential equations valid fo the esonant link voltage amp down inteval (mode ) is given below 79

88 3. Analysis and design dil Vdc L vc = dt dvc ic = C dt i i I = L C o1 (3.) Substituting the diffeential equations of the system above gives a second ode diffeential equation C d v = dt L C v C L C V dc (3.3) The geneal solution to the second ode diffeential equation is vc ( t) = Acos ω ( t t1) + Bsin ω ( t t1 ) + V (3.4) whee the chaacteistic angula fequency ω is expessed as dc ω = 1 (3.5) C L The esonant capacito cuent becomes ic ( t) = ωc Asin ω( t t1) + ωc Bcos ω( t t1 ) (3.6) The constants A and B of the geneal solution ae given by the initial capacito voltage and cuent, espectively vc ( t1) = A+ Vdc = VCc = KVdc ic ( t ) = ω C B= i ( t ) I = I 1 L 1 o1 1 (3.7) Mode is finished when zeo esonant link voltage ae obtained, i.e. when vc ( t ) = (3.8) A necessay condition fo this to be met is ic ( t ) (3.9) Applying the method fo calculating final values, see Appendix C.1, gives 8

89 3. Analysis and design ( ) + 1 Vdc = ( K ) V ω C ( dc ) + I 1,min ω C (3.1) By solving the second ode algebaic equation it is found that the minimum tip cuent is witten I 1,min = V dc C ( L K( K) ) (3.11) By adding a small cuent magin I m1 > (3.1) the tip cuent is given by C I1 = Im1 + I1,min = Im1 + Vdc ( L K ( K )) (3.13) The initial capacito cuent, used fo detemining the constant B of the geneal solution, thus becomes equal to C ic ( t1) = ω C B= Im1 Vdc ( L K ( K )) (3.14) Applying the method fo calculating final values gives C ic ( t) = Im1 + Im1Vdc L K ( K ) (3.15) In the last expession, it is clealy seen that fo a cuent magin I m1 equal to zeo, the esonant link voltage eaches zeo at zeo capacito cuent. Zeo voltage inteval Duing the zeo voltage inteval, mode 3, the esonant link voltage is clamped by the convete semiconductos. Also fo this cicuit, the zeo voltage inteval is inhibited by tuning off one tansisto of each convete half bidge. Howeve, fo the actively clamped quasi esonant DC link, the duation of the zeo voltage inteval can equal zeo. This occus if the output cuent to be set has a lowe magnitude than the inducto cuent i L when the zeo voltage inteval is enteed. The diffeential equation valid fo the zeo voltage inteval is witten 81

90 3. Analysis and design Integation gives V dc dil L = (3.16) dt Vdc il () t = il ( t ) + ( t t ) (3.17) L Thus, the duation of the zeo voltage inteval is expessed as L ( t3 t) = ( il ( t3) il ( t) ) (3.18) V dc The inducto cuents inseted in the expession above ae given by and C il ( t) = Io1 Im1 + Im1Vdc L K ( K ) (3.19) i ( t )= I (3.) L 3 Ideally, the second tip cuent level is detemined by I = Im + Io (3.1) Howeve, if the desied tip cuent level is lowe than the inducto cuent at the end of the esonant link voltage amp down inteval, accoding to the expessions above, i.e. if C Im + Io Io1 Im1 + Im1Vdc L K ( K ) (3.) the duation of the zeo voltage inteval equals zeo. In this case the tip cuent is expessed as C I = il ( t3 ) = il ( t) = Io1 Im1 + Im1Vdc L K ( K ) (3.3) In any case, the duation of the zeo voltage inteval is given by L C ( t3 t) = I Io1 + Im1 + Im1Vdc ( ) V L K K (3.4) dc 8

91 3. Analysis and design Fo the case when the tip cuent is detemined by (3.1), the duation of the zeo voltage inteval is ewitten as L L C ( t3 t) = ( Io Io1)+ Im1 + Im1Vdc ( ) + V V L K K dc L + V dc I m dc (3.5) Actually this is used to calculate the time needed to polong the zeo voltage inteval in ode to incease the clamp voltage V Cc. This is achieved by allowing the magin I m to vay, and to calculate the coesponding additional time the zeo voltage should be maintained by shot cicuiting each half bidge of the convete. The additional time is given by the last tem of the pevious expession, i.e. L ( t3 t) boost = m V I (3.6) When simulating this cicuit, this is used to contol the clamp capacito voltage V Cc. If the clamp voltage is to low, the zeo voltage inteval is polonged esulting in stoage of excess enegy in the inducto L. This excess enegy is tansfeed to the clamp capacito C c afte the esonant link voltage amp up inteval. Resonant link voltage amp up inteval The esonant link voltage amp up inteval, mode 4, stats as soon as the new switch state is applied, which foces a pat of the esonant inducto cuent i L to flow though the esonant link capacito C, wheeby its voltage stats to incease. Mathematically this mode is expessed by dc dil Vdc L vc = dt dvc ic = C dt i i I = L C o (3.7) Fom the system of diffeential equations, one second ode diffeential equation is fomed 83

92 3. Analysis and design C d v = dt L C v C L C V dc (3.8) The geneal solution is also in this case witten vc ( t) = Acos ω ( t t3) + Bsin ω ( t t3 ) + V (3.9) Consequently, the esonant capacito cuent is witten ic ( t) = ωc Asin ω( t t3 ) + ωc Bcos ω( t t3 ) (3.3) The initial conditions detemine the constants A and B of the geneal solution dc vc ( t3 ) = A+ Vdc = ic ( t ) = ω C B= il ( t ) I = I I 3 3 o o (3.31) Note that the initial esonant capacito cuent is dependent on the tip cuent. Mode 4 ends as soon as A necessay condition fo this to occu is vc ( t4 ) = KV (3.3) dc ic ( t4 ) (3.33) By applying the method fo calculating final values, see Appendix C, the capacito cuent at the end of mode 4 is expessed as i ( t ) = ω C C 4 ic ( t3 ) + Vdc 1 ( K 1) ω C C ic t L V = ( 3 ) + dc K ( K ) ( ) = (3.34) The last expession shows that this esonant link is always capable of etuning fom zeo voltage since thee is always excess enegy stoed in the esonant inducto L. This excess enegy is tansfeed to the clamp capacito C c, theeby chaging it. Consequently, its capacitance has to be high enough to pevent the voltage fom inceasing to much. 84

93 3. Analysis and design Clamping inteval Duing the clamping inteval, mode 5, the esonant cicuit ecoves. The diffeential equation fo this mode is witten dil Vdc L VCc = (3.35) dt The solution to the diffeential equation is found by integation, which gives ( K 1) Vdc il () t = il ( t4 ) ( t t4 ) L The initial inducto cuent is detemined accoding to (3.36) i ( t ) = i ( t ) + I (3.37) L 4 C 4 o The final inducto cuent, equals the esonant link output cuent, i.e. i ( t )= I (3.38) L 5 o The duation of the clamping inteval is thus expessed by L L ( t5 t4) = ( il ( t4 ) Io )= C ( t4 ) ( K 1) V ( K 1) V i dc dc (3.39) When the clamping inteval is finished, the esonant link voltage etuns to V dc. Note that the slope the voltage etuns with, see Figue 3.8, is not detemined by the esonant link passive components, but by its semiconductos. Design expessions Also this cicuit has only two passive component values to be selected. Consequently, only two design constaints can be met. The constaints ae, as fo the othe cicuits, the duation of the zeo voltage inteval and the maximum esonant link deivative. Note that this is not eally tue fo this cicuit since the maximum esonant link voltage deivative is not detemined by the passive components, as discussed above. Fist, the maximum duation of the zeo voltage inteval is detemined fom (3.5) 85

94 3. Analysis and design L ( t3 t) max = Io I V ( o1) + max m + V I dc dc L C + Im1 + Im1Vdc ( ) V L K K dc L (3.4) The maximum esonant link voltage deivative, obtained fo mode, appeas fo the minimum value of the constant B, i.e. when which gives 1 C B = I + Vdc ( C L K ( K m1 )) (3.41) ω dv dt C = ω A + B = I I Vdc = Vdc + K K m1 C + m1 ω ( C ) ω ω (3.4) Fo mode 4 instead, the maximum esonant link voltage deivative appeas when the constant B is at its maximum, i.e. ( ) = i ( t ) = ω C B = i ( t ) I C 3 max max L 3 o max C = ( Io1 Io ) I I V max m1 + dc L K ( K ) I I ( ) m1 o1 o max (3.43) esulting in dv dt C max ( ) L = ω A + Bmax ω Vdc + I I C ( o1 o ) max (3.44) Fo pope selection of the passive component values both these deivatives have to be consideed. 86

95 4 Devices fo esonant convetes Powe semiconducto data sheet infomation is not valid fo soft switching conditions. In ode to intepet the simulated esults in Chapte 5, some basic knowledge on powe semiconductos is given and phenomena elated to soft switching is discussed. The discussion is limited to diodes and insulated gate bipola tansistos since these ae the only semiconducto devices used in the simulations. In the liteatue, moe in dept discussions on powe electonic semiconducto devices ae found, fo example [5], [44], [63]. Geneal semiconducto physics is intoduced in [6], [61]. Also, passive components like inductos and capacitos ae to some extent discussed in this section. The discussion on passive components ends up with a pesentation of the loss models used fo these devices. In the liteatue, [4], [44], [6], [63], thoough pesentations on passive components and thei design ae found. 4.1 Powe diodes Powe diodes ae usually sepaated into two categoies, ectifie and switching diodes. The doping stuctues fo both categoies consist of the same layes, at least fo the voltage levels discussed hee. Howeve, they behave diffeent fom each othe, due to the fact that the length of the layes (in the diection of the cuent) and thei doping densities ae not the same. Theefoe, the discussion is applied to powe diodes in geneal, and then the diffeences between ectifie and switching diodes ae explained. Basic doping stuctue The doping stuctue fo a powe diode diffe, to some extent, fom that of a low powe and low voltage diode. The main diffeence oiginates fom the fact that the powe diode has to sustain high evese voltages, implying that the doping stuctue has to withstand a high electic field, without failue. Fo this eason, all powe electonic semiconducto devices ae equipped with a long (in the diection of the electic field)

96 4. Devices doping laye with low doping density. This doping laye, not found in low voltage and low powe devices, is often temed dift laye. In Figue 4.1, the pincipal doping stuctue of a powe diode is shown. Note that fo eal devices, the dift laye is consideably thicke than the othe. Howeve, in Figue 4.1, the thickness of the othe layes ae exaggeated fo visibility. i D p+ Anode n- n+ dift egion substate Cathode Figue 4.1 Pincipal powe diode doping stuctue. Fom the low powe countepat, the highly doped anode and cathode layes ae ecognised. The idea of having one thick laye of low doping density, is that the depletion egion fomed in the blocking state should mainly be located to this laye. The low doping esults in a low peak electic field, and the lage thickness means that the entie depletion egion is held inside the dift laye, i.e. it does not extend into the cathode laye. Howeve, fo so called punch though (PT) o buffe laye devices a geometically shot but highly doped buffe laye is located in between the dift and cathode layes. In this case, the idea is the same but the dift egion has in this case an even lowe doping density. Also, the dift egion is allowed to extend acoss the entie dift egion to each the buffe laye. The esult of this manipulation is that the dift egion can be less thick. Accoding to [44], the thickness can be appoximately halved compaed to the non punch though (NPT) case. The diode is called a natual PT device since no additional dawbacks aises fo the PT compaed to the NPT device. Also, the highly doped substate seves as buffe laye fo PT-diodes. Fo othe types of devices, buffe laye devices ae often efeed to as asymmetical. The eason is that the PT device can not block voltage of the opposite polaity, since none of the junctions sustain the high electic field stength esulting fom the high doping densities on both sides of the blocking junction. Fo the diode, no fowad blocking capability is povided, implying that this does not matte in this case. 88

97 4. Devices Steady state opeation When a powe diode is fowad biased, heavy injection of minoity caies into the low doped dift egion occus. In fact, the density of fee caies can become odes of magnitude highe than depicted by the doping atom density. Consequently, the esistivity of the dift egion becomes consideably lowe than expected fom the doping density. This phenomena is often efeed to as conductivity modulation. Due to conductivity modulation, the fowad voltage dop thus becomes athe low. Fo conductivity modulation to be established, it is of couse impotant that the diffusion length in the dift egion is not too shot compaed to the thickness (in the diection of the minoity caie movement) of the dift egion. Othewise, ecombination effects will cause a low minoity caie density in the bulk of the dift egion. When the diode is evese biased, the anode-dift junction suppots the voltage, i.e. a depletion egion is fomed at the junction. The depletion egion extends mostly into the low doped dift egion, see [44]. In this case a low doping atom density of the dift egion is advantageous since the peak electic field stength is educed. Howeve, the depletion egion also expands, implying that the dift egion must be thick if it is desied that the depletion egion must not extend acoss the entie dift egion. Howeve, since the diode is a natual PT device, the high doping of the cathode laye effectively pevents the depletion egion fom eaching the cathode contact. Switching When a semiconducto device taveses fom the conduction state to the blocking, o vice vesa, is temed a switching. Fo a powe diode, seveal phenomena not seen fo the low powe countepat appeas. In Figue 4., typical tun-on and tun-off wavefoms ae shown fo a feewheeling diode in a bidge application. The diode voltage v D shown in Figue 4., is the voltage between the anode and cathode of the diode, i.e. v D =v AC. At tun-on, the diode evese voltage fist declines to zeo. Then, the ectifying junction becomes fowad biased. Consequently, the diode cuent stats to incease. The diode cuent ate of change, i.e. the diode cuent time deivative, is detemined by the tansisto tuning off. If the cuent ate of change is extemely high, a diode fowad voltage peak is obseved [44], depending on the fact that excess caies ae not 89

98 4. Devices injected into the dift egion at the coesponding ate. Hence, a conductivity modulation lag is obseved. This esults in a highe fowad voltage dop than expected fom the data sheets, due to the highe esistivity of the dift egion. To some extent, the voltage peak obseved is also due to stay inductance of the bonding wies of the diode housing. As seen in Figue 4., a tun-on voltage peak do not show up hee. When the diode cuent has eached the level detemined by the load, the diode voltage etuns fom its peak level, to eventually each its steady state. The phenomena whee the fowad voltage dop becomes consideably highe than what is expected fom the data sheets is temed fowad ecovey. The steady state fowad voltage dop is detemined both by the height of the junction potential baie and the esistivity of the doping layes, mainly the dift egion. v D id 1 v D id t [µs] 1 t [µs] Figue 4. (a) The feewheeling diode cuent i D (black) and fowad voltage v D (gey) duing (a) tun-on, and (b) tun-off. Note that the coesponding tansisto, an IGBT in this case, is non-ideal, i.e. it affects the diode switching wavefoms. (b) A feewheeling diode tuns off when the complementay tansisto is tuned on. Fist, the diode cuent stats to decease at a ate detemined by the powe tansisto. On the contay to what is obseved fo the low powe countepat, the powe diode tun-off cuent continues to decease to become negative. This is due to the fact that the excess caies stoed in the dift egion fowad biases the anode-dift junction. 9

99 4. Devices As soon as these excess caies ae swept out, the anode-dift junction can suppot the blocking voltage. Thus, the diode voltage becomes negative and the diode cuent decease is inhibited. Now, the diode cuent stats to incease towads zeo. The diode cuent in this pat emoves the fee caies in the anode and dift layes to ceate a depletion egion. Also, at tun-off a negative voltage peak is obseved. The voltage peak in this case is due to the stay inductance of the entie powe electonic cicuit. Note that the powe diode evese blocking voltage must be selected to sustain this peak level. The phenomena in which the diode cuent becomes negative is temed evese ecovey. The main diffeence between feewheeling and ectifie diodes is that conductivity modulation is moe ponounced fo the latte, i.e. a lage amount of chage is stoed in the dift egion when a ectifie diode is conducting compaed with a feewheeling diode. This implies that the ectifie diode will have a lowe fowad voltage dop, due to its lowe on-state esistance. Howeve, the switching tansients will have a longe duation due to the lage amount of chage stoed. This implies that the ectifie diode is moe sensitive to high diode cuent deivatives. Both the fowad ecovey voltage peak and the evese ecovey cuent peak will thus be highe fo a ectifie diode compaed to a feewheeling diode of the same ating fo a given diode cuent time deivative. 4. IGBTs The IGBT [5], [44], [48], [63], was intoduced to be a compomise between the bipola junction tansisto (BJT) and the metal oxide semiconducto field effect tansisto (MOSFET). Howeve, the IGBT has become moe than just a compomise, due to its high uggedness, modeate voltage dop and faily high switching speed. Actually, in many moden designs it is the only easonable device choice. The main easons fo its populaity is the high blocking voltage, up to 6 kv, its modeate diving equiements and its limited need fo potective devices, i.e. snubbes. Basic doping stuctue The IGBT is a thee teminal semiconducto device. The teminal named emitte is common to both input and output. The device is contolled by applying a voltage between the gate and emitte teminals. The output cuent flows between the collecto and emitte teminals. The gateemitte egion is split into thousands of cells. In Figue 4.3, one such cell of a NPT-IGBT and also one of a PT-IGBT ae shown. The only 91

100 4. Devices stuctual diffeence between these two, is that the PT device has an additional doping laye, temed buffe. The desciption pesented hee, focuses on the NPT device. The most commonly used n-channel IGBT cicuit symbol is used thoughout the entie text and is theefoe not shown hee. Othe cicuit symbols fo the IGBT do exist, but this is the most fequently used. The eason fo dividing the gate-emitte stuctue into cells, is to keep the channel esistance low by inceasing its coss-sectional aea and deceasing its length. Futhe on, the emitte metallisation extends ove the body egion, which is done to shot cicuit the body-emitte junction. This is used to educe the isk of enteing latchup, a fault condition discussed late on. Emitte Gate Emitte Gate n+ p p body n+ body n+ p p body n+ body n- dift egion p+ injection laye n- dift egion n+ buffe laye p+ injection laye Collecto Collecto Figue 4.3 (a) Pincipal doping stuctue fo (a) the NPT-IGBT, and (b) the PT-IGBT. (b) Steady state opeation Fom Figue 4.3 it is seen that the doping stuctue of an IGBT looks simila to the one of a MOSFET. Fo the NPT device the only diffeence is the pesence of a heavily doped injection laye at the IGBT collecto metallisation. The eason fo having this laye, is that holes should be injected into the dift egion to obtain conductivity modulation when the device opeates in the conduction state. The lack of conductivity modulation is the main dawback of the MOSFET, being a majoity caie device. In the on state, simila to the MOSFET, a channel is ceated in the body egion undeneath the gate oxide, connecting the n-doped emitte and 9

101 4. Devices dift egions. The channel suppots an electon cuent, flowing fom the emitte into the dift egion. The negative chage of the electons, attacts holes fom the injection laye, which in tun causes conductivity modulation of the dift egion. When the IGBT opeates in the fowad blocking state, the dift egion suppots the voltage. Simila to the powe diode case, a depletion egion is fomed in the dift egion. Fo a NPT device, this is also tue fo the evese blocking state, i.e. when the IGBT is blocking a collecto-emitte voltage of evese polaity. Howeve, the PT-IGBT can not block a collecto-emitte voltage of negative polaity, since the injection-buffe junction should suppot the voltage in this case. Both these egions ae highly doped, esulting in a high electic field stength even at low blocking voltages. Consequently, avalanche beakdown will occu fo low evese blocking voltage. This is the eason why the PT-IGBT is often temed asymmetic. In Figue 4.4 the cuent-voltage chaacteistics of a typical IGBT is shown. The output chaacteistic of an IGBT shows the collecto cuent, i C, as a function of the collecto-emitte voltage v CE, fo diffeent gateemitte voltages v GE. i C i C C GC v CE (a) (b) (c) Figue 4.4 Output chaacteistic fo low collecto-emitte voltages (a), tansfe chaacteistic (b), and gate-collecto capacitance as a function on the collecto-emitte voltage (c). The tansfe chaacteistic shows the collecto cuent as a function of the gate-emitte voltage, when the IGBT is in the active egion. The tansfe chaacteistic is thus mainly inteesting fo the switching tansients, since othewise the device should opeate in the on-state o off-state egions. v GE v CE 93

102 4. Devices Switching at inductively clamped load Figue. shows typical switching wavefoms fo an IGBT opeating at inductively clamped load in a bidge application. The coesponding feewheeling diode is egaded as being ideal. At tun-on of the IGBT, the gate-emitte voltage v GE must fist each its theshold level, v GE(th), befoe the collecto cuent i C stats to incease. The time needed to do this is temed the tun-on delay time t d(on). The gate-emitte theshold voltage is seen in the tansfe chaacteistic of Figue 4.4 as a shap bend whee the collecto cuent becomes non-zeo. Note that since the IGBT has a capacitive input, the gate esisto detemines the delay time. Also note that the intenal capacitance is vaying due to depletion laye thickness, i.e. collecto-emitte voltage. The gate-collecto capacitance is the most affected. Its typical dependence on collecto-emitte voltage is shown in Figue 4.4, whee the faily shap knee appoximately coesponds to a collecto-emitte voltage equal to the applied gate-emitte voltage. Afte the tun-on delay time, the gate-emitte voltage continues to incease and the collecto cuent stats to incease. The collecto cuent time deivative is detemined by the tansfe chaacteistics, see Figue 4.4, which implies that it is detemined by the size of the gate esisto. The duation of this cuent ise inteval is temed cuent ise time t i. Following the cuent ise inteval, the voltage fall inteval commences. The duation of this inteval is temed voltage fall time t fv. The voltage fall inteval can be subdivided into two potions. The fist pat is simila to the voltage fall of a MOSFET, i.e. the Mille plateau. The second pat has consideably lowe fall ate mainly due to conductivity modulation lag. IGBT tun-off also stats with a delay time, t d(off), due to the fact that the gate-emitte voltage has to decease to the level detemined by the tansfe chaacteistic befoe the collecto-emitte voltage stats to incease. Duing the voltage ise time t v the collecto-emitte voltage inceases and the gate-emitte voltage is constant due to the Mille effect. When the collecto-emitte voltage has eached the level of the DC link voltage, the feewheeling diode becomes fowad biased. Hence, the IGBT collecto cuent stats to decease. The collecto cuent fall ate is also detemined by the gate-emitte voltage though the tansfe chaacteistic, i.e. the fall ate is essentially detemined by the gate esisto value. When 94

103 4. Devices the gate-emitte voltage has deceased to its theshold level v GE(th), the channel in the body egion is emoved, coesponding to that the MOSFET pat of the IGBT is tuned off. In IGBT data sheets this pat of the collecto cuent fall is temed t fi. Howeve, thee ae still excess caies stoed in the IGBT dift egion. Since the channel is not pesent, these caies can not be emoved though the channel. Instead, thee will be a long collecto cuent tail whee the cuent falls at a vey low ate. This low ate is due to the fact that the excess caies ae emoved by intenal ecombination, which is a vey slow pocess [44]. Note that the cuent tail fall ate is not affected by the gate esisto value. Howeve, the gate esisto value has some influence since the initial magnitude of the cuent tail is dependent on the amount of excess caies emoved fom the dift egion duing t fi [5]. Fo a low gate esisto value, t fi will be shot and hence the density of excess caies is almost unalteed duing t fi. Fo a high gate esisto value on the othe hand, a lage amount of the excess caies ae emoved duing the compaably long t fi. Thus, the initial magnitude of the collecto cuent tail will be lowe in the second case. Latchup The doping stuctue of the IGBT contains a paasitic thyisto (pnpn) stuctue, see Figue 4.3. The injection laye and the emitte egion foms the anode and cathode, espectively, of the paasitic thyisto stuctue. The body egion foms the gate (p-base) and the dift egion the n-base of this stuctue. The paasitic thyisto stuctue must not be tiggeed, a state temed latchup, since the thyisto can not be tuned off unless its anode cuent is foced to zeo by suounding cicuit elements. Though not obvious, the thyisto stuctue can be tigged by a lateal cuent, fowad biasing the body-emitte junction. The lateal cuent flow aises fom a pat of the hole cuent, injected fom the collecto, fist being attacted by the negative chage of the channel. When the holes entes the body egion, electons fom the emitte metallisation coveing the body ae attacted, which the injected holes ecombine with. Hence, a lateal cuent flow in the body egion esults. If the esistivity of the body is high enough, the lateal cuent can fowad bias the body-emitte junction. Note that even though the emitte metallisation also coves the body, i.e. shot cicuits the emitte and body egions, the body-emitte junction can be fowad biased in the inteio of the stuctue. 95

104 4. Devices Actually, latchup is distinguished into two diffeent cases, static which occus in the on-state and dynamic which occus duing tun-off. Static latchup is due to a too high collecto cuent, esulting in a lateal voltage dop fowad biasing the body-emitte junction. Hence, static latchup is avoided by not allowing a highe collecto cuent than specified by the manufactue. Dynamic latchup occus at tun-off, afte the channel has been emoved. Since the collecto-emitte voltage aleady is at the blocking level, see Figue., the depletion egion is being established in the dift egion. As a consequence, the emitte efficiency fo the emaining pnp-stuctue inceases, since the effective base length deceases. The effective base length is the potion of the dift egion emaining undepleted. The emitte efficiency inceases due to the fact that the possibility of ecombination deceases if the base length is shot. The poblem is that an inceased emitte efficiency esults in the fact that a lage pat of the total cuent is collecto cuent of the pnp-stuctue, which also is the lateal cuent in this case. Hence, if a gate esisto of low esistance is used, the lateal cuent might incease when the channel is emoved, compaed to the on-state case. Then, dynamic latchup will occu fo a lowe IGBT collecto cuent than static would. Theefoe, it is also impotant not to use a gate esisto value lowe than specified by the manufactue. Switching unde zeo voltage conditions One of the main poblems elated with soft switching appeas due to poo undestanding of powe semiconducto physics, since it is assumed that data sheet infomation is still valid at soft switching. Howeve, data sheet infomation fo IGBTs is in most cases given fo inductively clamped load, i.e. constant load cuent duing the switching tansients [34]. Also, the infomation is only valid fo a cetain constant DC link voltage. In the liteatue [34], [43], [5], a lot of poblems appeaing due to soft switching ae discussed. One of the most discussed phenomena obseved, is the cuent tail bump occuing at IGBT zeo voltage tun-off. In Figue.9, the cuent tail bump is clealy seen. Accoding to [5] the eason fo this bump is that duing ZVS tun-off the excess caies stoed in the dift egion ae not foced out by the expanding depletion egion as fo had switched tunoff. Consequently, afte the channel is emoved the collecto cuent continues its decease and no cuent tail is obseved until the IGBT 96

105 4. Devices collecto-emitte voltage begins to incease. The cuent tail bump esults in highe losses at ZVS tun-off than expected fom data sheet infomation. Nevetheless, the tun-off losses ae lowe fo ZVS than fo had switching [34]. Anothe poblem obseved, is due to the conductivity modulation lag [34], [43], appeaing fo high collecto cuent time deivatives. Fo an IGBT, the oigin of this lag is the same as fo the powe diode discussed ealie. This means that the collecto cuent inceases at a ate highe than the ate which excess caies ae injected into the dift egion, needed to establish conductivity modulation. In [34] poblems aising fom device packaging ae also discussed. Hee, the poblem is that bonding wie inductance not only gives an inceased fowad voltage dop but also can esult in uneven cuent distibution among seveal IGBT chips packaged in the same module, at high cuent time deivatives. Uneven cuent distibution leads to inceased losses and also inceased device stess. The soft switching poblems discussed above ae investigated in the simulations pesented in Chapte 5, whee at least the cuent tail bump is clealy seen. 4.3 Inductive elements A esonant convete has at least one inductive element being a pat of the oscillatoy cicuit. Moeove, a VSC also has a cuent stiff output filte, i.e. the output filte must contain inductive elements connected to the convete output teminals. To be able to calculate the oveall efficiency fom simulations, inducto models ae needed. The simulation models used and methods to detemine thei paametes ae discussed. Magnetic mateials Inductive elements consist of one o seveal coppe wie windings which in most cases ae wound upon an ion coe. In this section the diffeent coe mateials used in most cases ae discussed. Coe mateials and inducto design ae thooughly discussed in fo example [4], [44], [6], [63]. Magnetic components fo powe electonic applications, such as inductos and tansfomes, ae often designed only fo the intended application, due to the fact that it is impossible to maintain a stoage of the wide 97

106 4. Devices vaiety of components needed. This means that fo most powe electonic applications, inducto design is a natual pat of the development, since almost evey powe electonic cicuit contains this kind of components. Selection of appopiate coe mateial is an impotant issue in magnetic component design. The mateial choice is to a lage extent detemined by the fequency specta of the magnetising cuent. The fequency specta of inteest fo powe electonics, ange fom 5 Hz (thyisto bidge commutation inductos) to seveal MHz (pulse tansfomes in fo example tansisto dive cicuity). Thee ae mainly thee types of coe mateials used to cove this fequency specta. Fo the low fequency egion (5 Hz to some tens of khz), alloys of ion and fo example chome, silicon o cobalt ae used. These alloys ae chaacteised by high electic conductivity and high satuation flux density (up to 1.8 T). The high conductivity make this mateial subject to eddy cuent losses, i.e. the applied magnetic flux easily induces cuent in the coe. The induced cuents esults in esistive losses, efeed to as eddy cuent losses. To patly ovecome this poblem these coes ae laminated, o in some cases manufactued as steel tape, to decease the length of the cuent paths and the magnitude of the cuents induced. Fo the mid fequency egion (1 khz to 1 khz), coes made fom powde of the same mixtues as in the pevious case, ae used. The ion powde paticles ae coveed with an insulating laye, and foced togethe with pessue. Since the powde paticles ae electically insulated fom each othe, the conductivity and thus the eddy cuent losses of the coe become low. Howeve, anothe loss component efeed to as hysteesis loss, becomes moe significant compaed to the case fo the peviously discussed laminated coes. In the uppe fequency egion (3 khz to 1 MHz), soft feite coes ae commonly used. Feites ae ceamic compounds, consisting of ion oxide togethe with usually zinc o nickel. Othe compound mateials ae also used, and also mixtues of seveal compound mateials ae possible. The cystals of the feite ae typically 1 µm in dimension, thus limiting the eddy cuent path length and the magnitude of the cuent induced. Feites, like othe magnetic mateials have losses associated with the hysteesis of the B-H loop. Hysteesis occus due to fiction associated with magnetic domain wall movement and magnetic domain otation when an extenal magnetic field H is applied, causing the change in magnetic flux density to lag the change in magnetic field. This lag is known as hysteesis. Fo an AC magnetic field, a loop is fomed in the B-H plane, 98

107 4. Devices foming the hysteesis cuve. The aea enclosed by such a loop coesponds to the hysteesis loss. In most cases the manufactue specifies the coe losses as cuves showing the loss pe volume o mass unit, depending on the flux density and the fequency. In some cases, empiically deived expessions ae given instead of cuves. Thee ae howeve also analytically deived loss models like the Steinmetz fomula [44] whee the specific losses ae given by a1 a p = k f Bˆ + k f Bˆ Fe h ac ec ac (4.1) whee a 1, a, k h, and k ec ae mateial dependent constants. The fist tem of the Steinmetz fomula above, is due to hysteesis losses and the second tem due to eddy cuent losses. Note that the AC peak magnetic flux density is needed to calculate the ion losses. Seveal othe foms of Steinmetz fomula ae often used. Fo example, the hysteesis loop is tavelled once each peiod, implying that a 1 =1. Also, if the hysteesis loop is appoximated as being ectangula, a = can be assumed. Fo the magnetic coe mateials used in the simulations of Chapte 5, the manufactue [67] gives the specific ion losses accoding to the empiical elationship p Fe f = a b c + + Bˆ Bˆ. Bˆ ac ac ac + ( df Bˆ ac ) (4.) whee a, b, c and d ae mateial dependent constants. Specific ion losses in this case means that the losses ae given in the unit mw/cm 3. Simulation models To be able to simulate the battey chages with quasi esonant DC links, models of the magnetic components ae needed. To estimate the efficiency, the losses of these components have to be included. This is due to the fact that these losses must be compensated fo, to maintain the output powe. This means that the losses in othe pats of the cicuit may incease, since the input powe becomes highe. In Figue 4.5, simulation models fo an inducto and a thee winding tansfome ae shown. The two winding tansfome model used is simila to the thee winding countepat with the tetiay winding emoved. 99

108 4. Devices i L R Cu i L1 R Cu1 k 1 L R Cu i L v RFe R Fe L v RFe R Fe L 1 k 13 k 3 L 3RCu3 i L3 Figue 4.5 (a) Simulation models fo (a) an inducto, and (b) a thee winding tansfome. (b) In Figue 4.5, esistos ae included in the magnetic component equivalents to model powe dissipation. The esistos named R Cu ae used to model the coppe winding losses. Consequently, fo the thee winding tansfome thee is one such esisto fo each winding. Note that the coppe winding esistance is tempeatue dependent, implying that the opeating winding tempeatue has to be assumed. The aveage winding losses, fo each winding, is calculated fom P = R I Cu Cu L (4.3) whee I L is the RMS cuent though the coesponding winding with esistance R Cu. The esisto used to model the ion losses of the entie coe is denoted R Fe. Hee, the magnetising cuent i m is used to calculate the flux density of the coe. The magnetising cuent, efeed to the pimay winding, is calculated as N i i N i N3 m = L1 + L + N i L3 (4.4) 1 whee N 1, N and N 3 denotes the numbe of winding tuns fo the pimay, seconday and tetiay windings, espectively. Note that fo the single winding inducto and the two winding tansfome, the magnetising cuent is found just by setting the cuents of the absent windings equal to zeo. Accoding to Appendix D, the flux density depends on the magnetising cuent as 1 1

109 4. Devices B Li N A 1 m = 1 Fe (4.5) whee L 1 denotes the self inductance of the pimay and A Fe the ion coe coss-sectional aea, pependicula to the magnetic flux. By pefoming spectal analysis on the flux density calculated, the loss associated with each fequency component is calculated accoding to (4.). The ion losses fo these fequencies ae summed and multiplied with the ion coe volume, giving the total ion losses P Fe, in the unit W. The esisto R Fe, used to model the ion losses in the simulation equivalent model, is calculated fom R Fe V = P RFe Fe (4.6) whee V RFe is the RMS value of the magnetising voltage, see Figue 4.5. Note that the equivalent models ae only used to estimate the influence of the magnetic component losses on the othe devices of the entie cicuit. To calculate the actual losses of the magnetic components, equation (4.) is used on the simulated data. Note that also the magnetic coupling factos, k 1, k 13 and k 3, ae included in the thee winding tansfome model shown in Figue Capacitos Diffeent kinds of capacitos ae used in powe electonic cicuits. Hee, only two ae discussed, the non-polaised metallised film polypopylene capacito and the polaised wet aluminium electolytic capacito. Nonpolaised capacitos ae used in output filtes and fo applications with high capacito voltage time deivative, like commutation cicuits. Polaised capacitos ae used when a high capacitance is needed, fo example fo DC link capacitos. Design Metallised film polypopylene capacitos have a thin plastic film to suppot the metal laye of the electodes. The plastic used fo the film can fo example be polyeste. If the plastic film has electodes (of the same polaity) on both sides it is efeed to as double metallised film. The dielectic consists of a polypopylene film. To avoid ai pockets esulting in a locally high electic field stength, the polypopylene film should be somewhat poous to be able to absob oil, accoding to [6]. 11

110 4. Devices Wet aluminium electolytic capacitos contains a fluid, the electolyte, between the aluminium electodes. The electolyte is absobed by pape in between the aluminium electodes, in ode to avoid ai pockets. Since the electolyte is conductive, the aluminium electodes ae electically close togethe, only sepaated by the dielectic of the capacito. The dielectic constitutes of a thin aluminium oxide laye on the positive electode. Simulation model Both the metallised polypopylene and the wet aluminium electolytic capacitos ae modelled by the capacito equivalent shown in Figue 4.6. i C R ESR L ESL C Figue 4.6 Capacito simulation model. In Figue 4.6 two paasitic elements ae shown, L ESL and R ESR. The equivalent seies inductance L ESL is due to stay inductance of the leads and the metal layes foming the electodes. A numeical value fo L ESL is often specified in the manufactue data sheets. The equivalent seies esistance R ESR is due to the esistance of the leads and also dielectic losses. Theefoe, R ESR is fequency dependent accoding to tanδ RESR( f) = Rs + π fc (4.7) whee the tem tan δ is efeed to as the dielectic dissipation facto. As the name hints, the dielectic dissipation facto is due to losses within the dielectic itself. This tem is egaded as constant fo the possible opeating fequencies. Howeve, since the voltage acoss the dielectic deceases with inceasing fequency fo a constant RMS value of the capacito cuent i C, the dielectic losses also decease with inceasing fequency as concluded fom (4.7). The constant tem R s contained in the expession fo R ESR is due to the esistance of the leads and the electodes. Howeve, since the equivalent seies esistance is fequency dependent, it can not be used diectly in an online simulation model. Instead, spectal 1

111 4. Devices analysis is used to calculate the RMS capacito cuent fo each fequency. Then the loss of the coesponding fequency is calculated fom ESR ESR C P ( f) = R ( f) I ( f) (4.8) The loss contibution fo the diffeent fequency components ae summed, which gives the total losses P ESR. Finally, an equivalent seies esistance without fequency dependency is calculated accoding to R ESR PESR = (4.9) I whee I C is the RMS value of the total capacito cuent. Also in this case, the simulation model R ESR is only used to influence the est of the powe electonic cicuit. To calculate the capacito losses, each fequency component is teated sepaately, as in expession (4.8). C 13

112

113 5 Simulation Simulations ae used in ode to evaluate the battey chage equipped with the diffeent quasi esonant DC links investigated. The passive component values used fo the esonant links ae calculated accoding to the design expessions developed in Chapte 3. The simulations ae used to veify the design expessions and to estimate the enegy efficiency of the battey chage using the diffeent quasi esonant DC links. The simulations, giving the wavefoms and efficiency, ae pefomed fo battey chaging at ated powe. A had switched battey chage is also simulated as a efeence to investigate the impovement in efficiency, if any, gained by the use of an quasi esonant DC link. The Analogy softwae SABER is used fo all the simulations in this chapte. 5.1 Geneal simulation model The geneal simulation model used thoughout all the simulations is shown in Figue 5.1. Note that both the line side and the battey side output filtes consist of inductos only, to simplify the contolle. The quasi esonant DC link is shown as a block named QRDCL, to show its location independent of the esonant cicuit used. The DC link capacito is not included in this block, but dawn outside fo visibility. Fo the had switched battey chage, the DC link supply ails of the battey chage is diectly connected to the DC link capacito. This is achieved simply by ceating a QRDCL block with two feed though connections. The esonant link contolle block is needed both to delay the modulato contol signals until zeo voltage is achieved and also to contol the esonant link switches. To accomplish the latte need, diffeent signals depending on the type of esonant link used, ae measued. The contol of some of the cicuits even elies on knowledge about the esonant link output cuent both pio to and afte each esonant cycle. To contol these cicuits, the load cuents ae also used by the esonant link contolle. The contolle and modulato block is independent of the cicuit used and is descibed in Appendix A and Appendix B.

114 5. Simulation Utility Gid Line Filte L line L line L line Battey Filte Vehicle Battey Pack L batt QRDCL C dc c a,act c b,act c c,act c both c dc,act Resonant Link Contolle Resonant Link Contol Signals c a,mod c b,mod c c,mod c dc,mod i a i b v ab Contolle & Modulato v bc i batt v batt v dc i batt,ef Figue 5.1 Geneal simulation model. The utility gid consideed in the simulations is a symmetic 4 V, 5 Hz thee phase AC system. This coesponds to the consume level of the Swedish powe gid. The ated DC link voltage used in the simulations is set to 75 V. The ated battey voltage is 375 V, which is appoximately two times highe than the battey voltage of most pesent electic vehicles. Howeve, the battey chage simulated has the same atings as the one designed and tested in [3], except fo the ated powe which is 1 kw in this case but 75 kw in [3]. The fequency of the modulation caie is selected to equal 4.95 khz, implying that the modulato switching fequency is 4.95 khz. Note that the switching delay intoduced by the esonant link opeation, might esult in a deceased actual convete switching fequency. Geneal simulation devices and passive components The semiconducto switches used in the simulations ae selected to wok as close to as possible, but below, the level given by (.1). The line and battey side convete IGBTs used in the simulations ae of the medium fast types Intenational Rectifie IRGPH4M and IRGPH5M, espectively. The quasi esonant DC link IGBTs ae all of the fast type 16

115 5. Simulation IRGPH5K fom the same manufactue. The powe diodes ae of type Hais MR115. To meet the constaint (.1) seveal diodes ae seies o paallel connected, when needed. The IGBTs have a voltage ating of 1 V, implying that only paallel and not seies, connection is needed. These semiconducto devices ae selected since they ae the only suitable by means of atings, contained in the Analogy softwae SABER used fo the simulations. As mentioned in Chapte 4, the esistance of the IGBT gate esisto affects the switching times. Fo all IGBTs used in the simulations, the gate esistos ae selected to the minimum values ecommended in [66]. This is done due to the fact that the switching times ae only specified fo these values in [66]. Thus, the model validity by means of switching times fo the had switched case, can only be investigated fo these gate esisto values. Theefoe, each IGBT of type IRGPH5M and IRGPH5K is equipped with a 5. Ω gate esisto and each IRGPH4M is equipped with a 1. Ω gate esisto. The case tempeatue, fo all semiconductos used in the simulations, is set to 7 C. Besides the gate esistos each IGBT gate dive cicuit consists of an ideal voltage souce which assumes the discete values ±15 V, depending on the gate dive cicuit input signal level. In the had switched case a blanking time is also implemented in the gate dive cicuits, to pevent fom tansient shot cicuit duing switching. Essentially, blanking time is povided by delaying IGBT tun-on by µs but not delaying tun-off. The output filte inductos on both the line and battey sides ae simulated as being based on ion powde coes, to eliminate the poblem of ai gap losses, see Appendix D. Howeve, fo the ion powde coes manufactued by Micometals the opeating tempeatue is of geat concen. In the data book [67] it is stated that phenomena like themal unaway can become a poblem at opeational tempeatues as low as 75 C. It is also stated that the coe mateials is especially pone to themal unaway if the coe loss exceeds the coppe loss, which should be avoided. The inductive elements of the quasi esonant DC links used in the simulations ae theefoe designed to opeate at a tempeatue close to 9 C at an ambient tempeatue of 4 C, which make the inductos athe bulky with espect to the ating. Fo the line and battey side inductos such a modeate tempeatue ise would make the inductos even too bulky. Theefoe, the filte inducto opeating tempeatue is limited to 15 C instead. Accoding to the data book povided by Micometals, this is not a sevee poblem due to the fact that at this athe low fequency, the dominating coe loss is likely to be hysteesis loss which is not pone 17

116 5. Simulation to themal unaway. Futhemoe, it is also assumed that only one side of the inducto is actually a cooling suface, since the inductos must be mounted somehow. This esults in quite consevative output filte designs. The design pocedue is simila to the one fo a tape wound C-coe discussed in Appendix D. Howeve, ion powde coes ae usually not equipped with an explicit ai gap but instead seveal distibuted ai gaps esulting fom the insulation between the ion powde gains. This means that the mateial choice depends on both the ion losses and the desied inductance. The manufactues povide an quantity, the A L value, fo each coe and mateial it is available in. The inductance L is elated to the A L value accoding to L = A N L (5.1) Selection of appopiate line side output filte inductance values is coveed in [4]. The battey side inductance value is detemined in a simila way and is theefoe not discussed hee. The most impotant data fo the output filtes used in the simulations ae given in Table 5.1 below. In Table 5.1, the winding DC esistance is given, which is calculated based on the assumption that the winding tempeatue is 9 C. Skin effect of the winding cuents is neglected in all the simulations, since it is assumed that Litz wie [44], i.e. seveal paallel conductos, is used. Table 5.1 Line and battey side inductos used in the simulations. Inducto Coe A L (nh/n ) R Cu (mω) L (mh) R th ( C/W) L line T L batt 3 T The coe mateial used in the output filtes, i.e. Micometals mateial -8, has the constants fo calculation of the losses accoding to (4.), given in Table 5. [67]. The same constants ae also given fo some othe mateials used fo the esonant link inductos, which ae discussed late in this chapte. Table 5. Coe mateial loss calculation constants. Mateial a b c d

117 5. Simulation Since the coe losses given by expession (4.) is specific, i.e. pesented in mw/cm 3, the volume of the coe is needed to detemine the actual losses. The volume of a single coe of type T65 is 734 cm 3 accoding to [67]. The DC link capacito is selected based on its cuent handling capability and on the capacitance. Futhemoe, electolytic capacitos usually do not have a ated voltage exceeding 5 V, implying that seies connection is necessay. An appopiate capacitance value is detemined in [4], and is not discussed hee. The DC link capacito selected fo simulation actually consists of two seies connected 4.7 mf, 45 V capacitos manufactued by Rifa [65]. The equivalent popeties, fo the two capacitos togethe ae given in Table 5.3 below. Some of the data given in Table 5.3 ae actually not given explicit in [65], but instead deived to fit the model of Figue 4.6. Howeve, the data given in Table 5.3 do not contadict the data given by the manufactue. Table 5.3 Specification of the DC link capacito used in the simulations. Capacito Type C (mf) tanδ R s (mω) L ESL (nh) R th ( C /W) C dc PEHYV447DQ Geneal design citeia fo the quasi esonant DC links All the quasi esonant DC links ae designed to exhibit a maximum output voltage deivative of 1 V/µs. Futhemoe, the maximum duation of the zeo voltage inteval is selected to be 1 µs. Nevetheless, the duation of the zeo voltage inteval is allowed to be longe fo enegy stoage o clamp capacito voltage contol, i.e. 1 µs maximum duation is without application of such contol. Fo all the quasi esonant DC links utilising clamp action, the clamping facto K is set to 1.. The maximum esonant link output cuent change assumed at the design stage, equals the battey chaging cuent. Actually, this is the wost case esonant DC link output cuent change only if it is assumed that none of the line side convete half bidges ae switched simultaneously, to contibute to a lage change. 5. Simulation of the two switch passively clamped quasi esonant DC link Fist, appopiate passive component values ae detemined fo the two switch passively clamped DC link. Then, the simulation model is discussed and suitable passive component paamete values fo loss calculation ae 19

118 5. Simulation given. Last, the simulation esults veifying the design expessions, ae shown and the losses calculated. Figue 5. shows the passively clamped two switch quasi esonant DC link, used in the simulation model in Figue 5.1. Note that the DC link capacito is included in Figue 5., even though it is not a pat of the QRDCL block shown in Figue 5.1. L 1 i o i C S 1 L v C C i D 1 D S i 1 L 3 D 3 C dc V dc i 3 Figue 5. The passively clamped two switch quasi esonant DC link used in the simulation, including the DC link capacito. Simulation model and paametes Since this cicuit is passively clamped and has no enegy stoage capacito, capacito voltage contol is not needed in this case. Also, this cicuit has a thid degee of feedom, which in this case is used to limit the esonant inducto cuent i to the same level as the ated battey chaging cuent. The design expessions fo this cicuit, i.e. (3.58), (3.63) and (3.64) detemined in Section 3.1, gives appoximately the following component values L1 = 1. 8 µ H L = µ H L3 = 5. 5 µ H C = 66 nf (5.) The passive component values selected, only appoximately fulfils the design expessions since thee ae discete steps between component values manufactued. The simulations ae intended to be as ealistic as possible and theefoe only available component values ae used. The inductive components ae designed accoding to Table 5.4 below. Note that in this design the magnetic coupling facto of the clamping tansfome, i.e. L 1 /L 3, is assumed to be pefect even though no pecautions ae made to fulfil this. In the next chapte, a battey chage using this quasi esonant DC link is implemented and in this case the magnetic coupling facto is consideed in the design. 11

119 5. Simulation Table 5.4 Resonant link inducto specifications used in the simulations. Inducto Coe A L (nh/n ) N (tuns) R Cu (mω) R th ( C/W) L 1 /L 3 T5-. 71/ / L T The esonant capacito C, actually consists of 3 paallel nf polypopylene capacitos with loss paametes appoximated fom the Rifa PHE 48 seies [64]. The loss paametes used fo the esonant capacitos of all the quasi esonant links ae given by R s = mω (5.3) tan δ =. 78 The themal esistance, R th, vaies fo the esonant link capacitos fo the diffeent cicuits, depending on thei diffeent physical size. Howeve, they ae all designed not to exceed a tempeatue ise of 35 C. The equivalent seies inductance, L ESL in Figue 4.6, is set to zeo fo all the esonant capacitos in the simulations due to lack of manufactue data. The esonant link IGBTs, S 1 /S accoding to Figue 5., actually consist of two paallel IGBTs of type IRGPH5K each. As peviously mentioned, each IGBT is equipped with a 5. Ω gate esisto. The diodes D 1 /D ae modelled by fou paallel connected MR115 diodes each. The clamping diode, D 3, consists of five seies connected diodes of the same type. The eason fo this is that D 3 has to withstand a blocking voltage of 45 V. Since MR115 is a 15 V diode, five such ae needed to fulfil the equiement given by (.1). Simulated wavefoms and losses To veify the design expessions given fo the passively clamped two switch quasi esonant DC link, i.e. (3.58), (3.63) and (3.64), simulations ae used. One peiod of the fundamental gid fequency is simulated in ode to calculate the aveage losses, since the losses ae likely to be dependent of the cuent level and thus vay with time. The simulated wavefoms ae pesented in thee diffeent time scales. The shotest time scale is fo investigation of the soft switching behaviou of the IGBTs in the cicuit. The medium time scale is used to show the esonant link wavefoms, simila to the ones shown in Chapte 3. The longest time scale equals one peiod of the fundamental gid fequency, to show how the line and battey cuents ae affected by soft switching. 111

120 5. Simulation Fist, the quasi esonant DC link quantities, i.e. voltages and cuents, of inteest ae investigated. Figue 5.3 shows the esonant link wavefoms at tun-on of the uppe IGBT of the battey side convete at ated cuent, i.e. maximum incease of the esonant link output cuent i o. As discussed in the pevious section, this is the wost case incease only if it is assumed that no othe half bidge is switched duing the esonant cycle, contibuting to a lage incease. Fom Figue 5.3 it is seen that the esonant link voltage, v C, entes clamping. Accoding to the design constaints this should not happen at a maximum incease of the output cuent, since the esonant cuent i 1 should equal the output cuent befoe clamping occus. This in tun esults in a esonant link capacito cuent i C equal to zeo which implies that the incease in v C is finished. v C [V] i 1, i, i 3 [A] 4 dv C /dt [V/µs] Figue t [µs] Resonant link wavefoms at an output cuent incease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey) and the esonant cuents, i 1 (bottom, black), i (bottom, dak gey) and i 3 (bottom, light gey). Thee ae mainly two easons why clamping still occus in Figue 5.3. Fist, the battey cuent ipple, due to the switched convete output 11

121 5. Simulation voltage, gives a maximum esonant link output cuent incease lowe than the aveage battey cuent. Second, it was assumed in the deivation of the design expessions that the esonant cycle stats at steady state conditions, i.e. without oscillation between L 1 and C. As seen in Figue 5.3, v C is inceasing immediately befoe the esonant cycle is stated implying a positive capacito cuent i C. This also implies that i 1 is highe than the esonant link output cuent i o, which causes i 1 to be highe than needed at the end of the esonant cycle, thus clamping occus. The positive initial esonant capacito cuent i C also esults in that moe enegy is being tansfeed to L since i 1 is lage than i o, theeby counteacting the dischage of C. Theefoe, the peak value of i becomes somewhat highe than the value specified fo the design constaint (3.64). Figue 5.4 shows the esonant link wavefoms at tun-off of the uppe IGBT of the battey side convete, when the battey chage is opeated at nominal load, i.e. maximum decease of the esonant DC link output cuent i o. v C [V] i 1, i, i 3 [A] 4 dv /dt [V/µs] C Figue t [µs] Resonant link wavefoms at an output cuent decease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey) and the esonant cuents, i 1 (bottom, black), i (bottom, dak gey) and i 3 (bottom, light gey). 113

122 5. Simulation In Figue 5.4 above, it is seen that the esonant link voltage time deivative is appoximately 1 V/µs, which was the maximum value specified fo the design constaint (3.63). Note that a lage output cuent decease, which could esult if seveal half bidges of the battey chage change switch state at the same esonant cycle, gives an even highe esonant link voltage time deivative. Also note that fo these simulations, the duation of the zeo voltage inteval is kept constant at 1 µs independent of the esonant cycle. Fom Figue 5.3 and Figue 5.4, it is concluded that the design expessions gives the desied behaviou of the esonant cicuit. Howeve, some impotant measues ae not coveed by the design expessions, fo example the duation of the esonant cycle including the clamping inteval. This is a sevee dawback, since the maximum switching fequency obtainable is stongly affected. The collecto cuent and collecto-emitte voltage at tun-off of the quasi esonant DC link switch S 1, fo the cases shown in Figue 5.3 and Figue 5.4, ae shown in Figue 5.5. The coesponding wavefoms fo S looks exactly the same since the tansistos ae identical in the simulation model. In eality, thee ae paamete deviations between S 1 and S, esulting in slightly diffeent wavefoms fo the two tansistos. v CE [V] i C [A] v CE [V] i C [A] Figue t [µs] t [µs] Tun-off wavefoms fo the esonant link IGBT S 1 when the esonant link output cuent is maximum inceased (left) and maximum deceased (ight). The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). Note the diffeence in the IGBT cuent tail fo the two cases shown in Figue 5.5, which is due to the diffeence in the esonant link voltage deivative. The esonant cuent i can patly commutate to the diodes D 1 and D duing the zeo voltage inteval, which is shown as a step decease of the IGBT collecto cuent in the leftmost pat of Figue

123 5. Simulation Figue 5.6 shows the collecto-emitte voltage and the collecto cuent fo the uppe IGBT of the battey side convete, fo the esonant cycles shown in Figue 5.3 and Figue 5.4. Note the diffeence in the cuent tail bump at convete IGBT tun-off, compaed to the case of the esonant link IGBT tun-off shown in Figue 5.5. The low magnitude of the cuent tail bump appeaing fo the convete IGBTs is pobably due to the fact that intenal ecombination takes place duing the zeo voltage inteval. This esults in vey low convete losses fo the case whee the passively clamped two switch quasi esonant DC link is used fo the battey chage, which is shown late. v CE [V] i C [A] v CE [V] i C [A] Figue t [µs] t [µs] Switching wavefoms fo the uppe IGBT of the battey side convete at ated powe, tun-on (left) and tun-off (ight). The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). In Figue 5.7, one of the line side phase cuents and the battey cuent, fo one peiod of the AC side fundamental, ae shown fo chaging at ated powe and battey voltage. i a, i batt [A] - Figue t [ms] Line cuent in one phase (black) and battey cuent (gey). Both cuents ae defined as positive going out of the convetes. 115

124 5. Simulation Note the pesence of low ode hamonics in the cuents of Figue 5.7, which is due to the fact that the switching instants commanded by the modulato ae delayed by the opeation of the quasi esonant DC link. Futhemoe, the length of this time delay vaies due to the fact that the duation of the clamping inteval is vaying. Efficiency In ode to compae the efficiency of the diffeent quasi esonant DC links, the losses of the passive components ae calculated as descibed in Chapte 4. The simulation softwae used, diectly gives the instantaneous semiconducto losses which ae integated fo one peiod of the fundamental fequency of the AC mains, to give the aveage losses. The load condition consideed coesponds to battey chaging at ated powe. Howeve, since the battey chage cuent contolles have not eached steady state, the actual output powe is likely to deviate slightly fom the ated. In the simulation investigated hee, the aveage powe fed to the batteies was 1.14 kw. The losses of the quasi esonant link is listed in Table 5.5. Table 5.5 Losses of the passively clamped two switch quasi esonant DC link. Component C L 1 /L 3 L S 1 /S D 1 /D D 3 Losses (W) The total losses fo each of the blocks ae listed in Table 5.6. Note that the output filtes dissipate moe than half the total losses. Table 5.6 Losses fo the entie battey chage at ated powe. Component/ Line side Battey side Block Convete Filte Convete Filte DC link capacito Resonant cicuit Losses (W) This gives a total efficiency of 93.5 %. The efficiency fo the passively clamped quasi esonant cicuit including the convetes, equals 97.5 %, accoding to the simulations. 116

125 5. Simulation 5.3 Simulation of the one switch passively clamped quasi esonant DC link In this section passive component values fo the one switch passively clamped DC link ae detemined fom the expessions found in Chapte 3. Passive component paamete values fo loss calculation ae also given. Simulation esults veifies the design expessions. The efficiency is calculated based on the loss paametes and the semiconducto losses given by the simulato. Figue 5.8 shows the QRDCL block fo simulation of the passively clamped one switch quasi esonant DC link, used in the simulation model in Figue 5.1. Note that the DC link capacito is included in Figue 5.8. i o i 1 M L 1 L 3 C i i C L v C D 3 C dc V dc S D i 3 Figue 5.8 The passively clamped one switch quasi esonant DC link used in the simulation, including the DC link capacito. Simulation model and paametes Fo the one switch passively clamped quasi esonant DC link shown in Figue 5.8, the esonant link voltage v C has to be measued to detect both zeo voltage and clamping, as fo the pevious cicuit. Futhemoe, the esonant cuent i also has to be measued in ode to detect its zeo cossing duing the zeo voltage inteval. When the zeo cossing occus, S should be tuned off by setting its gate-emitte voltage negative, since i commutates to the feewheeling diode D. This is efeed to as natual commutation and is favouable since no cuent tail appeas fo the esonant link IGBT S. The design expessions detemined in Section 3., i.e. (3.137), (3.138) and (3.139), ae used to calculate appopiate passive component values based on the assumption that the magnetic coupling facto between the esonant inductos L 1 and L is.9. The passive component values selected fo the simulation model ae thus given by 117

126 5. Simulation L1 = 64. µ H L = µ H L3 = 16 µ H C = 165. nf (5.4) Note that these passive component values ae calculated fo a maximum cuent step coesponding to a ated battey cuent ten pecent highe than the specified. This is done to patly compensate fo the evese ecovey cuent of the esonant link diode D, even though not necessay fo eliable opeation which is futhe discussed late on in this section. The inductive components modelled fo the simulation ae designed accoding to Table 5.7. Also fo this esonant cicuit, the magnetic coupling facto of the clamping tansfome, i.e. L 1 /L 3, is assumed to be pefect. Still, no pecautions ae made in the design of the simulation model clamping tansfome to fulfil this. The same is also tue fo the magnetic coupling facto between L 1 and L, i.e. it is assumed that it equals.9 though not consideed fom a design point of view. Table 5.7 Resonant link inducto specifications used in the simulations. Inducto Coe A L (nh/n ) N (tuns) R Cu (mω) R th ( C/W) L 1 /L /L 3 T5-4. 4/1/./1.6/ The esonant capacito C is modelled by 11 paallel 15 nf capacitos with loss paametes appoximated fom the Rifa PHE 48 seies, given in Section 5.. Note that the athe high numbe of capacitos used hee is needed pimaily to limit the tempeatue ise and secondaily to adjust the total capacitance. The esonant link IGBT S is modelled as five IRGPH5K IGBTs connected in paallel. Each IGBT is equipped with a 5. Ω gate esisto. The diode D is modelled by nine paallel diodes of type MR115. As fo the two switch countepat, the clamping diode D 3, also in this case consists of five seies connected diodes of the same type. Simulated wavefoms and losses Simulations ae used to veify the design expessions given fo the passively clamped one switch quasi esonant DC link. Also fo this cicuit the esults ae pesented in thee diffeent time scales, in ode to focus on diffeent pefomance citeia. 118

127 5. Simulation Fist the quasi esonant DC link quantities, i.e. voltages and cuents, of inteest ae investigated. Figue 5.9 shows the esonant link wavefoms at tun-on of the uppe IGBT of the battey side convete at ated cuent, i.e. maximum incease of the esonant link output cuent i o. v [V] C dv /dt [V/µs] C i 1, i, i 3 [A] Figue t [µs] Wavefoms fo the passively clamped one switch quasi esonant DC link at an output cuent incease coesponding to the ated maximum. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey), and the esonant cuents, i 1 (bottom, black), i (bottom, dak gey) and i 3 (bottom, light gey). Fom Figue 5.9 it is seen that the esonant link voltage, v C, entes clamping. Still, the capacito cuent becomes slightly negative due to evese ecovey of the diode D appeaing when i cosses zeo duing the esonant link voltage amp up inteval. This also implies that i 1 is slightly lowe than the output cuent fed to the convetes. Clamping occus due to the fact that v C is lowe than V dc at this instant which implies that i 1 will continue to incease to become lage than the output cuent i o. This phenomena is alleviated by the ten pecent highe maximum output cuent incease used fo the design. Howeve, the dip in v C when 119

128 5. Simulation i cosses zeo duing the esonant link voltage amp up inteval is deceased by designing fo a highe output cuent incease than expected. In Figue 5.9 it is seen that the esonant link voltage deivative exceeds 1 V/µs duing the amp down inteval. This is due to the fact that the esonant cycle stats at a esonant link voltage close to the clamp level and at a slightly negative esonant link capacito cuent. Note the high peak value of the esonant inducto cuent i, shown in Figue 5.9. Also the peak value of i 1 is athe high. Togethe these two cuents contibute to a esonant link capacito peak cuent close to A. The high peak cuent is the eason why 11 capacitos ae needed to model the esonant link capacito C, without unealistic tempeatue ise appeaing. Fom Figue 5.9 it is also concluded that the maximum duation of the zeo voltage inteval is close to 1 µs, which is desied fom the design constaints. Note that also fo this cicuit the duation of the esonant cycle is not consideed by the design expessions, i.e. the maximum switching fequency obtainable is not contolled. Figue 5.1 shows the esonant link wavefoms at tun-off of the uppe IGBT of the battey side convete, when the battey chage is opeated at nominal load, i.e. maximum decease of the esonant DC link output cuent i o. Also in this case, the decease equals the wost case only if none of the line side convete half bidges ae switched duing the esonant cycle. Howeve, fo this cicuit the maximum time deivative of the esonant link voltage do not appea duing the amp up inteval, i.e. the i 1 cuent step of Figue 5.1 do not coespond to the wost case anyway, which was also concluded in Section 3.. Fom Figue 5.1 it is also seen that the esonant link voltage duing the amp down inteval is well below 1 V/µs in this case, unlike the case shown in Figue 5.9. This is due to the fact that in Figue 5.1, the esonant cycle stats at a esonant link voltage level lowe than the DC link voltage. As seen in Figue 5.9 and Figue 5.1 the selected component values fulfil the design constaints. Howeve, it is shown that the maximum voltage deivative is highe than the desied 1 V/µs if the esonant cycle stats fom a level exceeding the DC link voltage with a non-zeo esonant capacito cuent. This is due to the fact that the design expessions ae deived based on the assumption that the esonant cycle stats fom est, i.e. with the esonant link voltage v C equal to the DC link voltage V dc. 1

129 5. Simulation Futhemoe, it is also shown that evese ecovey of the diode D influences the esonant link wavefoms, especially at high output cuent incease. Hee, this is solved by designing the esonant cicuit fo a ten pecent highe output cuent incease than the actual. v [V] C dv /dt [V/µs] C i 1, i, i 3 [A] t [µs] Figue 5.1 Resonant link wavefoms at an output cuent decease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey) and the esonant cuents, i 1 (bottom, black), i (bottom, dak gey) and i 3 (bottom, light gey). Figue 5.11 shows the collecto-emitte voltage and the collecto cuent fo the uppe IGBT of the battey side convete, fo the esonant cycles shown in Figue 5.9 and Figue 5.1. Note the low cuent tail bump at convete IGBT tun-off. The quasi esonant DC link tansisto S, tuns off natually as discussed peviously in this section. This means that no cuent tail appeas, which is favouable since the switching losses becomes vey low. The high peak value of the esonant cuent i esults in high conduction losses fo S /D. 11

130 5. Simulation v CE [V] i C [A] v CE [V] i C [A] t [µs] t [µs] Figue 5.11 Switching wavefoms fo the uppe IGBT of the battey side convete at ated powe, tun-on (left) and tun-off (ight). The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). In Figue 5.1, one of the line side phase cuents and the battey cuent ae shown fo one peiod of the AC side fundamental, fo chaging at ated powe and battey voltage. Compaed to the coesponding cuents fo the peviously discussed two switch countepat, shown in Figue 5.7, it is clealy seen that the low fequency distotion is consideably lowe. This is due to the fact that the aveage duation of the esonant cycle is shote fo the passively clamped one switch quasi esonant DC link, compaed to the case fo the two switch countepat. i a, i batt [A] t [ms] Figue 5.1 Line cuent in one phase (black) and battey cuent (gey). Both cuents ae defined as positive going out of the convetes. Efficiency The aveage losses ae calculated also fo this cicuit, based on simulation esults. The load condition consideed coesponds to battey chaging at ated powe. Fo a simulation time coesponding to the peiod of the 1

131 5. Simulation gid fundamental, i.e. ms, the battey chage output powe becomes kw. The losses of the quasi esonant DC link is listed in Table 5.8. Table 5.8 Losses of the passively clamped one switch quasi esonant DC link. Component C L 1 /L /L 3 S D D 3 Losses (W) The total losses fo each of the blocks ae listed in Table 5.9. Table 5.9 gives a total efficiency equal to 94. %. The efficiency of the passively clamped one switch quasi esonant cicuit including the convete is equal to 97.7 %, accoding to the simulations. Table 5.9 Losses fo the entie battey chage at ated powe. Component/ Line side Battey side DC link Resonant Block Convete Filte Convete Filte capacito cicuit Losses (W) Simulation of the paallel quasi esonant DC link In this section appopiate passive component values ae detemined fo the paallel quasi esonant DC link. The simulation model semiconductos and passive component paametes fo loss calculation ae given. Simulation esults veifying the design expessions ae shown and the battey chage efficiency is calculated. In Figue 5.13, the QRDCL block fo simulation of the paallel quasi esonant DC link, used in the simulation model in Figue 5.1, is shown. D s i o i C S S s D v C C dc V dc C L i L C e V e Figue 5.13 The paallel quasi esonant DC link used in the simulation, including the DC link capacito. 13

132 5. Simulation Simulation model and paametes Fo contol of the paallel quasi esonant DC link the esonant link output cuent i o must be measued, since the tip cuent levels ae calculated based upon knowledge of i o. The output cuent fo each convete half bidge is measued (one of the output cuents of the line side convete is actually calculated fom the othe two). Togethe with the actual switch state and the switch state to be set, the pesent and the next level of the output cuent, i.e. I o1 and I o, ae calculated. Based on these output cuent levels, the tip cuents ae detemined. Note that also the esonant inducto cuent i L has to be measued to detect the tip cuent cossings and to detect when the esonant link switch S can be tuned off by means of an appopiate gate signal, which is afte i L has commutated fom S to D. The esonant link voltage v C also has to be measued, since the convete half bidges should be shoted by applying appopiate gate signals to all the convete IGBTs when the zeo voltage inteval is enteed. The esonant link voltage has to be measued also to detect the end of the esonant link voltage amp up inteval, whee S s should be tuned on again. Also, the enegy stoage capacito voltage, V e, is measued since it has to be contolled fo pope opeation of the paallel quasi esonant link. This cicuit has thee passive component values to be selected, L, C and C e, see Figue The design expessions fo this cicuit detemined in Section 3.3, i.e. (3.187) and (3.191), gives appopiate values fo L and C. The enegy stoage capacito value is selected fom simulations. Fo the implementation in [41], the capacitance of C e is selected as 7 times highe than the one of C. In [41], this means an enegy stoage capacito C e, of 1 µf which is a suitable value also hee. The passive component values selected fo the simulation model of the paallel quasi esonant DC link ae selected accoding to L C C e = µ H = 33 n F (5.5) = 94 µ F The simulation model esonant link inducto L, is designed accoding to Table

133 5. Simulation Table 5.1 Resonant link inducto specifications used in the simulations. Inducto Coe A L (nh/n ) N (tuns) R Cu (mω) R th ( C/W) L T-B The esonant link capacito C is consideed as being selected fom the Rifa PHE 48 seies. The loss paametes fo such capacitos ae given in Section 5.. The enegy stoage capacito C e is modelled as two paallel polypopylene capacitos, MSR-D manufactued by Ica. The elevant data fo the esulting, i.e. paallel equivalent, capacito is listed in Table 5.11 below. Table 5.11 Specification of the enegy stoage capacito used in the simulations. Capacito Type C (µf) tanδ R s (mω) L ESL (nh) R th ( C /W) C e MSR-D The simulation model esonant link IGBTs, S and S s, actually consist of thee paallel IGBTs of type IRGPH5K each. As peviously mentioned, each such IGBT is equipped with a 5. Ω gate esisto. The diodes D and D s ae modelled by six paallel connected Hais MR115 diodes each. The behaviou of the paallel quasi esonant DC link is simulated in the battey chage application in ode to veify the design expessions given, i.e. (3.187) and (3.191). Howeve, it is somewhat complicated to validate the simulation esults by means of wavefoms fo the cicuits elying on enegy stoed in a capacito, since the enegy stoage capacito voltage is contolled which affects the esonant link wavefoms. Still it is impotant to simulate the entie cicuit, i.e. without eplacing the enegy stoage capacito with a constant voltage souce, since the contol action needed do indeed affect the efficiency obtained. Figue 5.14 shows the esonant link wavefoms at tun-on of the uppe IGBT of the battey side convete at ated cuent, i.e. maximum incease of the esonant link output cuent i o. In Figue 5.14 it is seen both that the duation of the zeo link voltage inteval is longe than desied and that the esonant link voltage deivative is well below the maximum allowed. The eason why the duation of the zeo voltage inteval is longe than expected fom the design expessions, is that it is maintained longe on 15

134 5. Simulation pupose, in ode to decease the enegy stoage capacito voltage V e, i.e. due to contol action. The maximum esonant link voltage deivative is only expeienced fo the minimum output cuent I o, which is not achieved fo the case shown in Figue v [V] C i L, i C [A] 4 dv /dt [V/µs] C t [µs] Figue 5.14 Resonant link wavefoms at an output cuent incease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey) and the esonant cuents, i L (bottom, black) and i C (bottom, gey). Figue 5.15 shows the esonant link wavefoms at tun-off of the uppe IGBT of the battey side convete, when the battey chage is opeated at nominal load, i.e. maximum decease of the esonant DC link output cuent i o. In Figue 5.15 the duation of the zeo voltage inteval is shote than the one shown in Figue 5.14, due to the fact that the cuent decease at its most. Still, it is longe than pedicted fom the analysis in Section 3.3, due to the contol actions made to decease the enegy stoage capacito voltage V e. As shown in Figue 5.15, the esonant link voltage deivative is well below the specified maximum also in this case. 16

135 5. Simulation v C [V] i, i [A] L C 4 dv C /dt [V/µs] t [µs] Figue 5.15 Resonant link wavefoms at an output cuent decease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v C (top, black) and its time deivative (top, gey) and the esonant cuents, i L (bottom, black) and i C (bottom, gey). The eason why the maximum allowed esonant link voltage deivative is not appeaing fo the cases shown in Figue 5.14 and Figue 5.15, is that the cicuit is designed fo a minimum output cuent equal to dischaging of the battey chage at ated cuent. In Chapte 1, it is stated that the battey chage should be able to opeate as an electonic gastubine, i.e. to suppot the powe gid with peak powe duing peiods of high powe demand. This means that the battey could be dischaged with a cuent coesponding to the ated, which fo this cicuit becomes the limiting case by means of maximum esonant link voltage deivative. The esonant cycle time is not consideed fo this cicuit eithe. Howeve, the cycle time fo this quasi esonant DC link is the shotest of the fou investigated. The collecto cuent and collecto-emitte voltage at tun-off of the quasi esonant DC link IGBTs, S s and S, fo the case shown in Figue 5.15 i.e. 17

136 5. Simulation tun-off of the uppe IGBT of the battey side convete, ae shown in Figue v CE [V] i C [A] v CE [V] i C [A] t [µs] t [µs] Figue 5.16 Tun-off wavefoms fo the esonant link IGBTs S s (left) and S (ight) when the esonant link output cuent is deceased by its maximum. The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). Note the diffeence in the cuent tail fo the two IGBTs shown in Figue The seies IGBT S s tuns off at a typical zeo voltage condition, esulting in the appeaance of a long collecto cuent tail. The esonant link IGBT S tuns off natually by commutation to its feewheeling diode D, hence no cuent tail appeas. Figue 5.17 shows the collecto-emitte voltage and the collecto cuent fo the uppe IGBT of the battey side convete, fo the esonant cycles shown in Figue 5.14 and Figue Note the diffeence in the cuent tail at tun-off of the convete IGBT, compaed to the esonant link IGBT, S, tun-off shown in Figue The ponounced collecto cuent tail appeaing at convete IGBT tunoff, gives a consideable contibution to the convete losses when the paallel quasi esonant DC link is used fo the battey chage. This is seen late when the efficiency is investigated. The eason why this cuent tail appeas fo this esonant link but not fo the passively clamped peviously investigated, is that fo the paallel quasi esonant cicuit, it is the tun-off of one IGBT of each half bidge that initiates the esonant link voltage amp up inteval. Thus, no convete IGBT intenal ecombination takes place pio to the amp up inteval. 18

137 5. Simulation v CE [V] i C [A] v CE [V] i C [A] t [µs] t [µs] Figue 5.17 Switching wavefoms fo the uppe IGBT of the battey side convete at ated powe, tun-on (left) and tun-off (ight). The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). In Figue 5.18, one of the line side phase cuents and the battey cuent, fo one peiod of the AC side fundamental, ae shown fo chaging at ated powe and battey voltage. i a, i batt [A] t [ms] Figue 5.18 Line cuent in one phase (black) and battey cuent (gey). Both cuents ae defined as positive going out of the convetes. Note the small amount of low ode hamonics appeaing in the cuents shown in Figue This is due to the fact that the switching instants commanded by the modulato ae only slightly delayed by the opeation of this quasi esonant DC link, due to the athe shot duation of the esonant cycle. Efficiency The passive component losses fo the battey chage using the paallel quasi esonant DC link ae calculated as descibed in Chapte 4. The instantaneous semiconducto losses ae diectly given by the simulation softwae used, and the aveage losses ae calculated by integation. The load condition consideed coesponds to battey chaging close to ated 19

138 5. Simulation powe. In the simulation the aveage powe fed to the batteies becomes 9.96 kw. The losses of the quasi esonant link ae listed in Table 5.1. Table 5.1 Losses of the paallel quasi esonant DC link. Component C e C L S S s D D s Losses (W) The total losses fo each of the blocks ae listed in Table Note that the output filtes dissipate moe than half the total losses. Table 5.13 Losses fo the entie battey chage at ated powe. Component/ Line side Battey side DC link Resonant Block Convete Filte Convete Filte capacito cicuit Losses (W) This gives a total efficiency of 93.5 %. The simulated efficiency fo the paallel quasi esonant DC link including both the convetes is equal to 97. %. 5.5 Simulation of the actively clamped quasi esonant DC link The simulation model of the actively clamped quasi esonant DC link used fo the battey chage consideed, is discussed and suitable passive component simulation model paamete values fo loss calculation ae given. Simulation esults veifying the design expessions ae shown and the efficiency is calculated. Figue 5.19 shows the QRDCL block fo simulation of the actively clamped quasi esonant DC link, used in the battey chage simulation model in Figue 5.1. L i o S D i L v link i C v C S c C C c D c V Cc C dc V dc Figue 5.19 The actively clamped quasi esonant DC link used in the simulation, including the DC link capacito. 13

139 5. Simulation Simulation model and paametes Fo the opeation of the actively clamped quasi esonant DC link, by means of simulation, the simila quantities as fo the paallel quasi esonant DC link have to be measued. In an implementation, the tip cuent level should not be calculated as being an IGBT collecto cuent due to pactical poblems. Instead, both the tip cuents used in the simulation ae expessed as esonant inducto cuents, i L. This implies that this cuent has to be measued and also that the esonant output cuent must be estimated fom the line and battey side cuents and modulato command signals, as discussed in Section 5.4. Howeve, this adds no futhe complexity to the esonant link contol, since this anyway has to be done fo pope selection of the instant to initiate the amp up inteval, i.e. the second tip cuent level and its cossing. The esonant link voltage v link has to be measued, since the convete half bidges should be shoted by applying appopiate gate signals to all the convete IGBTs when the zeo voltage inteval is enteed. The esonant link IGBT S should be tuned off when the zeo voltage inteval is enteed. The clamp capacito voltage V Cc is measued, since it has to be contolled to obtain the desied clamping voltage fo the actively clamped quasi esonant DC link. The esonant cicuit has thee passive component values to be selected, L, C and C c. The design expessions fo this cicuit detemined in Section 3.4, i.e. (3.4) and (3.44), gives appopiate values fo L and C. The clamp capacito value is selected fom simulations. The passive component values used in the simulations ae L C C c = µ H = 54. nf = 94. µ F (5.6) Note that the minimum cuent magins I m1 and I m, needed fo safe opeation, ae assumed to equal 5 A each in the calculation of the passive component values. These minimum cuent magins ae also used in the simulation model. The esonant inducto is designed accoding to Table

140 5. Simulation Table 5.14 Resonant link inducto specification used in the simulations. Inducto Coe A L (nh/n ) N (tuns) R Cu (mω) R th ( C/W) L T4-D The simulation model esonant capacito C actually consists of fou paallel connected capacitos, two 1 nf and two 15 nf, with loss paametes selected fom the Rifa PHE 48 seies, see Section 5.. The clamp capacito is modelled the same way as C e was fo the paallel quasi esonant DC link, i.e. as two paallel connected Ica MSR-D-47-45, see Section 5.4. The esonant link IGBTs, S c and S, shown in Figue 5.19, actually consist of thee paallel connected IGBTs of type IRGPH5K each. The diodes D c and D ae modelled by six discete, paallel connected diodes of type Hais MR115 each. Simulated wavefoms and losses Fo the battey chage utilising the actively clamped quasi esonant DC link, one peiod of the fundamental gid fequency is simulated in ode to calculate the aveage losses, as fo the peviously investigated quasi esonant links. Fist, the quasi esonant DC link quantities, i.e. voltages and cuents, of inteest ae investigated. Figue 5. shows the esonant link wavefoms at tun-on of the uppe IGBT of the battey side convete at ated cuent, i.e. maximum incease of the esonant link output cuent i o. In Figue 5. it is seen that the duation of the zeo voltage inteval is longe than was desied at the design stage. This is due to the fact that contol actions ae made to incease the clamp voltage. The clamp voltage is inceased by supplying excess enegy to the clamp capacito at the clamping inteval. To do this, the zeo voltage inteval is maintained somewhat longe than needed by means of shot tem opeation of the esonant cicuit. This means that excess enegy is stoed in the esonant inducto L duing the zeo voltage inteval. This enegy is then tansfeed to the clamp capacito C c at the clamping inteval. Howeve, this also means that a highe cuent than expected is supplied to the esonant link capacito C duing the amp up inteval, causing the esonant link voltage deivative to be highe than desied, which is also seen in Figue

141 5. Simulation Note that in both Figue 5. and Figue 5.1 the esonant link voltage deivative is not explicitly shown but instead the esonant capacito voltage v C deivative. This is done in ode to avoid showing the high deivatives, appeaing in the esonant link voltage v link at the stat of the enegy stoage inteval and at the end of the clamping inteval. These high voltage deivatives can not be contolled by pope selection of the esonant link passive components. v [V] link i, i [A] L C 5 dv C /dt [V/µs] t [µs] Figue 5. Resonant link wavefoms at an output cuent incease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v link (top, black) and the time deivative of the esonant capacito voltage v C (top, gey), and the esonant cuents, i L (bottom, black) and i C (bottom, gey). The coesponding wavefoms at ated esonant link output cuent decease, i.e. tun-off of the uppe battey side convete IGBT when chaging at ated powe, ae shown in Figue 5.1. The same poblems as seen in Figue 5. also occus hee. The duation of the zeo voltage inteval and the esonant link voltage ising edge deivative both exceeds thei desied values. The easons ae the same as discussed fo tun-on of the uppe battey side convete IGBT, even though the poo esult is not as obvious as in Figue 5.. One way to avoid the high esonant link voltage deivative, caused by clamp voltage contol action, is to include the boost cuent in the 133

142 5. Simulation selection of the passive components. In the design expessions given in Chapte 3, this is done by specifying the maximum boost cuent as a cuent magin and include it in the design. It is howeve impotant to only include this vaiable boost cuent when the voltage deivative is calculated and not fo the duation of the zeo voltage inteval. This is due to the fact that the boost cuent commanded by the clamp voltage contolle can be lowe than its maximum, thus giving a shote duation of the zeo voltage inteval than expected. v link [V] i L, i C [A] 5 dv /dt [V/µs] C t [µs] Figue 5.1 Resonant link wavefoms at an output cuent decease coesponding to the ated maximum value. The wavefoms shown ae esonant link voltage v link (top, black) and the time deivative of the esonant capacito voltage v C (top, gey), and the esonant cuents, i L (bottom, black) and i C (bottom, gey). The tun-off wavefoms fo the esonant cicuit IGBTs ae left out hee, since they ae simila to the ones discussed fo the paallel quasi esonant DC link cicuit. The clamp cicuit IGBT S c tun-off wavefom in essence esembles the one given fo S s in Figue 5.16, i.e. a collecto cuent tail bump appeas since the IGBT tuns off unde zeo voltage conditions. The esonant cicuit IGBT, S, tuns-off natually since the esonant inducto cuent i L commutates to the convete feewheeling diodes when the zeo voltage inteval is enteed. Hence, the tun-off wavefoms fo the IGBT denoted S fo the actively clamped quasi esonant cicuit, 134

143 5. Simulation closely esembles the tun-off wavefoms given in Figue 5.16 fo the paallel quasi esonant cicuit IGBT S. Figue 5. shows the collecto-emitte voltage and the collecto cuent fo the uppe IGBT of the battey side convete, fo the esonant cycles shown in Figue 5. and Figue 5.1. Note the convete IGBT collecto cuent tail at tun-off. This implies that also fo the battey chage equipped with the actively clamped quasi esonant DC link, the convete losses will be high compaed to the cases when the passively clamped quasi esonant DC links ae used. v CE [V] i C [A] v CE [V] i C [A] t [µs] t [µs] Figue 5. Switching wavefoms fo the uppe IGBT of the battey side convete at ated powe, tun-on (left) and tun-off (ight). The quantities shown ae the collecto-emitte voltage (black) and collecto cuent (gey). In Figue 5.3, one of the line side phase cuents and the battey cuent, fo one peiod of the AC side fundamental, ae shown fo chaging at ated powe and battey voltage. i a, i batt [A] t [ms] Figue 5.3 Line cuent in one phase (black) and battey cuent (gey). Both cuents ae defined as positive going out of the convetes. 135

144 5. Simulation Only a small amount of low ode hamonics appeas in the cuents shown in Figue 5.3, even though the actively clamped quasi esonant cicuit is not as fast as the paallel, peviously investigated. Efficiency As fo the othe quasi esonant DC links investigated, the losses fo a battey chage using the actively clamped esonant cicuit, ae calculated. The calculations ae based on simulation data fo one peiod of the fundamental fequency of the AC mains, to give the aveage losses. Also fo this chage the load condition consideed is battey chaging at ated powe. In this case the aveage powe fed to the batteies was 1.7 kw. The losses of the actively clamped quasi esonant DC link ae listed in Table Table 5.15 Losses of the actively clamped quasi esonant DC link. Component C c C L S S c D D c Losses (W) The total losses fo each of the blocks ae listed in Table Note that in this case the output filtes dissipates less than half the total losses. Table 5.16 Losses fo the battey chage at ated powe. Component/ Line side Battey side Block Convete Filte Convete Filte DC link capacito Resonant cicuit Losses (W) This gives a total efficiency equal to 91.9 %. The efficiency fo the passively clamped quasi esonant cicuit including the convete is equal to 95.7 %, accoding to the simulations. 5.6 Simulation conclusions One of the investigated quasi esonant DC link battey chages should be implemented fo futhe analysis. Also, a had switched battey chage should be implemented to compae the simulated efficiency with the measued. In this section the simulated losses and efficiency fo a 1 kw had switched battey chage is fist given, and then the choice of quasi esonant cicuit selected fo implementation is discussed. The actual design and implementation of both the had and soft switched battey chages ae pesented in Chapte

145 5. Simulation Losses and efficiency of the had switched battey chage The had switched battey chage is simulated unde the same conditions as the quasi esonant DC link chages ae, i.e. battey chaging at ated powe fo one peiod of the line side fundamental. The losses fo the had switched battey chage at a chaging powe of 1.44 kw, ae given in Table Table 5.17 Losses of the had switched battey chage at ated powe. Component/ Line side Battey side Block Convete Filte Convete Filte DC link capacito Snubbe capacitos Losses (W) The chaging powe and the losses listed above gives an oveall efficiency fo the battey chage of 93.8 %. The convete efficiency is 98.1 %. Note that fo the simulated had switched battey chage, the gate esisto values ae selected 1 times highe than fo the quasi esonant chages, to patly decease the maximum convete output voltage time deivative. Still, the maximum obtained deivative is as high as 1 V/µs, in the simulation model. The losses ae howeve only slightly affected by the high gate esisto values used in the simulation, which is pobably due to the fact that the dominating pat of the switching losses is due to IGBT collecto cuent tailing. Note that the IGBT collecto cuent tail is only slightly affected by the gate esisto value. Table 5.18 shows the simulated efficiency fo the diffeent battey chages investigated. Table 5.18 Simulated convete efficiency and total efficiency of the diffeent battey chages, opeating at ated powe. Battey chage Convete efficiency Total efficiency Passively clamped two switch quasi esonant DC link 97.5 % 93.5 % Passively clamped one switch quasi esonant DC link 97.7 % 94. % Paallel quasi esonant DC link 97. % 93.5 % Actively clamped quasi esonant DC link 95.7 % 91.9 % Had Switched 98.1 % 93.8 % 137

146 5. Simulation An impotant conclusion dawn fom the simulations of the diffeent battey chages, is that the maximum convete efficiency is obtained fo the had switched topology, which is shown in Table Howeve, esonant convetes ae in most cases used fo highe switching fequencies than the 4.95 khz used hee, which means that the convete switching losses fo the had switched chage would be highe in such a case. Still, seveal of the quasi esonant DC links investigated do not allow highe switching fequency, without compomising the maximum output voltage deivative, the duation of the zeo voltage inteval o the output cuent low ode hamonics. The esults of this chapte, by means of simulated efficiency, should be used caefully. This is due to the fact that the battey chages do not opeate at steady state conditions, in the simulations. This is clealy seen in the tables containing the losses of the diffeent battey chages. In fact, the DC link voltage dops a few volts fo all the cicuits duing the simulations, which is due to the fact that the integal pats of the cuent contolles, see Appendix B, do not settle fo such a shot simulation time. One way to cicumvent this poblem, is to use the calculated losses of a pevious simulation to calculate initial conditions fo the integal pats. Even though this method was used, it was not iteated the numbe of times needed fo the integal pats to settle, mainly due to the long simulation time equied. Howeve, a DC link capacito voltage decease of V coesponds to an aveage powe of less than W, fed fom the DC link capacitos to the est of the battey chage. This powe is fed fom the gid when steady state conditions ae established. This means that this powe should be fed though the line side filte and convete, which implies that the losses of these pats would incease. Howeve, the additional powe constitutes only a mino pat of the total powe, fed via the line side. Futhemoe, the battey chage and convete input powe ae calculated by adding the coesponding output powe and the losses. This implies that the esonant link powe losses ae not affected, at least not to a lage extent. Theefoe, the simulated efficiency is pobably close to the one obtained fo steady state conditions. Note that in the case of simulated convete efficiency it is only the line side convete losses that inceases, due to the additional powe. Still, it should be pointed out that the DC link voltage decease is not equal in the simulations of the diffeent battey chages, but it only coesponds to a few volts even in the wost case. Note that a simila compaison is made in [7]. In [7] the ated powe is 5 kw and the DC link voltage is 375 V. Theefoe, 6 V IGBTs ae used 138

147 5. Simulation in this case. In [7] the efficiency of the had switched battey chage becomes lowe than the efficiency of seveal of the quasi esonant DC link equipped ones, even though the same esonant cicuits as hee ae compaed. The eason fo this is that the had switched battey chage is equipped with capacitive tun-off snubbes connected acoss each tansisto, i.e. not had switched. As discussed in Section.1 the capacitive tun-off snubbe is not suitable in bidge applications since the IGBT collecto cuent becomes vey high at tun-on, which causes the low efficiency epoted in [7]. Actually, snubbes ae used also fo the had switched battey chage investigated hee. Howeve, in this case capacitive ovevoltage snubbes, connected acoss each half bidge, ae used. Such snubbes ae intended to educe the semiconducto ovevoltage stess, appeaing due to cicuit stay inductance. This kind of snubbe does not affect the semiconducto switching wavefoms. Selection of quasi esonant DC link fo implementation The passively clamped two switch quasi esonant DC link battey chage is selected fo implementation. The easons fo selecting this cicuit ae the quite high efficiency togethe with the uncomplicated contol needed fo implementation. Uncomplicated contol is impotant since seveal quasi esonant DC links elies upon high bandwidth measuements of esonant link voltage and esonant inducto cuents, which is had to achieve. Also, intenal time delay of the IGBT dives futhe complicates the contolle implementation. Anothe impotant eason fo selecting the passively clamped two switch quasi esonant DC link battey chage is that also a had switched vesion should be implemented. To cicumvent diffeences between individual semiconductos used, it is favouable if the vey same convete components can be used fo both chages implemented, by means of efficiency compaison. Howeve, thee ae also dawbacks associated with the passively clamped two switch quasi esonant DC link. The main poblems occus in the clamp cicuit, whee seveal diodes have to be seies connected and a tansfome with high magnetic coupling facto has to be designed. Anothe poblem is the lage amount of low ode hamonics contained in the output cuents, caused by the time delay intoduced by the long esonant cycle time fo this cicuit. 139

148

149 6 Implementation In this chapte, the implementation and evaluation of the passively clamped two switch quasi esonant DC link battey chage, ae pesented. The atings and switching fequency of the implemented battey chage ae the same as fo the ones investigated in Chapte 5. The implementation of the powe electonic main cicuit is pesented in steps discussing each component used. A lot of emphasis is put on minimising the effects due to non-ideal device behaviou. One section descibing the modulato used is also given. Finally, the quasi esonant DC link battey chage is tested and its efficiency compaed to a had switched countepat. To ovecome measuement deviations due to paamete vaiations both fo the semiconductos and the passive components, the quasi esonant battey chage is alteed to fom a had switched, instead of using two sepaate cicuits fo the compaison. 6.1 Powe electonic main cicuit The battey chage main cicuit is shown in Figue 6.1. The connection points fo the clamp tansfome, a and a, ae maked in Figue 6.1. To pefom measuements on the had switched battey chage, the clamp tansfome is disconnected at the connection points, a and a, which instead ae connected diectly to each othe. Note that the output filtes of the implemented battey chage ae puely inductive, i.e. LCL-filtes ae not used fo the evaluation. The eason fo not using LCL-filtes is discussed in the measuement section. The output filtes used in the battey chage implementation ae not designed especially fo the application, and thei loss chaacteistics ae unknown. Theefoe, loss measuements ae made both on the battey chage including filtes and on the battey chage itself. In ode to detemine to what extent the limited bandwidth of the powe mete used affects the measuements, it is impotant to include the passive filtes in the measuement of losses.

150 6. Implementation L 1 a a i a S 1 D 1 i 1 L 3 3 Φ V line L line L line L batt i batt L v C C i v D3 D 3 C dc V dc L line V batt D S i 3 Figue 6.1 The main cicuit of the implemented quasi esonant battey chage. To convet the chage to a had switched, the clamp tansfome is disconnected at the points a and a, and these points ae connected diectly to each othe. The DC link capacito actually consists of fou electolytic capacitos, two seies connected and two in paallel. Data on the DC link capacito paametes fo loss calculation ae not available. Neithe is the equivalent seies inductance, L ESL. The data available on the output filtes and the DC link capacito ae listed below. L L C line batt dc = mh = 1. 7 mh =. mf (6.1) To estimate the efficiency of the implemented battey chages, by means of simulation, the loss paametes used fo the output filtes and the DC link capacito ae the same as was given in Chapte 5. Convete semiconducto devices The convete semiconductos used in the simulations ae consideed not suitable fo the implementation. The main eason is that in the simulations seveal semiconductos ae connected in paallel to meet the constaint (.1), which complicates the design. Instead IGBT modules consisting of an entie half bidge, i.e. two IGBTs and two feewheeling diodes, ae used. The cuent atings of these modules ae selected in such a way that paalleling is not needed. By using modules, good mechanical and themal design ae also gained. The modules selected fo the battey chage convetes ae of the type SKM5GB13D manufactued by Semikon [68], which consists of 5 A, 1V devices. Howeve, at a silicon tempeatue of 15 C, which is a suitable opeating tempeatue, the ated cuent fo the module is 4 A. The IGBT module ated cuent is thus slightly highe than needed fo the line side convete of the battey chage, accoding to (.1). 14

151 6. Implementation Dive cicuits suitable fo the modules selected ae also manufactued by Semikon. Fo the battey chage the dive SKHI3/1 is chosen [68]. This is a 1 V dual dive which means that it actually consists of two dives, one fo the uppe and one fo the lowe IGBT of a half bidge. The dives ae equipped with intenal gate esistos, whose esistance only can be deceased. Howeve, the built in gate esisto has a esistance of Ω but fo the IGBT modules used, 7 Ω is ecommended [68]. Howeve, IGBT gate esistos of Ω ae used fo the implementation. In Chapte 4, the influence of the gate esisto value on the switching wavefoms is discussed. The dive cicuit SKHI3/1 intenally povides blanking time and is also equipped with an intelock function. The intelock function is in this application tuned-off. The logic contol signals fed to the dive povides the blanking time needed fo the had switched convetes. Quasi esonant DC link IGBTs Since the peak esonant inducto cuent is selected to equal the ated battey cuent, the same IGBT modules can be used fo the esonant link IGBTs S 1 and S and the diodes D 1 and D. Note that one module is used fo each IGBT and feewheeling diode combination, i.e. S 1 /D and S /D 1. Thus, one IGBT of each module must neve be tuned on. The dive SKHI3/1 is used also fo the esonant link IGBTs, with gate esistos of Ω. Clamp cicuit diodes The clamp cicuit diode D 3, must withstand a blocking voltage of at least six times the DC link voltage, which appeas acoss the diode duing the esonant link zeo voltage inteval. This means that the clamp cicuit diode should be selected to sustain a voltage of 45 V in this case. Consequently, seveal diodes have to be seies connected. Since the seies connected diodes ae not likely to exhibit the same popeties, an additional magin has to be adopted, by means of blocking voltage. Thus, an even moe consevative magin than the one used fo the othe semiconductos, i.e. (.1), must be used. In the implemented design, six 15 V diodes ae seies connected, implying a voltage magin of 1 %. Futhemoe, since the seies connected diodes do not have exactly the same chaacteistics, a voltage dividing netwok is adopted. The voltage dividing netwok used fo the implementation is shown in Figue

152 6. Implementation i 3 v D31 D 31 D 3 D 33 D 34 D 35 D 36 R s C p R s C p R s C p R s C p R s C p R s C p R m R p R p R p R p R p R p Figue 6. The six seies connected diodes fo ealising D 3 togethe with the voltage dividing netwok added. An opto-couple is used to detect clamp action. The paallel esistos, R p, ae used to divide the total blocking voltage among the seies connected diodes duing stationay blocking conditions. Othewise, diffeences in the evese leakage cuent chaacteistic fo the diodes can cause sevee evese voltage imbalance among the six diodes. The paallel capacitos, denoted C p, ae used to divide the total blocking voltage duing the tun-off tansients. This is needed due to the fact that the seies connected diodes possibly exhibits diffeent amounts of evese ecovey chage, Q, leading to the fact that one of the diodes will stat blocking befoe the othe. Thus, this diode is exposed to the total blocking voltage appeaing at the moment. In [63] selection of pope paallel esisto and capacito values is discussed. As seen in Figue 6., anothe esisto, R s, is connected in seies with each paallel capacito C p. This esisto is included in ode to dampen oscillations between C p and the stay inductance of the cicuit. In ode to select pope diodes fo the clamp cicuit, the effect of evese ecovey is investigated. Figue 6.3 shows an equivalent of the clamp cicuit with an equivalent paallel capacito added. Also the stay inductances of the cicuit ae included. i dc L 1 L 1λ i 1 L σ L dc L 3λ L 3 i 3 V dc C dc i C L C C v C I o D 3 C p,eq Figue 6.3 Clamp cicuit equivalent fo investigating influence of clamp diode evese ecovey and cicuit stay inductance. The equivalent paallel capacito, fo six seies connected diodes, is given by 144

153 6. Implementation C, = 1 C 6 peq p (6.) The idea of the following investigation, is to study the effect of the evese ecovey cuent of D 3. Assume that the investigation stats when the off esonance inteval is enteed, i.e. immediately afte the clamping inteval. Note that the stay inductances ae neglected in this investigation. The cuent though the equivalent paallel capacito is coupled to the clamping tansfome giving N 3 dvc i 3 = C peq, (6.3) N dt 1 whee N 1 and N 3 ae the winding tuns numbe of the clamping tansfome. The diffeential equation fo the cicuit in Figue 6.3, neglecting the stay inductances, is thus witten L 1 N 3 C + N1 C d vc, + vc = Vdc (6.4) dt peq The geneal solution to the diffeential equation is given by v ( t) = Acos ω ( t t ) + Bsin ω ( t t ) + V (6.5) C eq 4 eq 4 whee the chaacteistic angula fequency is given by dc ω eq = L1 C N N1 C peq, (6.6) It is assumed that the evese ecovey is extemely snappy, i.e. the diode cuent etuns to zeo, fom its negative peak value, abuptly. This means that the initial esonant link capacito cuent will be non zeo in this case. If the peak evese ecovey cuent is denoted I, the constants of the diffeential equation above, is given by A= ( K 1) Vdc 1 N B C N I C L 3 1 C N = = N ω eq 1 1 C p,eq N N 3 1 I (6.7) 145

154 6. Implementation This means that the minimum esonant link voltage obtained duing the off esonance inteval becomes vc,min = V A + B dc (6.8) Hence, the minimum esonant link voltage is lowe than calculated in Section 3.1. The poblem is that, as the off esonance inteval oscillation continues, the esonant link voltage will ente a clamping condition again, though opeating in the off esonance inteval. This occus since moe enegy than peviously assumed, is oscillating in the cicuit. As shown above, pope selection of the clamp cicuit diodes is an impotant issue, since even a low evese ecovey cuent affects the behaviou of the esonant cicuit to a lage extent. Theefoe, thee fast diode modules of type Semikon SKKD4F15 [68], consisting of two seies connected diodes each, is selected fo the implementation. The voltage dividing netwok components ae selected as R R C p s p = 1 kω = 1 Ω (6.9) = 1 nf Note that the voltage dividing capacitos in the clamp cicuit also affects the othe modes of opeation, since the total capacitance of the esonant cicuit is inceased. Consequently, the chaacteistic angula fequency decease. Clamp tansfome The clamp tansfome design is also an impotant issue. Fist, the impotance of keeping the stay inductances of the esonant cicuit at a minimum, whee the clamp tansfome leakage inductances take pat, is highlighted. This is done with aid of Figue 6.3. The citical instant to be investigated, is when the esonant cicuit taveses fom the amp up inteval to the clamping inteval. The esonant inducto cuent i 1, immediately pio to the clamping inteval, is expessed as i ( t ) = I o + i (6.1) whee i 1 coesponds to the excess enegy stoed in the clamping tansfome L 1 /L 3. Assuming that the stoed magnetic enegy does not change duing this shot inteval, the following elationships ae established 146

155 6. Implementation ic = i1 Io idc = i1 i3 N3 i1 Io + i3 = i N1 1 dic vc i1 = C d = d dt dt dt didc N1 vc = + C d 1 (6.11) dt N3 dt di3 N1 vc = C d dt N3 dt The following equations ae also valid V V dc dc didc di1 dic Ldc v1 ( L1λ + Lσ ) LC vc = dt dt dt didc di L v N 3 3 dc 1 L3λ = dt N dt 1 (6.1) whee L dc and L C ae the equivalent seies inductances of C dc and C, espectively. The leakage inductance of the clamp tansfome windings ae denoted L 1λ and L 3λ. L σ epesents the stay inductance not associated with a paticula component, i.e. the stay inductance of the supply ails etc. By combining the pevious expessions it is found that L stay C d v dt C 1 whee the total stay inductance, L stay, is witten L stay N1 + vc = + Vdc = KVdc (6.13) N 3 N1 N1 = + Ldc + L1 + L + LC + L3 N 1 λ σ λ (6.14) N 3 The chaacteistic angula fequency fo this cicuit is thus 3 ω stay = 1 L stay C (6.15) Since the initial capacito cuent equals i 1, the esonant link peak voltage becomes ˆv C i1 = KVdc + ω C stay (6.16) 147

156 6. Implementation Fom the deivation above, the impotance of keeping the stay inductance of the cicuit low becomes clea. Note that especially the DC link capacito equivalent seies inductance, denoted L dc in the deivation, affects the ove voltage expeienced. Howeve, this inductance is usually athe low, at least compaed to the leakage inductance of the clamp tansfome windings denoted L 1λ and L 3λ. In ode to minimise the clamp tansfome leakage inductance, a coaxial winding tansfome [9], [33] is adopted fo the passively clamped two switch quasi esonant DC link investigated in [7], [8] and [17]. By using a coaxial winding aangement, the leakage inductance becomes vey low and in [33] a magnetic coupling facto of.999 is obtained. Howeve, the coaxial winding tansfome has a lage dawback in the fact that it is complicated to manufactue a winding with seveal tuns. This means that designing a tansfome fo a cetain self inductance esults in the need of a coe having a lage coss sectional aea. In [8] and [9], seveal tooidal coes ae mounted along an U-shaped coaxial winding, to fom the tansfome. The pimay is the oute, hollow conducto, which in effect is wound less than one tun. The seconday conducto is thus inside the pimay, to fom a coaxial winding. Hee, a diffeent appoach is used fo the implementation of the clamp tansfome, since it should be designed fo a given pimay self inductance. The idea is to wind the pimay and seconday conductos in paallel paths, which is a well known method to obtain low leakage inductance [63]. In this case, the winding tuns atio should be 1:5 to give a clamp voltage % highe than the DC link voltage. Hence, a split winding technique has to be adopted. The split winding technique fo a coaxial tansfome is discussed in [8]. Fo the paallel pimay and seconday conductos discussed hee, the split winding technique means that the pimay and seconday should be wound togethe upon the tansfome coe. To accomplish this, N 3 /N 1 paallel conductos ae wound, with a tuns numbe equal to the desied numbe of pimay tuns, i.e. N 1 tuns in this case. Then, N 3 /N 1 conductos ae connected in paallel, to fom the pimay and N 3 /N 1 conductos ae connected in seies, to fom the seconday. Fo the clamp tansfome design, a band conducto is used fo the pimay and a cicula conducto fo the seconday, see Figue 6.4. The combination shown in Figue 6.4 is wound upon the ion coe, with the numbe of tuns equied fo the pimay. Then the five cicula conductos ae connected in seies to fom the seconday. This 148

157 6. Implementation coesponds to the split winding technique, since the band conducto can be egaded as consisting of five paallel conductos, which is also implied in Figue 6.4. a d-a a Figue 6.4 (a) The investigated winding aangement (a), with the band conducto equivalent fo the five paallel conductos indicated and (b), 1/ nd of the clamp tansfome coe with the windings. (b) Accoding to [1], the leakage inductance fo two paallel cicula conductos, is calculated fom (in the unit H/m) µ 1 = + accosh d π 4 a Lλ (6.17) The split winding technique gives the leakage inductance fo the pimay, L 1λ, and seconday, L 3λ, as L L 1λ 3λ N1 N L N µ 1 N = λ 1 = + d MLT accosh π 4 a N 3 1 N3 N L N µ 1 = λ 1 = + d MLT accosh π 4 a N MLT MLT (6.18) whee MLT is the mean length pe winding tun. The coe used fo the implemented clamp tansfome is an ion powde coe of type Micometals T65-8/9 [67]. The following specification fo the clamp tansfome is listed in Table 6.1. Table 6.1 Clamp tansfome specification. Inducto Coe A L (nh/n ) N (tuns) A Cu (mm ) L (µh) L 1 /L 3 T65-8/9 /11 1.5/. 96.8/4 In Figue 6.4, 1/ nd of the tansfome with the winding aangement used is shown. Howeve, note that additional insulation is used since (N 3-1)/N 3 of the total seconday voltage will appea between two adjacent winding tuns, in this case V=3 V. At such high voltage and 149

158 6. Implementation shot distance between the conductos, thee is a potential isk of patial dischage o coona effects appeaing, destoying the insulation. Hee, this is solved by using an insulating mica foil between the conductos, see Figue 6.5. Also the coe itself is coveed with mica foil, wound diectly upon it. a c d-a b-a c a b w b Figue 6.5 The winding aangement used fo the implemented clamp tansfome. Note the mica film (gey), which is used to eliminate insulation poblems by means of patial dischage. Resonant inducto The esonant inducto L used fo the implementation is designed almost accoding to the specification used in the simulation, i.e. Section 5.. Howeve, since the self inductance of the clamp tansfome pimay, i.e. L 1, is lowe in the implementation, the inductance of L is also loweed in such a way that the atio L /L 1 used in the simulation, is peseved also fo the implementation. The specification fo the esonant inducto L is given in Table 6.. Table 6. Resonant inducto specification. Inducto Coe A L (nh/n ) N (tuns) A Cu (mm ) L (µh) L T The inducto was intentionally designed to be wound with Litz wie [44], consisting of at least 1 paallel stands. Consequently, a coppe fill facto k Cu equal to. was assumed at the design stage. Howeve, it was not possible to manufactue the inducto with this type of conducto. Instead only two paallel wies wee used. This esults in the fact that the ion powde coe is somewhat ovesized due to the incease in coppe fill facto, by using fewe paallel conductos. Skin effect [44] of the coppe conducto cuent can also become a poblem since the AC esistance inceases with inceasing fequency. Resonant link capacito The esonant link capacito C, consists of six discete capacitos connected in paallel, thee 1 nf and thee 1 nf, to give a total capacitance of 66 nf. The eason fo not using thee paallel nf as in the simulation of 15

159 6. Implementation Section 5., is because the convete should also be opeated unde had switched conditions. It is advantageous to distibute the capacitance among the IGBT-modules since they seve as ovevoltage snubbes in the had switched case. The capacitos used fo the implemented quasi esonant DC link, to fom the esonant link capacito, ae fom the Rifa PHE 48 seies [64], see Section Quasi esonant DC link contolle In this section, the quasi esonant DC link contolle is descibed. The contolle is used to opeate the esonant link IGBTs in a pope way, and to delay the modulato contol signals fed to the convete dive cicuits until zeo link voltage is established. These tasks seems, at a fist glance, athe simple to implement. Howeve, seveal impotant issues have to be consideed. Fist of all, eo states of the esonant link must be detected. The ight contol actions must then be taken to solve the poblem. The second issue is that the IGBT dive cicuits have an intenal time delay of about 1 µs, which also has to be consideed. In ode to obtain safe opeation of the quasi esonant DC link, two signals ae measued. Fist, clamp action is detected by the opto-couple shown in Figue 6.. This is needed due to the fact that a esonant cycle must not be initiated befoe the pevious is completely finished. If the esonant link IGBTs, S 1 and S, ae tuned on when the cicuit is in the clamping state, too much esonant enegy is stoed in the cicuit. As a consequence, the peak esonant inducto cuent i will become consideably highe than expected, which means that S 1 and S expeience highe cuent stess than expected. The opto-couple in the cicuit fo clamp action detection is used to povide galvanic isolation between the main cicuit and the contol electonics. This is especially impotant in this case, because of the location in the clamp cicuit whee a voltage of seveal kv appeas. The opto-couple input is connected acoss a esisto, R m, equal to kω. Also the cuent i is measued fo opeational easons. As implied above, a high peak value of this cuent might esult in esonant link IGBT failue. Theefoe, the cuent i is measued in ode to detect eos esulting in a high peak value, occuing due to othe poblems than the peviously discussed. The cuent i is measued with a LEM cuent tansduce of type LA5P, which has a ated cuent of 5 A, but can measue cuents up to 7 A. The main advantages gained by using a LEM cuent tansduce ae the high bandwidth and galvanic isolation. 151

160 6. Implementation The need fo galvanic isolation is discussed above. A high bandwidth is not necessay fo contol of the quasi esonant cicuit, since the measued cuent is only compaed to a pe-set value to detect ove cuent. Howeve, to analyse the cicuit, the cuent should be measued anyway and theefoe the high bandwidth is favouable. The state machine fo esonant link contol is shown in Figue 6.6. The esonant link contolle is implemented in a pogammable logic device, PLD, which in fact consists of two PALV1 integated cicuits. One of these integated cicuits is used to implement an asynchonous state machine which keeps tack of the esonant cycle, see Figue 6.6. In the othe integated cicuit, a time function to contol the duation of each inteval is implemented. 1xxx 1 xxxx 1xx1x 1xx1x xxxx 11xx 1xx1x xxx 1xxx1 xxxx 1x1x xxxx xxx1x xxxx 1xxx 1xxx 1xx1x 1xxx x11x 1xxx xxxx 1xx1x xxxx 111 1x1x 1xxx Figue 6.6 State gaph showing the implemented quasi esonant DC link contolle. The state machine is implemented in PAL cicuits. In Figue 6.6, the input sequences esulting in the state tansitions ae shown next to each gaph symbolising the possible tansitions. The input sequence is fomed by the following digital signals Input_sequence = [Enable,Soft_stat,Clamp,Time,Time_clamp] The input signal Enable is set as long as no eo occus, i.e. as long as ove cuent is not detected. Soft_stat is set when the caie wave modulato commands a change of any of the convete switch states. This 15

161 6. Implementation is implemented as an exclusive o function between the actual and commanded switch state fo the switch states of each convete half bidge. The Clamp signal is set duing clamp action. Note that the optocouple shown in Figue 6. is actually inveting, which means that the signal Clamp is diectly given. The Time and Time_clamp signals ae intended fo synchonisation of the state machine. The states shown in Figue 6.6, coespond to the diffeent modes of opeation of the quasi esonant cicuit. As seen thee ae eight logic states whee two of them ae needed due to the IGBT dive cicuit delay. These two states ae efeed to as intemediate o tansition states. The states ae descibed in Table 6.3. Table 6.3 Desciption of the states of the quasi esonant contolle and modulato. State Desciption Idle condition, coesponds to off esonance 1 Ramp down. Resonant link IGBTs tuned on. 11 Ramp down intemediate state. The new switch state is applied to the dives. 111 Zeo voltage inteval. 11 Zeo voltage intemediate state. The esonant link dive contol signal is set low. 1 Resonant link voltage amp up inteval. 11 Clamping inteval. 1 Clamping intemediate inteval needed to obtain a hazad fee ealisation. As seen in Figue 6.6, the Time signal is vey impotant fo the contolle opeation. Note that fo each state whose tansitions ae tiggeed by the Time signal, the logic state is maintained fo a cetain time set fo the paticula state. Fo each such state, the time set should coespond to the duation of the esonant link mode in question. Theefoe, the times set have to be tuned, even though the simulated wavefoms gives the appoximate duation of each inteval. Note that since the Time signal is involved in almost all the state tansitions of the entie quasi esonant modulato and contolle, the state machine might as well be implemented as a synchonous state machine. Howeve, the PALV1 integated cicuits only have one clock signal, which is used to update the convete switch state, i.e. used as a clock signal fed to the latches needed to delay the dive cicuit input signals to wait fo the zeo voltage inteval. This clock o update signal is tigged duing the esonant link voltage amp down inteval, as soon as the amp down intemediate state is enteed. 153

162 6. Implementation The logic signal contolling the esonant link IGBT dives, is simply the last bit of the thee bit patten used to symbolise the logic states. 6.3 Measuements In this section the measued esults ae pesented and compaed to the simulated. Wavefoms of the quasi esonant DC link quantities ae shown, and discussed. The convete efficiency is measued fo both the quasi esonant and the had switched battey chages, and compaed to simulation esults. The tests ae made at a lowe convete DC link voltage than designed fo, due to ovevoltage poblems aising fom the stay inductance of the powe electonic main cicuit. The DC link voltage used fo the measuements theefoe equals 65 V. This means that the ated maximum cuent step which the quasi esonant DC link is designed fo, is loweed by the atio (65/75), i.e. to appoximately 3.1 A. Consequently, the ated battey cuent is deceased to the same level. In effect, the ated output powe of the battey chage is deceased by the atio (65/75), to become 7.5 kw. The lage eduction in output powe is due to the fact that the ated battey voltage equals half the DC link voltage. This is of mino impotance since such a high DC voltage is not available, at least not fo the cuent level equied, in the laboatoy. Theefoe, the efficiency measuements ae pefomed at ated battey side output cuent and a DC voltage of 4 V. Fo pactical easons, the DC voltage is geneated by a otating convete instead of electochemical batteies. Wavefoms The esonant link wavefoms shown in this section ae measued with a Tektonix TDS 64A fou channel digitising oscilloscope in all cases but one, which will be pointed out. The esonant cuents i 1 and i 3 ae measued by a LEM RR333-SD Rogowski cuent tansduce, whose output amplifie has a quite naow bandwidth which is seen in the measued signals, late on. Also note that a Rogowski cuent tansduce can not measue DC cuents, which means that no attention should be paid to the DC level of the cuents i 1 and i 3 shown in the figues of this section. In the fist pat of this section, the attention is focused on test of the esonant link opeation and paamete estimation. The measuements 154

163 6. Implementation shown at this stage ae made at a DC link voltage close to 375 V and at idle conditions with the battey chage output disconnected. In Figue 6.7, fist a esonant cycle is shown and then an off esonance inteval of long duation follows. v C, V dc [V] 4 i 1, i [A] 1 Figue t [µs] Off esonance oscillation at educed DC link voltage. The wavefoms shown ae v C (uppe, black), V dc (uppe, gey), i 1 (lowe, black) and i (lowe, gey). Duing off esonance opeation, the esonant link voltage is still oscillating due to esonance between L 1 and C, which is discussed in Chapte 3. Note the magnitude of the oscillating voltage which is between.8 and 1. times the DC link voltage, which also is concluded fom Chapte 3. Also note the inging seen in both the esonant link voltage v C and the esonant cuent i, when the esonant link entes the clamping inteval, in Figue 6.7. In Figue 6.8, the clamp cicuit cuent i 3 and the fowad voltage v D31 acoss one of the six clamp cicuit diodes, see Figue 6., ae shown. Fo convenience, also the esonant link voltage is shown. The poo bandwidth of the Rogowski cuent tansduce is clealy seen in Figue 6.8. Fom Figue 6.8, it is also clea that the Rogowski cuent tansduce can not epoduce the accuate DC level of the measued cuent. A Rogowski coil can not be used to measue a DC cuent, since it in fact is equivalent to an ai wound tansfome. 155

164 6. Implementation v C [V] 4 v D31 [V] i 3 [A] - -1 Figue t [µs] Clamp cicuit wavefoms. The uppe pat shows the esonant link voltage. The lowe pat shows the diode fowad voltage, v D31, of one of the six seies connected clamp cicuit diodes (black) and the clamp tansfome seconday cuent i 3 (gey). Since the cuent is measued with a Rogowski cuent tansduce, the DC level is not accuately shown. The esults shown in Figue 6.7 and Figue 6.8 ae used to estimate the esonant cicuit actual passive component values by means of inductance and capacitance. The time deivative of i 3 in Figue 6.8, togethe with the measued DC link voltage gives the self inductance of the clamp tansfome seconday, i.e. L 3. The esonant link voltage duing the clamping inteval and the DC link voltage gives the clamping facto K, which means that also L 1 is estimated. Then the off esonance oscillation peiod time is measued, which togethe with L 1 gives the total equivalent capacitance of the cicuit. The passive component value which is hadest to estimate is definitely L. Hee, L is estimated fom the second esonant cycle shown in Figue 6.8, by measuing the time to complete the esonant link voltage amp down inteval. Howeve, as seen in Figue 6.8, the esonant cicuit is not stated at est, implying that the actual initial conditions must be used instead of the ones deived fo this mode in Chapte 3. On the othe hand, this is not a sevee poblem, since the cycle stats close the esonant link voltage minimum fo the off esonance inteval. Thus, the esonant capacito cuent i C is egaded as being equal to zeo. By iteating equation (3.5) with these initial conditions, the inductance of L is estimated. 156

165 6. Implementation Accoding to the measuements discussed above, the following passive component values ae estimated L1 = µ H L = µ H L3 = 3. mh C N N C + ( ) = 3 1 p,eq 11 nf (6.19) Also the oscillation peiod time at the stat of the clamping inteval, shown in the esonant link voltage measuement of Figue 6.8, is measued. This oscillation time togethe with the passive component values peviously calculated, gives the total stay inductance L stay accoding to equation (6.15). This gives L stay = 111. µ H (6.) assuming that the equivalent seies inductance of the DC link capacito L dc equals 3 nh and that all othe stay inductances equals zeo except the clamp tansfome leakage inductances. If the latte ae consideed being equal seen fom the pimay o seconday it is found that L 1λ = 533 nh (6.1) This coesponds to a magnetic coupling facto equal to.995, which is faily high. Howeve, it is not high enough fo the application which is eflected in the fact that the quasi esonant battey chage is opeated at a maximum DC link voltage of 65 V, wheeas it was designed fo 75 V. Anothe inteesting featue investigated at low DC link voltage is the effect of clamp cicuit diode evese ecovey. The faily shallow slope of i 3 duing the clamping inteval, indicates that the evese ecovey cuent of the clamp cicuit diodes is likely to be low even if ectifie diodes ae used. Theefoe, six ectifie diodes of type Semikon SKKD46/16 [68] wee tested in the clamp cicuit. The measued esonant link voltage fo this case is shown in Figue 6.9. Note that this measuement is made with a diffeent oscilloscope, Philips PM 3384A, which has one fouth of the bandwidth of the oscilloscope used fo the est of the measuements. Although, the time deivative of the clamp cicuit cuent i 3 is low, the evese ecovey poblem discussed peviously in this chapte shows up. Note that clamping occus also in the off esonance inteval. 157

166 6. Implementation v C [V] 4 Figue t [µs] Resonant link voltage, when ectifie diodes ae used in the clamp cicuit. Note the lage magnitude of the off esonance oscillation and the fact that clamp action occus duing this inteval. By use of equation (6.7), it is found that the evese ecovey cuent I is equal to.75 A fo the case shown in Figue 6.9. Since the esonant cicuit behaviou shown in Figue 6.9 is not acceptable, the fast diode SKKD4F15 is used fo the clamp cicuit instead of the ectifie diode. One impotant conclusion to be dawn fom the measuements above and the discussion peviously in this chapte, is that the voltage shaing capacitos needed fo ealisation of the clamp cicuit diode, D 3, do affect the esonant link wavefoms. This is eflected in the fact that the duation of both the esonant link amp down and amp up inteval becomes longe than fo the case simulated in Chapte 5. This alone inceases the total cycle time. Moeove, the duation of the clamping inteval also becomes longe due to the fact that the voltage time aeas of these two intevals togethe with the zeo voltage inteval should equal the one of the clamping inteval, on the aveage [7]. The incease of the total cycle time esults in the fact that the switching instants fo the implemented battey chage ae futhe delayed. Thee ae also advantages gained by the inceased equivalent capacitance. The esonant link voltage deivative becomes lowe than expected which is advantageous in itself. Also, the need fo accuate timing becomes less ponounced due to the fact that the voltage is low fo a longe time since the esonant link voltage slopes ae moe shallow. Note that the ovevoltage due to cicuit stay inductance is not affected by the additional capacitance, since C p,eq is shoted by D 3 duing the clamping inteval. The est of the measuements ae made at a DC link voltage level of 65 V. The battey side output cuent efeence value is equal to 3 A, unless othewise specified. In Figue 6.1, one esonant cycle fo the case when clamping do not occu is shown. 158

167 6. Implementation v C, V dc [V] i 1, i [A] t [µs] Figue 6.1 Resonant link wavefoms fo one cycle in the case when clamping do not occu. The uppe pat shows esonant link voltage v C (black) and the DC link voltage V dc (gey). In the lowe pat, the esonant cuents i 1 (black) and i (gey), ae shown. In Figue 6.1, the uppe battey side convete IGBT is tuned on at ated cuent (fo the DC link voltage used). In Figue 6.11 both positive and negative esonant DC link output cuent steps ae shown. Note that the cuent steps fo two of the esonant cycles shown in Figue 6.11, ae lage than the ated ones. These lage output cuent changes occus due to the fact that seveal half bidges ae switched duing the vey same esonant cycle. The passive component values ae selected based on a esonant DC link output cuent change equal to the ated battey side convete output cuent, accoding to Section 3.1. Thee it is also stated that fo a esonant link output cuent incease lage than the ated, the esonant link voltage will stat to decease when i has deceased to zeo duing the esonant link voltage amp up inteval. This occus due to the fact that i 1 has not eached the level coesponding to the new convete switch state. Howeve, this is not seen in Figue 6.11, although the positive output cuent step of the fist esonant cycle shown is about 3 A. The eason why this does not occu, is due to the time contol used fo the esonant cicuit. 159

168 6. Implementation The esonant link IGBTs ae kept on fo a constant time, and the length of the amp down inteval used in the contolle must cove the wost case. This means that in some cases the zeo esonant link voltage is maintained fo longe than 1 µs which is used in the selection of the esonant link passive components. The longe duation of the zeo voltage inteval thus implies that moe enegy than expected is stoed in the cicuit when the clamping inteval is enteed. v C, V dc [V] i, i [A] t [µs] Figue 6.11 Resonant link wavefoms fo lage positive and negative cuent steps. Note that the output cuent decease duing the last esonant cycle is lage than the ated maximum. The uppe pat shows esonant link voltage v C (black) and the DC link voltage V dc (gey). In the lowe pat, the esonant cuents i 1 (black) and i (gey), ae shown. In Figue 6.1, the esonant link wavefoms ae shown fo a time inteval coesponding to one peiod of the modulation caie. As seen in Figue 6.11 and Figue 6.1, the esonant inducto cuent i has a highe peak magnitude than expected fom the design expession. The high peak value of i esults fom the incease of the equivalent esonant link capacito due to the capacitive voltage dividing netwok used in the clamp cicuit. Also, note that the peak value of i is dependent on the level of the esonant link voltage v C and the capacito cuent i C, at the stat of the esonant cycle. 16

169 6. Implementation v C, V dc [V] i 1, i [A] t [µs] Figue 6.1 Resonant link wavefoms fo a time inteval coesponding to the modulation caie time peiod. This means that ideally eight distinct esonant cycles should take place but in the case shown seveal switchings ae made duing some of the esonant cycles. The uppe pat shows esonant link voltage v C (black) and the DC link voltage V dc (gey). In the lowe pat, the esonant cuents i 1 (black) and i (gey), ae shown. Figue 6.1 shows the peviously discussed poblem associated with a too high amount of esonant enegy stoed when the clamping inteval is enteed. This both gives a highe ove voltage due to the stay inductance of the cicuit accoding to (6.16) and a longe duation of the clamping inteval accoding to (3.38). In Figue 6.1, only five esonant cycles take place, wheeas ideally eight should be pefomed. This implies that moe than one of the fou convete half bidges ae switched simultaneously fo some of the esonant cycles. Duing a clamping inteval, seveal switching tansitions might be held to await the next zeo voltage inteval. Theefoe, the modulato commands ae delayed a vaying time, depending on the duation of the clamping inteval. 161

170 6. Implementation The vaying delay time, imposed on the modulato command signals, esults in low ode hamonics appeaing in the output cuents, see Figue i a, i batt [A] t [ms] Figue 6.13 One of the line side phase cuents (black) and the battey cuent (gey), in the case of puely inductive output filtes at ated cuent when the DC link voltage equals 65 V. In Figue 6.13 the input cuent fo one of the AC side phases and the battey side output cuent, in the case of puely inductive output filtes, ae shown. Though pesent, the low ode hamonics ae not such a lage poblem in this case. In Figue 6.14, one of the AC side input cuents ae shown fo the oute inducto in the case of a LCL-filte at idle conditions with the battey side disconnected. As shown, a high content of low ode hamonics, appeas. The high hamonic content esults fom the fact that the impedance of the LCL-filte is consideably lowe than fo the L- filte, since the filtes ae designed to have the same attenuation at switching fequency. The esult shown in Figue 6.14 is of couse not acceptable, and theefoe L-filtes ae used fo all the measuements. i a [A] t [ms] Figue 6.14 One of the line side phase cuents in the case of LCL-filte, at idle conditions. Note the magnitude of the low ode hamonics. The high hamonic content is due to modulation eos esulting fom the fact that the convete contol signals ae delayed by the esonant link opeation.

171 6. Implementation Efficiency In ode to measue the losses, a powe mete is connected to the test setup. To measue the output powe fom a voltage souce powe convete is a complicated task, due to the switched natue of the output voltages, which makes high bandwidth measuements necessay. Theefoe, a fou channel Noma D 61 wide band powe analyse is used fo the measuements, which has a bandwidth of 4 khz. Howeve, an even highe bandwidth is desiable fo the output voltage deivatives appeaing in this case. To veify the convete input and output powe measuements, the powe mete is also connected outside the filtes to measue the total powe losses of the battey chage. The esult of these measuements is shown in Table 6.4. Table 6.4 Measued battey chage efficiency. Battey chage Without output filte losses Including output filte losses P in [W] P out [W] Efficiency P in [W] P out [W] Efficiency Had switched % % Quasi esonant % % A seies of measuements ae made on each chage in Table 6.4. The vaiations in efficiency between individual measuements ae appoximately ±.5 % to the aveage efficiency. The esults shown in Table 6.4 ae individual measuements close to the aveage of the seies, fo each case. Note that the vaiation of ±.5 % in addition to the bandwidth limitations of the powe mete, indicates that the efficiency only can be measued with two significant numbes. As seen in Table 6.4, the efficiency of the had switched battey chage seems to be appoximately 3 pecent units highe than the quasi esonant battey chage efficiency. The inductive filtes ae esponsible of deceasing the efficiency by 4 pecent units. To compae the measued esults with simulations, models have to be developed fo the semiconducto devices used in the implementation. The simulation softwae used, SABER, suppots chaacteisation of semiconductos based on vendo data sheets. Howeve, the behavioual models obtained ae not as accuate as the physical models used in the simulations of Chapte 5. The simulated esults, at a load condition coesponding to the measuements, ae shown in Table

172 6. Implementation Table 6.5 Simulated battey chage efficiency. Battey chage Without output filte losses Including output filte losses P in [W] P out [W] Efficiency P in [W] P out [W] Efficiency Had switched % % Quasi esonant % % In Table 6.5, only the leftmost pat is of inteest since the inductive filtes used in the laboatoy set-up is not the same as the simulated. In fact, fo the measuements the filte inductos ae wound on.3 mm laminated coes, wheeas in the simulation ion powde coes ae consideed. The eason fo not simulating the inductos used in the test set-up, is that the only data available is thei inductance. The simulated convete efficiency fo the had switched battey chage is consideably lowe than the measued. Howeve, the efficiency of the battey chage equipped with the quasi esonant DC link shows good ageement between measuements and simulations. The eason fo this is the poo semiconducto models used. Especially the switching tansients ae difficult to model coectly with a behavioual model, since they depend on a lot of factos. Fo example, both tun-on and tun-off enegy dissipation ae junction tempeatue dependent but the model used do not use tempeatue as an input. Theefoe, the simulation model must be chaacteised fo the coect opeating tempeatue to give the coect tun-on and tun-off enegies. The data sheets fo the semiconductos used, specifies these enegies only at a junction tempeatue of 15 C, wheeas the heat sink used fo the implemented battey chage was kept close to oom tempeatue, i.e. 5 C, implying that the junction tempeatue is consideably lowe than 15 C. The on-state, o conduction, losses on the othe hand ae not as tempeatue dependent as the switching losses. The losses of the had switched convete oiginates fom both switching tansients and cuent conduction. The conduction losses ae almost tempeatue independent but the switching losses inceases with inceasing tempeatue. Since the actual junction tempeatue pobably is lowe than 15 C, which the simulation models ae based on, the losses ae ove estimated. Fo the quasi esonant convete implemented, the conduction losses ae dominating, see Section 5.. Since these ae not tempeatue dependent, at the same extent as the switching losses, the simulated and measued convete efficiencies show bette ageement in this case. 164

173 7 Conclusions Quasi esonant DC link convetes fo a battey chage application ae investigated in this thesis. The main topic investigated, egads passive component selection to meet cetain pefomance citeia. Fou quasi esonant DC links ae designed and then simulated. One of the quasi esonant DC links is implemented in the battey chage application consideed, fo futhe investigation. This chapte concludes the esults obtained, by means of simulations and measuements. Also some topics fo futue wok on esonant convetes ae given. 7.1 Results The design expessions deived in Chapte 3, ae used to detemine suitable passive component values to meet cetain pefomance citeia. The pefomance citeia selected fo the investigation ae the maximum voltage deivative and the maximum duation of the zeo voltage inteval. Howeve, the most impotant issue coveed by the developed design expessions is to guaantee the opeation of the quasi esonant DC link at the wost case load conditions. In Chapte 5, the fou diffeent quasi esonant DC links investigated ae simulated. To give a fai compaison, the simulated quasi esonant DC links ae designed to meet the same maximum voltage deivative and maximum duation of the zeo voltage inteval. The simulations shows good ageement with the expessions deived in Chapte 3, by means of design citeia. The enegy efficiencies ae calculated based on the simulations. Fom these calculations it is found that the output filtes dissipate appoximately half the total losses of the battey chage. Also, it is found that the quasi esonant battey chages do not have lowe losses than the had switched. One of the quasi esonant DC link battey chages investigated, is designed and built fo 1 kw nominal powe. Impotant aspects egading the implementation ae discussed in Chapte 6. The esonant link wavefoms ae shown and discussed. Also, the losses of the entie battey

174 7. Conclusions chage and the quasi esonant DC link convete losses ae measued. The efficiency of a had switched battey chage is also measued fo compaison. Both the quasi esonant and the had switched battey chages ae simulated with semiconducto models based on data sheet infomation. The simulated and measued efficiency do not show full ageement and the easons fo this ae discussed. Both simulations and measuements indicate that the efficiency of the battey chage do not incease by the use of a quasi esonant DC link compaed to the had switched case. The main eason is that the switching fequency is only 5 khz fo the investigated battey chage. At such a low switching fequency, the efficiency is aleady high fo a had switched convete. In ode to fully utilise esonant convete technology the switching fequency should be highe than it is in this study. Howeve, it is also seen fom both simulations and measuements that seveal of the investigated quasi esonant DC links ae not suitable fo opeation at a high switching fequency. Aleady fo the low switching fequency used, the switching instants commanded by the modulato ae seveely delayed esulting in low ode hamonics appeaing in the convete output cuents. To patly ovecome this poblem, the estiction on the convete output voltage deivative can be loosen o the clamping facto can be somewhat inceased. Howeve, both these actions incease the semiconducto stess. 7. Futue wok Fo futhe investigations of quasi esonant DC link convetes two topics ae of paticula inteest, modulation stategies and semiconductos developed fo soft switching applications. Thee is a lot of wok done and ongoing, on these topics. Fo example, fo two of the cicuits investigated hee, by means of passive component selection, thee ae publications on modulation issues [17], [4]. In [6] semiconductos suitable fo soft switching is, to some extent, discussed. The wok pesented in [54] closely elates to Chapte 3 and Chapte 5. In [54], the esonant link voltage deivative of the quasi esonant DC link convete pesented in [11] and [31], is vaied to minimise the losses. Still, the esults obtained by such investigations ae dependent on the type of semiconductos used. 166

175 Refeences [1] S.G. Abeyatne, M.T. Aydemi, T.A. Lipo, Y. Muai and M. Yoshida, Cuent Clamped, PWM, Quasi-Resonant, DC Link Seies Resonant Convete, IEEE-IAS Conf. Rec., Denve, USA, Oct. 1994, pp [] V.G. Agelidis, P.D. Ziogas and G. Joos, An Optimum Modulation Stategy fo A Novel Notch Commutated 3-Φ PWM Invete, IEEE Tans. Ind. Applicat., vol. 3, no. 1, pp. 5-61, Jan./Feb [3] M. Bojup, P. Kalsson, M. Alaküla and B. Simonsson, A Dual Pupose Battey Chage fo Electic Vehicles, IEEE-PESC Conf. Rec., Fukuoka, Japan, May 1998, vol. 1, pp [4] M. Bojup, Advanced Contol of Active Filtes in a Battey Chage Application, Licentiate s Thesis, Depatment of Industial Electical Engineeing and Automation, Lund Institute of Technology, Lund, Sweden, Nov [5] B.K. Bose, Recent Advances in Powe Electonics, IEEE Tans. Powe Electon., vol. 7, no. 1, pp. -16, Jan [6] A. Calsson, The back-to-back convete; contol and design, Licentiate s Thesis, Depatment of Industial Electical Engineeing and Automation, Lund Institute of Technology, Lund, Sweden, May [7] S. Chen and T.A. Lipo, A Passively Clamped Quasi Resonant DC Link Invete, IEEE-IAS Conf. Rec., Denve, USA, Oct. 1994, pp [8] S. Chen, B.J.C. Filho and T.A. Lipo, Design and Implementation of a Passively Clamped Quasi Resonant DC Link Invete, IEEE- IAS Conf. Rec., Olando, USA, Oct. 1995, pp

176 Refeences [9] S. Chen and T.A. Lipo, A Novel Soft-Switched PWM Invete fo AC Moto Dives, IEEE Tans. Powe Electon., vol. 11, no. 4, pp , July [1] D.K. Cheng, Field and Wave Electomagnetics, nd ed., Addison-Wesley, Reading, USA, [11] J.W. Choi and S.K. Sul, Resonant Link Bidiectional Powe Convete: Pat I - Resonant Cicuit, IEEE Tans. Powe Electon., vol. 1, no. 4, pp , July [1] T. Citko, M. Dubowski and A. Sikoski, AC/DC/AC Quasi- Resonant Tansisto s Convete fo AC Dive Application, EPE 95 Conf. Rec., Sevilla, Spain, Sept. 1995, vol., pp [13] D.M. Divan, The Resonant DC Link Convete - A New Concept in Static Powe Convesion, IEEE-IAS Conf. Rec., Denve, USA, Septembe 1986, pp [14] D.M. Divan and G. Skibinski, Zeo Switching Loss Invetes fo High Powe Applications, IEEE-IAS Conf. Rec., Atlanta, USA, Octobe 1987, pp [15] D.M. Divan, L. Malesani, P. Tenti and V. Toigo, A Synchonized Resonant DC Link Convete fo Soft-Switched PWM, IEEE Tans. Ind. Applicat., vol. 9, no. 5, pp , Sept./Oct [16] D.M. Divan, Low-stess Switching fo Efficiency, IEEE Spectum, Decembe 1996, pp [17] B.J.C. Filho and T.A. Lipo, Space-Vecto Analysis and Modulation Issues of Passively Clamped Quasi-Resonant Invetes, IEEE Tans. Ind. Applicat., vol. 34, no. 4, pp , Jul./Aug [18] S.J. Finney, T.C. Geen and B.W. Williams, Spectal Chaacteistics of Resonant-Link Invetes IEEE Tans. Powe Electon., vol. 8, no. 4, pp , Oct [19] J. He and N. Mohan, Paallel Resonant DC Link Cicuit - A Novel Zeo Switching Loss Topology with Minimum Voltage Stesses, IEEE Tans. Powe Electon., vol. 6, no. 4, pp , Oct

177 Refeences [] J. He, N. Mohan and B. Wold, Zeo-Voltage-Switching PWM Invete fo High-Fequency DC-AC Powe Convesion, IEEE Tans. Ind. Applicat., vol. 9, no. 5, pp , Sept./Oct [1] M. Hemmingsson, A Poweflow Contol Stategy to Minimize Enegy Losses in Hybid Electic Vehicles, Licentiate s Thesis, Depatment of Industial Electical Engineeing and Automation, Lund Institute of Technology, Lund, Sweden, Jan [] K. Heumann, Ch. Kelle and R. Somme IGBT Devices in a Voltage Mode Resonant DC Link Invete, EPE 91 Conf. Rec., Fienze, Italy, Sept. 1991, vol. 1, pp [3] J. Holtz, Pulsewidth Modulation fo Electonic Powe Convesion, Poc. of the IEEE, vol. 8, no. 8, pp , Aug [4] G. Hua and F.C. Lee, An Oveview of Soft-Switching Techniques fo PWM Convetes, EPE Jounal, vol. 3, no. 1, pp. 39-5, Ma [5] B. Jayant Baliga, Moden Powe Devices, Wiley, New Yok, USA, [6] C.M. Johnson and V. Picket, Thee-Phase Soft-Switching Voltage Souce Convetes fo Moto Dives. Pat : Fundamental Limitations and Citical Assessment, IEE Poc.-Elect. Powe Appl., vol. 146, no., pp , Ma [7] P. Kalsson, M. Bojup, M. Alaküla and L. Getma, Efficiency of Off-Boad, High Powe, Electic Vehicle Battey Chages with Active Powe Line Conditioning Capabilities, EPE 97 Conf. Rec., Tondheim, Noway, Septembe 1997, vol. 4, pp [8] M.K. Kazimieczuk and D. Czakowski, Resonant Powe Convetes, Wiley, New Yok, USA, [9] M.H. Khealuwala, D.W. Novotny and D.M. Divan, Coaxially Wound Tansfomes fo High-Powe High-Fequency Applications, IEEE Tans. Powe Electon., vol. 7, no. 1, pp. 54-6, Jan

178 Refeences [3] M.H. Khealuwala, R.W. Gascoigne, D.M. Divan and E.D. Baumann, Pefomance Chaacteization of a High-Powe Dual Active Bidge dc-to-dc Convete, IEEE Tans. Ind. Applicat., vol. 8, no. 6, pp , Nov./Dec [31] J.S. Kim and S.K. Sul, Resonant Link Bidiectional Powe Convete: Pat II - Application to Bidiectional AC Moto Dive Without Electolytic Capacito, IEEE Tans. Powe Electon., vol. 1, no. 4, pp , July [3] J.B. Klaassens, M.P.M. van Wesenbeeck and P. Baue Softswitching Powe Convesion, EPE Jounal, vol. 3, no. 3, pp , Septembe [33] K.W. Klontz, D.M. Divan and D.W. Novotny, An Actively Cooled 1 kw Coaxial Winding Tansfome fo Fast Chaging Electic Vehicles, IEEE-IAS Conf. Rec., Denve, USA, Oct. 1994, pp [34] A. Kunia, O.H. Stielau, G. Venkataamanan and D.M. Divan, Loss Mechanisms in IGBT s Unde Zeo Voltage Switching, IEEE-PESC Conf. Rec., Toledo, Spain, Octobe 199, pp [35] N.H. Kutkut, D.M. Divan, D.W. Novotny and R.H. Maion, Design Consideations and Topology Selection fo a 1-kW IGBT Convete fo EV Fast Chaging, IEEE Tans. Powe Electon., vol. 13, no. 1, pp , Jan [36] W.R. Lachs, D. Sutanto and D.N. Logothetis, Powe System Contol in the Next Centuy, IEEE Tans. Powe Systems, vol. 11, no. 1, pp , Feb [37] M. Lindgen, Filteing and Contol of a Gid-connected Voltage Souce Convete, Licentiate s Thesis, Depatment of Electic Powe Engineeing division of Electical Machines and Powe Electonics, Chalmes Univesity of Technology, Gothenbug, Sweden, Sept [38] G. Maggetto, Advanced Dive Systems and Infastuctue fo Electic o Hybid Buses, Vans and Passenge Cas (II), EPE Jounal, vol., no. 3, pp , Oct

179 Refeences [39] G. Maggetto, Advanced Dive Systems and Infastuctue fo Electic o Hybid Buses, Vans and Passenge Cas (III), EPE Jounal, vol., no. 4, pp. 11-4, Dec [4] L. Malesani, P. Tomasin and V. Toigo, Space Vecto Contol and Cuent Hamonics in Quasi-esonant Soft-switching PWM Convesion, IEEE-IAS Conf. Rec., Denve, USA, Oct. 1994, pp [41] L. Malesani, P. Tenti, P. Tomasin and V. Toigo, High Efficiency Quasi-Resonant DC Link Thee-Phase Powe Invete fo Full- Range PWM, IEEE Tans. Ind. Applicat., vol. 31, no. 1, pp , Jan./Feb [4] Colonel W.T. McLyman, Tansfome and Inducto Design Handbook, Macel-Dekke, New Yok, USA, [43] A. Metens, Design of a kva Resonant DC Link IGBT Invete on the Base of Expeimental Device Evaluation, EPE 91 Conf. Rec., Fienze, Italy, Sept. 1991, vol. 4, pp [44] N. Mohan, T.M. Undeland and W.P. Robbins, Powe Electonics; Convetes, Applications, and Design, nd ed., Wiley, New Yok, USA, [45] J. Mucko, H.G. Lange and J.Ch. Bendien, A Novel Resonant DC to DC Convete with High Powe Density and High Efficiency, EPE 89 Conf. Rec., Aachen, Gemany, Oct. 1989, vol. 3, pp [46] S. Munk-Nielsen, Thee Phase Resonant DC Link Convetes; Analysis and Simulation, Ph. D. Thesis, epot no.1, Depatment of Electical Enegy Convesion, Institute of Enegy Technology, Aalbog Univesity, Aalbog, Denmak, Apil [47] S. Munk-Nielsen, Thee Phase Resonant DC Link Convetes; Analysis, Realization and Test, Ph. D. Thesis, epot no., Depatment of Electical Enegy Convesion, Institute of Enegy Technology, Aalbog Univesity, Aalbog, Denmak, Apil [48] T. Nilsson, Undestanding the IGBT popeties in pactical opeation, Licentiate s Thesis, Depatment of Electic Powe Engineeing division of Electical Machines and Powe Electonics, Chalmes Univesity of Technology, Gothenbug, Sweden, Dec

180 Refeences [49] J.A. O, A.E. Emanuel and D.J. Pileggi, Cuent Hamonics, Voltage Distotion, and Powes Associated with Electic Vehicle Battey Chages Distibuted on the Residential Powe System, IEEE Tans. Ind. Applicat., vol. IA-, no. 4, pp , Jul./Aug [5] D. Owen, J. Simpson and J. McGuie, UK Electic Vehicle Chaging Infastuctue Case Study, EVS-1 Conf. Rec., Anaheim, USA, Dec. 1994, vol. 1, pp [51] H.W. Ott, Noise Reduction Techniques in Electonic Systems, nd ed., Wiley-Intescience, New Yok, USA, [5] A. Petteteig and T. Rogne, IGBT Tun-Off Losses - In Had Switching and with a Capacitive Snubbe, EPE 91 Conf. Rec., Fienze, Italy, Sept. 1991, vol., pp [53] V. Picket and C.M. Johnson, Thee-Phase Soft-Switching Voltage Souce Convetes fo Moto Dives. Pat 1: Oveview and Analysis, IEE Poc.-Elect. Powe Appl., vol. 146, no., pp , Ma [54] V. Racek, R. Kistof and P. Flajzik, A Novel Method fo Optimising of Soft Switched Invete with Quasi Resonant Cicuit, EPE 99 Conf. Rec., Lausanne, Switzeland, Sept [55] S. Salama and Y. Tados, Novel Soft Switching Quasi Resonant 3-Phase IGBT Invete, EPE 95 Conf. Rec., Sevilla, Spain, Sept. 1995, vol., pp [56] A. Sikoski and T. Citko, Quasi-Resonant Paallel DC Link Cicuit fo High-Fequency DC-AC Invetes, EPE 93 Conf. Rec., Bighton, UK, Sept. 1993, vol. 3, pp [57] A. Sikoski, T. Citko and T. Paczkowski, Contol of the Thee Phase AC/DC Tansisto Convete with Quasi-Resonant Commutating Cicuit, IEE-PEVD Conf. Rec., London, UK, Oct. 1994, pp [58] A. Sikoski, Optimization of the AC/DC/AC Convete Cuent Contol Loop, EPE 97 Conf. Rec., Tondheim, Noway, Septembe 1997, vol. 3, pp

181 Refeences [59] R.L. Steigewald, R.W. De Doncke and M.H. Khealuwala, A Compaison of High Powe DC-to-DC Soft-Switched Convete Topologies, IEEE-IAS Conf. Rec., Denve, USA, Oct. 1994, pp [6] B.G. Steetman, Solid State Electonic Devices, 3d ed., Pentice-Hall Intenational, Englewood Cliffs, USA, 199. [61] S.M. Sze, Semiconducto Devices; Physics and Technology, Wiley, New Yok, USA, [6] K. Thobog, Powe Electonics, Pentice-Hall Intenational, London, UK, [63] B.W. Williams, Powe Electonics; Devices, Dives, Applications and Passive Components, Macmillan, New Yok, USA, 199. Databooks [64] Evox Rifa Film Capacitos , [65] Evox Rifa Electolytic Capacitos , [66] Intenational Rectifie, IGBT Designe s Manual, [67] Micometals Powe Convesion & Line Filte Applications, [68] Semikon Powe Electonics 99,

182

183 A Modulation In this appendix convete modulation is consideed. Fist, caie based pulse width modulation (PWM) is intoduced. This kind of modulation stategy is often used fo had switched convetes, and it is often stated that it is suitable also fo quasi esonant DC link convetes. Howeve, esonant DC link convetes cannot use this kind of modulation stategy, since these convetes ae only allowed to switch at the zeo voltage intevals of the esonant link voltage. This implies that the switching fequency is detemined by the esonant link oscillation fequency. The method used fo this kind of convetes is temed discete pulse modulation (DPM). Hee, only the opeation of one such modulation stategy is discussed. Featues like diffeences in output spectum and so on ae discussed in the liteatue [3], [44], [6], [63], but ae left out in this text. A.1 Caie based PWM Caie based PWM is well discussed in the liteatue, fo example in [3], [44], [6], [63]. Hee, caie based PWM is only discussed to give a moe complete desciption of the contol system and its inteface to the powe electonic main cicuit. The contolles, used in both the simulation and the implementation of the battey chage, geneate voltage efeence values. These efeence values ae fed to the modulato whee they ae tansfomed into pulses detemining whethe the uppe o lowe tansisto of each half bidge should be on. This implies that one voltage efeence value must be geneated fo each half bidge, to fom the pulse patten fo each half bidge output potential. In ode to geneate this pulse patten, the PWM stategy adopted uses a caie wave. The caie wave can have diffeent shapes, fo example tiangula o saw-tooth shaped. Both fo the simulations of the diffeent battey chage topologies and fo the implementation, tiangula caie

184 A. Modulation PWM is used. Anyway, saw-tooth caie PWM ae used fo the quasi esonant DC link convetes epoted in [17], [4], [41]. The switching instants fo a paticula half bidge ae detemined by the cossings between the caie wave and the voltage efeence value fo the half bidge consideed. Fo an AC convete the voltage efeence value is time vaying with a fequency detemined by the desied output fequency. Of couse, the caie fequency must be seveal times highe than the fequency of the voltage efeence value fo the modulation to wok popely. The atio between these two fequencies is efeed to as the pulse numbe, o modulation index. In ode to obtain the pope aveage output voltage fo a cetain efeence value, the caie wave amplitude has to be a function of the DC link voltage. Note that the DC link voltage limits the maximum output voltage possible to supply to the load. To some extent, the convete topology also detemines the paametes of the caie wave. Fo example one single half bidge (the battey side convete consideed in the thesis) can have an aveage output voltage ideally anging fom zeo up to the DC link voltage level. This implies that the caie wave should vay between these values. On the othe hand, a thee phase VSC (fo example the line side convete consideed in this thesis) has both negative and positive instantaneous output voltages, implying that the caie wave in this case vaies between a value coesponding to minus half the DC link voltage to plus half the DC link voltage. All thee phases can use the same caie wave to detemine the switching instants in this case. Note that in both cases above, the peak to peak value of the caie wave is popotional to the DC link voltage. Also, note that in the thee phase convete case, it is not necessay fo the caie to vay between a negative and a positive value, since a constant value can instead be added to each voltage efeence value. A constant value added in this manne, coesponds to a zeo sequence component which can not be supplied by such a convete anyway [4]. Saw-tooth caie PWM As the name implies, the caie wave in this case is saw-tooth shaped. This means that the caie will tavese fom its minimum value to its maximum (o vice vesa) abuptly. When this occus, the cossing between caie wave and efeence value will occu simultaneously fo all phases using this caie. One example of saw-tooth caie modulation 176

185 A. Modulation of a thee phase convete is shown in Figue A.1. Note that the pulse numbe is consideed as vey high which means that the voltage efeences appeas as constant fo the shot time inteval shown. 1 V dc v a, ef - 1 V dc c a v b, ef v c, ef v saw t t c b t c c t Figue A.1 Saw-tooth caie PWM of a thee phase convete. In Figue A.1, the efeence levels fo each phase, v a,ef, v b,ef and v c,ef, ae shown togethe with the saw-tooth caie wave v saw. Also the coesponding pulse pattens fo each phase, c a, c b and c c, ae shown. The intepetation of these pulse pattens is that fo each half bidge, a high level coesponds to uppe switch (tansisto o diode) conducting and a low level means that the lowe switch is conducting. Tiangula caie PWM Tiangula caie PWM uses a tiangula wave as caie. The main diffeence in opeation compaed to the peviously discussed saw-tooth caie PWM, is that in this case simultaneous switching only occus when two efeence values ae equal at the caie cossing. Figue A. shows the esulting pulse patten when tiangula caie PWM is used fo a thee phase convete. Simila to the pevious case, the pulse numbe is consideed as being vey high. 177

186 A. Modulation 1 V dc v ti v a, ef - 1 V dc c a v b, ef v c, ef t t c b t c c t Figue A. Tiangula caie PWM of a thee phase convete. The intepetation of the quantities given in Figue A. is the same as the one given fo saw-tooth caie PWM, except that the caie is called v ti in this case. A. Discete pulse modulation Discete pulse modulation is simila to hysteesis contol [3]. In hysteesis contol the idea is to feed the efeence value and the actual value to a compaato with a dead band. The compaato output detemines the switch state to be set fo each half bidge. In this way the actual value is kept within a hysteesis band located aound the efeence value. Voltage egulated sigma delta modulato The voltage egulated sigma delta modulato (Σ M), is the by fa most popula modulato used fo esonant DC link convetes, mainly due to the fact that the modulation is load independent and exhibits elatively good spectal pefomance [18]. This type of modulato acts upon the eo between the measued output voltage and its efeence level. The eo is fed to an integato. The output of the integato is input to a compaato, with hysteesis band equal to zeo. 178

187 A. Modulation Since this modulato is used fo esonant DC link convetes, the switching instants commanded by the compaato ae delayed until a esonant link voltage equal to zeo is obtained. This can be achieved by latching the command signal fom the compaato, and the use of anothe compaato to geneate the clock signal to the latch when zeo voltage occus. Figue A.3 shows a schematic of the Σ -modulato fo one bidge leg. Hee, K is the gain of the integato and D symbolises the D-latch. The signal zv fed to the D-latch, is the clock signal which tigges the D- latch when zeo voltage is detected. v i, ef - K D c i v i zv Figue A.3 Schematic pictue of the Σ -modulato fo one half bidge. Thee ae a lot of inteesting featues egading Σ -modulation, some of them can be found in [13], [18]. 179

188

189 B Contol In this section the contolles used in the simulation model ae descibed. Fist the battey side cuent contolle is discussed and then the vecto cuent contolle used fo the line side convete. Finally the DC link voltage contolle is discussed. Fo details on the contolle used fo the implemented battey chage, see [4]. B.1 Battey side cuent contolle The simulation model battey o DC side cuent contolle is implemented as a PI contolle, with feed fowad of the battey voltage. All the contolles discussed in this appendix ae based on sampled quantities, i.e. time discete. Hence, the discete time battey side PI cuent contolle is witten k 1 * * 1 * vbatt ( k + 1) = K ( ibatt ( k) ibatt ( k) )+ ( ibatt ( n) ibatt ( n) ) T i + + v batt ( k) n= (B.1) whee v batt and i batt ae the battey voltage and cuent, espectively. The coesponding efeence values ae maked with a sta (*). The gain of the popotional pat is selected in ode to obtain dead beat action, i.e. fo a step change in the output cuent efeence level, the actual output cuent should each this value at the next sampling instant. The following gain, K, and integato time constant, T i, ae used fo the simulation model battey side cuent contolle L R K = + Ts 1 L Ti = + RT s (B.)

190 B. Contol whee L and R ae the load inductance and esistance, espectively. The sampling time is denoted T s. B. AC side vecto cuent contolle The vecto contolle is based on the synchonously otating efeence fame dq-system. This implies that that the thee phase quantities (abc) have to be tansfomed into the stationay efeence (αβ) fame (two phase quantities) and then futhe tansfomed into otating efeence (dq) fame (two phase quantities). The contolle acts upon the dq-quantities, and also gives efeence values expessed in the otating fame. Theefoe, the efeence values must be tansfeed back into thee phase quantities befoe they ae passed on to the modulato. Howeve, befoe the efeence values ae fed to the modulato they ae symmetised in ode to utilise the convete DC link voltage in a moe efficient way. Vecto tansfomations As stated above, the thee phase quantities ae tansfomed into two phase quantities, i.e. fom abc to αβ-quantities. This means that a vecto s in the stationay αβ -fame is expessed as αβ s sa sbe j π j π = ( + ( 3 ) + sce ( 4 3 ) )= sα + js 3 β (B.3) Fo a symmetic thee phase quantities, this is simplified to 3 sα = sa 1 sβ = sb s ( ) c (B.4) This is futhe tansfeed into the otating dq-fame, see Figue B.1, though the tansfomation which means that dq αβ jθ s = s e = s + js d q (B.5) 18

191 B. Contol sd = sα cosθ + sβ sinθ sq = sα sinθ + sβ cosθ (B.6) q β s β s ωt s q θ s α s d d α Figue B.1 The stationay and otating efeence fames. Note that this means that the fundamental components of the thee phase quantities ae expessed as DC quantities in the otating dq-fame. Fo a gid connected convete, the dq-system is oiented to the integal of the gid voltage vecto. This implies that the diection of the gid voltage vecto and the q-axis coincide. Hence, an easy way to calculate the tansfomation angle, θ, is fom eα sinθ = eα + e e β cosθ = eα + e β β (B.7) Note that this method is not suitable fo implementation whee distubances, tansduce offset and hamonics might intefee with the fundamental. Vecto contolle Cuent contolles fo the d and q components ae implemented in a simila way as the DC side cuent contolle. Howeve, in this case thee ae also coss coupling tems which appeas as feed fowad tems. Hence, k 1 * * 1 * vd( k + 1) = K ( id( k) id( k) )+ id( n) id( n) T ( ) i n = * Kc ( iq( k) + iq( k) )+ ed ( k) (B.8) 183

192 B. Contol k 1 * * 1 * vq( k + 1) = K ( iq( k) iq( k) )+ iq( n) iq( n) T ( ) i n + = * + Kc ( id( k) + id( k) )+ eq( k) (B.9) whee e denotes the powe gid voltage and K c is the coss-coupling gain. The gains and the integato time constant, fo dead beat cuent contol, is in this case given by L R K = + Ts π fl Kc = 1 L Ti = + RT s (B.1) whee f is the powe gid fundamental. In the simulations the following set points o efeence values ae used fo the AC side cuent contolle i i * d ( k) = vbatt ( k) vdc( k) ( k) = ibatt ( k) + i e ( k) e ( k) * * q dc q q ( k) (B.11) whee DC link capacito cuent efeence is detemined fom the DC link voltage contolle, discussed late on. Symmetisation The dq-fame voltage efeence values ae tansfeed into αβ -quantities and futhe into thee phase quantities. In ode to fully utilise the DC link voltage available, the thee phase efeence voltages ae alteed in such a way that the maximum and minimum instantaneous voltage efeence values have the same magnitude, i.e. that thei distance fom the zeo level ae equal. This is achieved by calculating = ( ( )+ ( )) 1 * * * * * * vz( k) max va( k), vb( k), vc( k) min va( k), vb( k), vc ( k) The new efeence values ae given by (B.1) 184

193 B. Contol * * vaz ( k) = va( k) vz ( k) * * vbz ( k) = vb( k) vz ( k) * * vcz ( k) = vc ( k) vz ( k) (B.13) Theefoe, this is called symmetisation. B.3 DC link voltage contolle In ode to maintain the DC link voltage at the desied level, it has to be contolled. The deviation between the actual DC link voltage and its efeence value, is multiplied with a gain giving a cuent efeence accoding to * dc * s ( ) i k K C dc( + 1) = dc T v dc( k ) v dc( k ) 4 (B.14) In ode to limit the cuent demanded by the DC link voltage contolle, the constant included in the gain is selected as K dc = 1. (B.15) The DC link cuent efeence value calculated above is added to the q- axis cuent efeence. Howeve, the low value of the gain, K dc, in effect means that the DC-link voltage contolle is tuned off, at least fo the shot simulation time employed ( ms). Instead, appoximate initial cuent contolle integal pats ae calculated fom the battey chage losses of pevious simulations, to accommodate fo the DC link voltage vaiations. This is done due to the fact that fo the shot simulation time used, the integal pats will not assume steady state conditions. 185

194

195 C Diffeential equations In this appendix a unified appoach to use the diffeential equations of a esonant cicuit in ode to chaacteise its behaviou is pesented. The obtained esults can be used to calculate peak values, constaints on component values etc. An application example whee the method is applied to the esonant DC link convete, is also given. C.1 Method A typical solution to the diffeential equations aising fom a esonant cicuit is u( α) = Acos( α) + Bsin( α) + D= E v( α) = ACsin( α) + BCcos( α) = F (C.1) Fo a ZVS esonant cicuit, u can be egaded as the voltage acoss the esonant capacito and v as the coesponding capacito cuent. A and B ae detemined by the initial values, fo the paticula mode of the esonant cycle. D is due to the stationay solution of the diffeential equation. E and F ae the values of u and v, espectively at instant α. Fo a esonant cicuit the esonance fequency, as well as the time, ae pat of α. Since the capacito cuent is the poduct of the capacitance and the time deivative of the capacito voltage, the facto C in (C.1) is the poduct of the capacitance and the time deivative of α, in this case. The equation system (C.1) above is substituted into BC( E D) AF sin( α) = ( A + B ) C AC( E D)+ BF cos( α) = ( A + B ) C (C.)

196 C. Diffeential equations This expession, togethe with the tigonometic identity sin ( α) + cos ( α) = 1 (C.3) gives constaints on what simultaneous values of u and v, i.e. E and F, that ae possible, accoding to F ( E D) + C = A + B (C.4) By using the obtained constaint above, one unknown final value of one mode of the esonant cycle can be calculated upon knowledge of the initial values and the othe final value of the paticula mode. By epeating this seveal times, an entie esonant cycle can be chaacteised. Futhemoe, the necessay initial values needed to assue a cetain final value can be calculated. C. Application to the esonant DC link convete The esonant DC link convete intoduced in section.3 is selected as an example to show the application of the method peviously descibed. Since only the behaviou of the esonant cicuit is of inteest hee, the simplified convete cicuit can be used, see Figue.16. Usually, the esonant cycle is only piecewise linea, which means that it has to be subdivided into intevals whee a cetain set of diffeential equations and initial conditions ae valid. These intevals ae efeed to as modes of opeation. As the fist mode of opeation (mode 1), a natual choice is the link voltage amp down inteval, i.e. the pat of the esonant cycle whee the esonant link voltage has a negative deivative with espect to time. Fo the esonant DC link, this mode of opeation is chaacteised by the diffeential equations dil L + vc = V dt dvc ic = C dt il = ic + io dc (C.5) 188

197 C. Diffeential equations By assuming that the output cuent is constant duing this mode, i.e. i o = I 1 (C.6) o this system of odinay diffeential equations can be ewitten as one second ode diffeential equation C vc = Vdc dt LC LC d v (C.7) This diffeential equation has the solution vc ( t) = Acos ω ( t t ) + Bsin ω ( t t ) + V (C.8) Hee, A and B ae constants depending on the initial values of the capacito voltage and cuent, espectively. The chaacteistic angula fequency of the esonance cicuit, ω, is given by dc ω = 1 LC (C.9) The capacito cuent is expessed by ic ( t) = ωc Asin ω ( t t ) + ωc Bcos ω( t t ) (C.1) Assuming a continuously oscillating esonant cicuit, i.e. without damping, gives the initial conditions fo this mode v ( t ) = A+ V = V ic ( t ) = ω C B= C dc dc (C.11) The constants A and B ae detemined by the initial conditions, which means that the esonant link capacito voltage and cuent ae given by ( ) vc ( t) = Vdc 1 + cos ω ( t t ) ic ( t) = ωcvdc sin ω( t t ) (C.1) Mode 1 is finished when zeo esonant link voltage is obtained, which gives v i C C ( t ) = 1 ( t ) = 1 (C.13) 189

198 C. Diffeential equations These values seves as initial conditions fo the next mode of opeation. It should be clea that in this case they ae easy to calculate without the use of the peviously shown method. As soon as the zeo voltage inteval is enteed a new convete switch state is set, if desied. The zeo voltage inteval is somewhat special fo this type of esonant link convete, in the sense that its duation can equal zeo. This is due to the fact that a decease in the output cuent, i o, accoding to the new switch state of the convete implies that the esonant inducto L has excess enegy stoed, esulting in a positive, non-zeo esonant link capacito cuent occuing immediately afte the output cuent change. If, on the othe hand the output cuent is inceased, the link voltage is clamped to zeo by the feewheeling diodes of the convete. At the same time, the inducto cuent is inceased since the entie DC link voltage is applied acoss L. Mathematically this is expessed by the diffeential equation dil L = Vdc (C.14) dt which have the solution Vdc i t i t L t t I Vdc L ( ) = L ( 1) + ( 1) = o1 + ( L t t 1 ) (C.15) The zeo voltage clamping due to the feewheeling diodes is inhibited as soon as the esonant inducto cuent, i L, eaches the level of the output cuent I o. This means that the esonant link voltage amp up inteval (mode 3) stats when i ( t ) = I (C.16) L o When analysing this cicuit it is impotant to emembe that the last expession is only valid if the output cuent is inceased. Othewise the link voltage amp up inteval stats immediately, i.e. when i ( t ) = I (C.17) L o1 One of the poblems when analysing this cicuit aises fom this fact, since this esults in diffeent initial conditions fo the esonant link capacito cuent, depending on the output cuent change. 19

199 C. Diffeential equations Fo mode 3, the diffeential equations of mode 1 ae still valid, howeve with a new set of initial conditions. The initial conditions in this case ae dependent on whethe the output cuent fom the esonant cicuit, i o, has inceased o deceased due to the new switch state of the convete. If the output cuent has inceased, a zeo voltage inteval has been pesent pio to mode 3 and the initial capacito cuent will equal zeo. If the output cuent has deceased, the initial capacito cuent will be non-zeo and positive. Fo the latte case, it was peviously stated that the duation of the zeo voltage inteval (mode ) will be vey shot. Howeve, in both these cases the initial capacito voltage equals zeo, thus Mathematically the fist case is expessed as v ( t ) = A+ V = (C.18) C dc i ( t ) = I (C.19) L o i ( t ) = ω C B= (C.) C which gives ( ) vc ( t) = Vdc 1 cos ω ( t t) ic ( t) = ωcvdc sin ω( t t) (C.1) The maximum esonant link voltage is eached when the capacito cuent equals zeo, i.e. which gives ic ( t3 ) = (C.) vc ( t3 ) = V (C.3) Hee, the esonant cycle is completed fo the fist case. The second case is mathematically expessed as dc i ( t ) = I > I (C.4) L o1 o i ( t ) = ω C B= I I C o1 o (C.5) This gives the solution 191

200 C. Diffeential equations Io1 Io vc ( t) = Vdc( 1 cos ω ( t t) )+ sin ω ( t t) ω C ic ( t) = ωcvdc sin ω( t t) + ( Io1 Io) cos ω ( t t) (C.6) Also in this case the maximum esonant link voltage appeas when the capacito cuent equals zeo. By using the descibed method, i.e. equation (C.4), the maximum voltage in this case is descibed by Io I vc ( t3) = Vdc + Vdc + ω C 1 o (C.7) This expession can be simplified to L vc ( t ) = Vdc + Vdc + C I o I ( ) 3 1 o (C.8) In this case the maximum esonant link voltage becomes highe than twice the DC link voltage. This means that the peviously assumed initial state fo the esonant link voltage amp down inteval (mode 1) is not valid in this case. Howeve, as seen in Figue.17, the initial conditions becomes valid afte only one additional esonant cycle. The VPC stategy Anothe example is found by applying the method to the voltage peak contol (VPC) stategy fo the esonant DC link convete found in [46], [47]. The idea of this stategy is to pefom the change of the switch state at such a esonant link voltage level that the maximum capacito voltage always becomes close to twice the DC link voltage. This implies that some of the switching tansitions ae made at a esonant link voltage somewhat highe than zeo. Howeve, since the VPC stategy is intended fo the esonant DC link convete, the diffeential equations and thei solutions found peviously ae still valid but with diffeent initial conditions. Conside the case when the output cuent i o is supposed to decease. Instead of allowing the capacito voltage to each zeo, the change of convete switch state takes place at v ( t ) = v (C.9) C 1 C 19

201 C. Diffeential equations The coesponding capacito cuent, pio to the change of switch state, is depicted as i ( t ) = i (C.3) C 1 C Equation (C.4) states that the elationship between v C and i C is given by This is ewitten to ic ω C + ( v V ) = V C dc dc ( ) C dc C C i = ( ω C ) V v v (C.31) (C.3) Since the capacito is dischaged at the esonant link voltage amp down inteval the solution is given by i = ( ω C ) V v v C dc C C (C.33) The inducto cuent at this instant becomes equal to i = I + i (C.34) L o1 C Since only the case when the output cuent, i o, inceases due to the change of convete switch state is consideed, the amp up inteval (mode 3) stats diectly. The initial esonant link capacito voltage is v ( t ) = A+ V = v (C.35) C 1 dc C The initial capacito cuent fo the esonant link capacito voltage amp up inteval becomes i ( t + ) = ω C B= i I = I I + i = C 1 L o o1 o C o1 o dc C C = I I ( ω C ) V v v (C.36) The aim of the VPC stategy is to fulfil (note t 1 =t ) vc ( t3) = V ic ( t3) = dc (C.37) If this is inseted into equation (C.4), the expession below is obtained 193

202 C. Diffeential equations ω C + ( V V ) = v V dc dc C dc ( o1 o dc C C) 1 + I I ω C V v v ( ) ω C ( ) + (C.38) This expession is ewitten to Io1 Io VdcvC vc = V v ω C dc C vc (C.39) By assuming the expession is futhe simplified v C Vdc (C.4) Io1 Io VdcvC vc = V v ω C dc C vc (C.41) This is equal to V v Io1 I = ω C dc C vc o (C.4) If both sides ae squaed, this expession becomes equal to V v 1 Io1 I vc = ω C dc C o (C.43) which is ewitten to v 1 Io1 I VdcvC + 4 ω C C o = (C.44) Accoding to the constaint (C.4), the only solution to this second ode equation is 194

203 C. Diffeential equations 1 Io1 I vc = Vdc Vdc 4 ω C 1 L = Vdc Vdc C I o1 4 I o = ( ) o In [46], [47] the coesponding expession is witten as v C Z Io I = Vdc 1 cos acsin Vdc ( ) o1 (C.45) (C.46) whee Z L = (C.47) C Hee, the symbol names ae fitted to the ones used peviously in this section, which ae not the same as the ones used in [46], [47]. Note that the VPC stategy is only used if the esonant link output cuent deceases due to the change in convete switch state, i.e. if I o1 >I o. Othewise, the maximum esonant link voltage do not exceed twice the DC link voltage anyway. C.3 Integation of the voltage equation Fo some of the esonant DC link cicuits the diffeential equations becomes linealy dependent. This implies that thee will be one tem in the inducto cuent expession which is linealy dependent in time. The eason fo this is that the solution contains an integation of the capacito voltage which has one constant tem. Assuming that the expession to be integated, is witten ut ( ) = Acos ω( t t) + Bsin ω( t t ) + D (C.48) If the deivative of v with espect to time equals u, i.e. if dv dt then v is found by integation of (C.48), thus = u (C.49) 195

204 C. Diffeential equations vt () vt ( ) = u( τ) dτ = t t = Acos ω ( τ t ) + Bsin ω ( τ t ) dτ t t ( ) = A B D B = sin ω ( t t) cos ω ( t t) + ( t t) + ω ω ω ω ω (C.5) 196

205 D Inducto design In this appendix, inducto design is eviewed. The design method used, is basically the same as the one descibed in [4]. Nevetheless, some of the steps ae also found in [44]. D.1 Inductance Fist, the inductance of a gapped ion coe inducto, see Figue D.1, is deived. N A Fe l δ i Figue D.1 Basic gapped ion coe inducto. Accoding to [1], the inductance L is defined as d L = ψ (D.1) di whee ψ is the flux linkage esulting fom the cuent i. Fo a linea media, i.e. disegading magnetic satuation and hysteesis in the case of an ion coe, this is equivalent to L = ψ (D.) i Fo the gapped ion coe of Figue D.1, Ampèe s cicuital law gives N i = HFe lfe + Hδ lδ (D.3) Hee, N denotes the numbe of winding tuns, H Fe and H δ the magnetic field intensity in the ion coe and ai gap, espectively. The magnetic

206 D. Inducto design flux mean path length is denoted l Fe in the ion and l δ in the ai gap. The magnetic flux densities, B Fe and B δ, is defined fom B B = µµ = µ H H Fe Fe Fe δ δ (D.4) whee µ is the pemeability of ai and µ Fe is the elative pemeability of the ion coe mateial. Substitution into Ampèe s cicuital law gives BFe Bδ N i = lfe + l µµ µ Fe δ (D.5) Assuming unifom flux densities, the flux linkage is expessed as = NBFe AFe = NB A (D.6) ψ δ δ whee A Fe and A δ ae the coss-sectional aeas of the ion coe and the ai gap, espectively. Substituting the flux linkage into Ampèe s cicuital law gives ψ lfe lδ N i = + µ N µ A A Fe Fe δ (D.7) Finging flux in the vicinity of the ai gap is neglected, which is equivalent to This gives B = B = B A = A (D.8) δ Fe δ Fe ψ lfe N i = + lδ µ A N µ Fe Fe (D.9) Reaanging this, gives an expession fo the inductance accoding to ψ µ AFeN L = = i lfe + l µ Fe δ (D.1) In most cases the elative pemeability of the ion coe is high and the ai gap long, i.e. 198

207 D. Inducto design l δ l Fe >> µ Fe (D.11) which implies that the inductance is appoximately given by A N L = µ Fe lδ (D.1) D. Inducto coe size selection One of the fist steps in the design of an inducto, is to select an appopiate coe size. The poblem of selecting the coe size aises fom the fact the geometical popeties of a coe ae composed in a wide vaiety of ways. It is thus desiable to select the coe size in a fomalised way, by assigning a geneal quantity to a coe that is not depending on its actual geometical shape, i.e. the atio between the geometical measues of the coe. A common way to accomplish is by selecting the coe based upon the desied aea poduct. Hee, this method is eviewed fom [44]. The peak flux linkage is expessed as ψ ˆ = Liˆ = NA Bˆ m Fe m (D.13) whee i m is the magnetising cuent. The winding window A w of a coe is in the case of a single inducto coil expessed as A w NACu = (D.14) k Cu whee A Cu is the winding coppe conducto coss-sectional aea and k Cu is the coppe fill facto, expessing how tightly wound the inducto coil is. The coppe conducto RMS cuent I Cu is expessed as ICu = ACu JCu (D.15) whee J Cu is the coesponding cuent density. Substitution into equation (D.13) gives Liˆ m JCu = k Bˆ Cu mawafe (D.16) I The aea poduct, AP, of a coe is defined accoding to Cu AP = A A (D.17) w Fe 199

208 D. Inducto design Substitution into (D.16) and eaanging the tems gives Liˆ I AP = k Bˆ J m Cu Cu m Cu (D.18) Fo an inducto, the coppe conducto cuent and the magnetising cuents ae equal fom a design point of view, i.e. Thus, in this case the aea poduct is witten i () t = i () t (D.19) m Cu Liˆ I AP = k BJ ˆ Cu Cu Cu Cu (D.) The last esult is also found in [44]. If seveal inducto coils ae wound upon a single coe, like fo a egeneative snubbe [63], the expession (D.18) has to be slightly modified. This is done by assuming equal cuent density of each of the inducto coils. This means that the winding window aea A w is equally divided among the winding coils. Thus, the winding window aea available fo one coil is witten A w Aw NACu 1 = N = N k (D.1) w w Cu whee N w is the numbe of windings, i.e. the numbe inductos, wound upon the coe. Note that, simila to the case of a tansfome, the inductance and both the magnetising and coppe conducto cuents must be efeed to the same coil. The AP value fo a coe with seveal inducto coils thus becomes AP N L i ˆ = I w k Bˆ J k m, k Cu, k Cu m Cu (D.) whee the inductance and cuents ae efeed to coil k. This is used fo coe selection of the clamping tansfomes used in the simulations of Chapte 5. Note that fo the implementation of a clamping tansfome, the magnetic coupling facto must also be taken into consideation. As discussed in Chapte 6, designing fo a specified coupling facto is a by fa stonge constaint than selecting coe size based on the AP value. Thus, the method above can not eadily be used fo design of a clamping tansfome.

209 D. Inducto design D.3 Inducto design example In this section one way of designing a cetain type of inductos is given though an example. The inducto designed is actually used in the line side LCL-filte of the battey chage pesented in [3]. The design is based on a tape wound C-coe. An advantage of tape wound coes is that a high stacking facto is obtained even though a thin steel tape (.5-.3 mm) is used. The specification of the inducto is given in Table D.1. Table D.1 Inducto specification. L.3 mh I 1 khz I 5 khz I 1 khz 1 A 1 A Thus, the total RMS cuent is appoximately given by the 1 khz component, i.e. 5 A I Cu 1 A (D.3) By using fou paallel conductos of ectangula coss-section, 3 5 mm, a RMS cuent density equal to A/mm is obtained. The absolute maximum magnetising, and thus coppe conducto, cuent is calculated accoding to î Cu = A = 185 A (D.4) To select coe size, an initial guess of a suitable peak magnetic flux density has to be done. Hee B ˆ = 35. T (D.5) is selected. Also, a easonable guess on the coppe fill facto k Cu must be made. A common value is.4. If this is used it is found that Li I AP = ˆ Cu Cu k BJ ˆ = 379 cm 4 (D.6) Cu Cu The C-coe TELMAG Su 15b, have geometical popeties accoding to Figue D. and Table D.. 1

210 D. Inducto design e a Figue D. c g b d Inducto based on a C-coe. The winding (gey) is split into two paallel connected windings. Table D. Geomety of the coe Su 15b. a 55.6 mm b c d e g 15. mm 49.4 mm 76. mm 154. mm 5. mm By including the stacking facto of the coe with.1 mm tape, the ion coe aea is found A Fe = cm = 3. 8 cm (D.7) The winding window aea is appoximated as A w cm = 77. cm (D.8) Hence, the aea poduct fo this coe becomes AP = A A =57 cm 4 (D.9) w Fe An initial guess, i.e. without ai gap, of the numbe of winding tuns equied, is given by equation (D.13). Thus N = Liˆ Cu A Bˆ = 48 tuns (D.3) Fom equation (D.1), the total ai gap length is calculated. Fe µ AFeN lδ = = 3 mm = 16 mm (D.31) L Accoding to [4], the finging flux facto, k FF, is calculated as

211 D. Inducto design k FF = 1 + lδ e A ln l =. 65 (D.3) Fe δ The finging flux facto is then used to adjust the numbe of winding tuns, to compensate fo the finging flux intoduced in the vicinity of the ai gap. lδ L N = = 3 tuns (D.33) µ A k Fe The educed tuns atio implies that the peak magnetic flux density becomes highe than expected. Accoding to (D.13) it is given by FF ˆ ˆ LiCu B = = 53. T (D.34) A N Fe The peak flux density is calculated fo each fequency component and then the ion coe loss fo each component is found fom the manufactue data sheets, which fo.1 mm tape gives Bˆ 1 khz =. 486 T B ˆ 5 khz =. 9 T Bˆ 1 khz =. 14 T P P P Fe,1 khz Fe,5 khz Fe,1 khz = 141 W = 1 W = 6 W (D.35) If mino loops ae neglected, the total ion coe loss is found diectly summing the loss associated with each cuent component, i.e. PFe = PFe, i = 157 W (D.36) i Anothe ion coe loss component, ai gap loss due to finging flux components being pependicula to the tape suface, intoduces additional eddy cuent losses. In [4], the ai gap losses ae calculated fom the empiically deived expession P = 388dl f Bˆ δ, i δ i i (D.37) The coesponding ai gap losses, fo the diffeent cuent components, is found to be 3

212 D. Inducto design P P P δ,1 khz δ,5 khz δ,1 khz = 1 W = 4 W = W (D.38) Again, the total ai gap losses ae found by summing the components Pδ = Pδ, i = 18 W (D.39) i which seems to be faily high. To calculate the losses in the winding, efeed to as coppe losses, the mean length pe tun, MLT, is calculated. Fo a C-coe with a winding geomety accoding to Figue D., i.e. two coils, MLT is given by MLT = c + d + g = 351 mm (D.4) The total winding esistance of the inducto is calculated at a winding tempeatue of 9 C. At this tempeatue the esistivity of coppe, ρ Cu, equals Ωmm /m. The winding esistance is thus R Cu The coppe losses is calculated fom N MLT = ρcu = 44. mω (D.41) A Cu P = R I = 58 W (D.4) Cu Cu Cu In ode to estimate the tempeatue ise of the winding, its suface aea is calculated accoding to ATCu, = 4e( c+ g) + e( d + g) + 4g( c+ g) + dg=. 176 m (D.43) Also, the ion coe suface aea is calculated A = 4bc+ bd + 4cf = 676 m (D.44) TFe,. The total themal flux density though the coppe winding, is calculated as Ψ TCu, = 1 A TCu, e + Fe Cu b e P + P + P δ = 78 W/m (D.45) In the same manne, the themal flux though the ion coe suface not coveed by the coppe winding, is calculated 4

213 D. Inducto design Ψ TFe, = 1 A TCu, b b+ e P Fe = 1154 W/m (D.46) Accoding to the liteatue, fo example [4], [44], heat tansfe is due to two physical pocesses, adiation and convection. Radiation follows the expession ( ) Ψ T, ad =. ε T s T a (D.47) whee ε is the emissivity of the suface, and T s and T a ae the suface and ambient tempeatues, espectively. Heat tansfe by convection is accoding to [4], expessed as ( ) η Ψ T, conv = 17. s a FT T p (D.48) whee F is an ai fiction facto, η is a facto depending on the shape and oientation of the suface and p is the elative pessue. Note that othe text books pesents diffeent methods fo calculating the convection heat tansfe. The total heat tansfe is given by the sum of the adiation and convection components, i.e. ΨT = ΨT, ad + ΨT, conv (D.49) Howeve, since the heat tansfe by convection is complicated to model, heat tansfe is instead calculated fom expeience. In [4] it is stated that the heat tansfe is usually 55 % adiation and 45 % convection, which means that the total heat tansfe can be appoximated diectly fom the adiation component. The tempeatue ise at an ambient tempeatue of 4 C, using this appoximation, is shown in Figue D.3. In Figue D.3, anothe appoximation is also shown whee the tempeatue ise is calculated accoding to T s = Ta + α ΨT + k T α a (D.5) whee the two constants ae selected as α =1 W/m C and k α =.1 W/m C. As seen in Figue D.3, both methods give simila esults. If equation (D.5) is used, the tempeatue ise of the coppe winding suface becomes TsCu, Ta =174 C o (D.51) 5

214 D. Inducto design which is by fa too high. The tempeatue ise of the ion coe suface becomes TsFe, Ta = 7 C o (D.5) T s -T a [ C] Figue D Ψ T [W/m ] Calculated tempeatue ise at an ambient tempeatue of 4 C, based on adiated heat (black) and an appoximate method (gey). The calculated tempeatue ise of the coppe winding suface is high, mainly due to the ai gap losses. Often, the ai gap losses ae not included in the tempeatue calculation, which in this case gives Ψ TCu, = 1 A TCu, e + Fe Cu b+ e P P = 174 W/m (D.53) TsCu, Ta =67 C o (D.54) Anothe question to be asked, is how good the empiical ai gap loss model is. Howeve, when the inducto was implemented and tested, the coppe winding suface close to the ai gap was by fa too hot, i.e. moe than 13 C. To patially ovecome this poblem, the winding was split close to the ai gap, in ode to give a moe efficient cooling of the ion coe in the vicinity of the ai gap, see Figue D.4. Anothe advantage gained by splitting the winding, is that the eddy cuents induced in the coppe winding, ae educed. To some extent this solved the poblem, but fan cooling was also needed. 6

215 D. Inducto design (b) Figue D.4 (a) Magnetic flux lines (a) of the entie inducto, and (b) of the egion aound one of the ai gaps. 7