pn-junctions Semiconductor Metal Oxide Diode - The Simplest IC-device Advanced Digital IC-Design What is a MOS-transistor?

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1 Advaced Digital IC-Desig his lecture will he MOS-trasistor Refresh the MOS-trasistor fuctio ad models Especially, short chael effects Digital IC-Desig he Diode i a IC-device he Diode Diodes appears i all MOS-trasistors (the drai & source area hey have parasitics that affects the performace (speed, power Diodes should always be backward y biased (egative V BS 1

2 Diode - he Simplest IC-device Advaced Digital IC-Desig Discrete compoet ICstructure p + + Metal Semicoductor + p + SiO he MOS rasistor p-juctios he MOS-trasistor: A Old Ivetio I 195, Julius Edgar iliefeld described the first MOSFE structure - U.S. Patet i 1930 hat is a MOS-trasistor? MOS = Metal Oxide Semicoductor Polysilico I early thirties, a similar structure was show by Oskar Heil - British Patet i 1935 Noe of them built a workig compoet Metal Oxide SiO Silico, doped he first workig MOS-trasistor was show i the early sixties Semicoductor

3 he MOS-trasistor (or MOSFE N-MOS rasistor Most importat device i digital desig Very good as a switch Bulk Silico Structuret Relatively few parasitics Rather low power cosumptio High itegratio desity Each box i the layout represets a mask or a step i the process p p hi Oxide Simple maufacturig Ecoomical for large complex circuits Mask ayout P-MOS rasistor How does it ork? Bulk p + + p + p + - echologies N-ell P-ell wi-ub Opes a chael must be lager tha a threshold V V V drives a curret N-ell he gate legth sets the ame of the techology 3

4 hat is a MOS rasistor? MOS a Four ermial Device voltage cotrols the curret from drai to source A Switch Circuit Symbol coected to lower potetial for -chael devices (ofte to GND S G R o eq D S G D coected to higher potetial for p-chael devices (ofte to V DD Bulk keeps the substrate at a stable potetial. If ot show it is assumed to be coected to the supply/gnd. Ifiite resistace whe < V R eq whe V V = hreshold voltage Bulk (Body Bulk (Body Importat Dimesios How does the rasistor ork? echology developmet: he is slightly icreased t ox 1993: 0.6 um 003: 65 m 013: 18 m? Negative charges are attracted A depletio regio is formed > he techology is amed after the gate legth Diode area Depletio Regio 4

5 How does it ork? iear Regio (Resistive Operatio he is icreased above V More egative tha positive charges are attracted close to the gate (turs to -type material A chael is formed (Strog iversio V is icreased slightly Horizotal E-field from drai to source A curret is established > V > V V < -V chael Depletio Regio -chael Depletio Regio iear Regio (Resistive Operatio iear Regio (Resistive Operatio is proportioal to the vertical E-field i.e. to the # of charges attracted by the gate voltage is proportioal to the horizotal E-field i.e. to the charge velocity caused by the drai voltage V V ID = k ( V V V forms a vertical E-field + I + V establish a horizotal E-field ID = μ Qξ μ = Electro mobility ξ = E-field over the chael Q V V # of charges attracted by the gate Q V ess charges i drai regio V ξ = V ID = k ( V -V - V ( k' = μcox From charge coc. From Horizotal E-Field 5

6 Saturatio Regio Saturatio Regio V = V Strog iversio reached precisely (i.e. V GD = V No chael close to the drai > V V = -V + + V /" Isert V = -V i the liear equatio V ID = k ( V V V V V = k ( V ( V k ID = ( V V Chael egth Modulatio Chael egth Modulatio V > -V Pich off he effective chael legth is modulated by V Electros are ijected through the depletio regio Saturatio V > -V >V V >V -V + + Pich off I k V V V D = ( (1 +λ λ = Empirical costat 6

7 he hreshold Voltage V he Bulk (Body Potetial he substrate is slightly doped ( for NMOS here are always free electros i the substrate o form a chael, we eed to attract t these egative charges he threshold is whe the umber of egative ad positive charges are equal he value of V is thus set by the p-dopig cocetratio > V he bulk is most ofte coected to GND (V DD for PMOS Negative V SB opes the diode; Not Allowed Positive V SB makes it harder to attract t egative charges to the chael hat is, the threshold voltage will icrease V V SB p chael + + Depletio Regio Strogly p-doped he hreshold Voltage V MOS Model for og Chaels V = V + γ ( φ + V φ 0 F SB F φ F = Fermi potetial γ icreases with the acceptor cocetratio ow threshold ow voltage trasistors but they are leaky wo threshold voltage techologies ca be used for low power idely used model for maual calculatios V V V V k = μ C V = V V ; V ; ox + γ ( I I D D φf + = k (( V k = ( V V V V (1 + λv φ 0 VSB F V (1 + λv Added to avoid discotiuity 7

8 Velocity & Mobility Velocity & Mobility he electro (hole velocity is related to the mobility ( μ m μ = = Electro mobility Vs m μ p = = Hole mobility Vs ypical 0.35μm techology he mobility is depedet o dopig cocetratio Ofte determied empirically Note that the electro mobility is about 3 times higher he electro (hole velocity is related to the mobility he velocity is also depedet o the E-field ( ξ υ = μ ξ υ p = μξ p m s m s ( μ Velocity Saturatio ( υ sat Velocity Saturatio ( υ sat ( ξ V forms a horizotal E-field A icreased E-field leads to higher electro velocity However at a critical E-field ( ξ c, the velocity saturates due to collisios with other atoms υsat 10 for both electros ad holes s 5 m + + V establish a horizotal E-field ν (m/s Costa t Mobility υ 0 E ξ sat c = μ E ξ Costat Velocity ν sat = 105 m/s ξ E [V/um] he mobility is ot costat whe velocity saturatio is reached 8

9 versus V (ma -V = =.07 V V A = 0.63 V = V DD =.5 For both V (V og-chael model Short-chael model versus (A 6 x quadratic (V og Chael (A.5 x liear quadratic (V Short Chael versus V V = -V Quadratic ( (ma =.5 0. (ma 0.4 = = = iear ( =.5 =.0 = 1.5 = V (V V (V Model for Maual Aalysis A first order model of the velocity υ = μ ξ for ξ ξc υ = υsat = μ ξc for ξ ξc og Chael Short Chael 9

10 Model for Maual Aalysis A Uified Model for Maual Aalysis A first order model of the velocity saturated regio: VA IA = μ Cox (( V V VA ' Vmi ID = k (( V V Vmi (1 +λv Vmi = mi( V V, V, VA A Uified Model for Maual Aalysis hree Regios ' V ID = k (( V V V (1 +λv Resistive V A 0.63 V 0.15 (ma V = V ' ID = k ( V V (1 +λv Saturated 0.1 iear Velocity saturated V = 1.5 V ' VA ID = k (( V V VA (1 +λv Velocity saturated 0.5 V = 1 V -V Saturated V (V

11 he PMOS rasistor Sub-threshold Regio Velocity saturatio is less proouced for PMOS due to lower mobility he sub threshold drai curret have a expoetial relatio to the gate voltage (compare to bipolar 0 x 10-4 V = -1.0V (A -0. V = -1.5V -0.4 Assume that all variables Iare V = -.0V 0V egative! V = -.5V l(id Super-threshold regio (Super-V Sub-threshold regio (Sub-V V (V V 1 3 (V MOS Dyamic Behavior MOS Capacitaces wo ypes of Capacitace Juctio Capacitace -Diode areas - Divided i two parts - area ad side wall Capacitace - to Bulk - to / C + C SB X d C G C GD + C DB t ox Chael Cap. Juctio Cap. Overlap Cap. 11

12 Juctio Capacitace Juctio Capacitace / Diffusio Bottom C Diff = C Bot + C S C Diff = C Bot + C S C Bot = C j Area C j i F/um owards Chael Do t cout the wall towards the chael C S = C js Perimeter C js i F/um Noliear: depedet o the diode voltage s Side all Capacitace Chael Capacitace X d Cut off iear C G = C ox eff eff C G depeds o the regio C C GB C GD Saturatio C OX i F/um + + 1

13 Overlap Capacitace Coclusios - Static Behavior C GD = C ox X d C = C ox X d X d ' V ID = k (( V V V (1 +λv Resistive C ox i F/um Or C GD = C o C = C o C eff C GB C GD ' k ID = ( V V (1 + λv Saturated ' VA I = k (( V V V (1 + +λ V Ve locity saturated D A C o i F/um V = V0 + γ ( φf + VSB φf hreshold Voltage A Uified Model for Maual Aalysis Coclusios - Dyamic Behavior ' Vmi ID = k (( V V Vmi (1 + +λ V C G = C ox eff C GD = C = C ox X d Capacitace V mi = mi( V V, V, V A V = V0 + γ ( φf + VSB φf C Diff = C Bot + C S C Bot = C j Area C S = C js Perimeter Juctio Capacitace 13