JFETS MOSFETS. MOSFET vs JFETS. JFET s MOSFETS. FETS Spec sheets Configurations Applications

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1 JFET MOFET BJT JFET MOFET Circa G/I (signal gain) Best Better Good FET pec sheets Configurations Applications Isolation PN Junction Metal Oxide ED Low Moderate Very sensitie Control Current oltage Voltage Power YE No Yes Acknowledgeents: Neaen, Donald: Microelectronics Circuit Analysis and Design, 3 rd Edition pring 2014 Lecture pring 2014 Lecture 6 2 MOFET MOFET s JFET Much ore finicky difficult process (to ake) than JFET s. Good news: Extreely high input ipedance. Zero input current. Bad news: Easily blown up by ED on the gate. Add protection circuit and input bias current becoes at best coparable to JFET s. Good news: Essentially infinitely fast. If you change the gate oltage, the deice will respond instantaneously! Essentially always in static equilibriu. Bad news: It can be really hard to change the gate oltage quickly! (especially power deices) Much better power deices than JFET s. (There were briefly power JFET s as output deices in audio aps. Too any blew up.) And you can t ake digital VLI out of JFET s. JFET s MOFET s JFET Very siple anufacturing process like BJT s. Much cheaper than (discrete) MOFET s. Quieter than MOFET s. Low input bias current like back biased diode. As low as 10pA. But note this doubles eery 6 deg C! At high teps a JFET op ap can hae ore input current than soe bipolar op aps! Used in icrophones, hearing aids and other high ipedance sources (electret icrophones hae ery high output ipedance) because of low noise and ruggedness copared to MOFET s. Fast. Used on any high speed scope probes. Was ajor adance in bias current and speed oer bipolar input op aps. ee data sheets of (JFET input) LF356 series and copare to then extant bipolars. Downside is input capacitance can t be as low as soe BJT s. Wide spread in threshold oltage and zero V current. oeties requires sorting and selecting for a gien circuit pring 2014 Lecture pring 2014 Lecture 6 4

2 Field Effect Transistors (FET) MOFET ybols FETs are oltage controlled deice with ery high input ipedance (little current) p channel MOFET: Metal Oxide eiconductor FET JFET: Junction FET traditional interediate odern/siplified D G G D n channel N channel JFET P channel JFET pring pring 2014 Lecture 6 6 iple Model of MOFET Excellent graphic showing four states of MOFET for different V and Vds D G + ~0 gate current D D V - G G MOFET ade VLI (icroprocessors and eories) possible. Very high input resistance Voltage controlled deice ~25 V ax operating off state V < V t on state V V t pring pring 2014 Lecture 6 8

3 What s the difference between the drain and the source? Classic ideal MOFET characteristics Flat cures in saturation region assue long channel MOFET s can be syetrical and drain and source interchangeable. Especially inside IC s. But discrete deices (with few exceptions) hae input protection networks on the gate to protect against ED. Also, the substrate ust connect soewhere. Once the input protection claping and the substrate are connected to a terinal, that ust be the source pring 2014 Lecture pring 2014 Lecture 6 10 ideal osfet cures continued Channel Length Modulation: Early Voltage Triode ode, or linear ode, or ohic region. aturation or actie ode. As the channel length becoes short, these equations becoe inaccurate. At the channel ends, source and drain regions causing fringing effects and Distort the electric fields fro the ideal case used to derie aboe eq s. For analog design, long-channelmofet s can offer extreely high output Ipedance, aking excellent stiff current sources. Miniu geoetry transistors used in digital VLI do not hae such flat cures pring 2014 Lecture pring 2014 Lecture 6 12

4 MOFET: Gain & non linearity source Heaily doped (n-type or p-type) diffusions Very thin (<20Å) high-quality io 2 insulating layer isolates gate fro channel region. Channel region: electric field fro charges on gate locally inerts type of substrate to create a conducting channel between source and drain. W L bulk gate Polysilicon wire Inter-layer io 2 insulation drain I D W/L Doped (p-type or n-type) silicon substrate MOFETs (etal-oxide-seiconductor field-effect transistors) are four-terinal oltage-controlled switches. Current flows between the diffusion terinals if the oltage on the gate terinal is large enough to create a conducting channel, otherwise the osfet is off and the diffusion terinals are not connected Chris Teran FETs as switches The four terinals of a Field Effect Transistor (gate, source, drain and bulk) connect to conductors that generate a coplicated set of electric fields in the channel region which depend on the relatie oltages of each terinal. gate source drain INVEION: A sufficiently strong ertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. The gate oltage when the channel first fors is called the threshold oltage -- the osfet switch goes fro off to on. E h N+ N+ p bulk E inersion happens here CONDUCTION: If a channel exists, a horizontal field will cause a drift current fro the drain to the source Chris Teran pring 2014 Lecture pring 2014 Lecture 6 16

5 2N7000 2N pring 2014 Lecture pring 2014 Lecture 6 18 MOFET Configurations NMO Coon ource More generalized coon source with source degeneration and equations: pring 2014 Lecture pring 2014 Lecture 6 20

6 NMO Coon Drain ource Follower Equations Three basic configurations. MOFET Configurations Coon source Coon drain Coon gate pring 2014 Lecture pring 2014 Lecture 6 22 Equations: NMO Coon Gate Cascode Configurations All hae the sae purpose to decouple the input terinal (of the botto deice) fro capacitie feedback fro the output by taking the output fro a second deice. Botto deice: Current gain (no appreciable oltage gain) Top deice: Voltage gain (no current gain) Cobines coon-eitter/source/cathode with coonbase/gate/grid. esult is pring 2014 Lecture 6 23 BJT JFET MOFET Vacuu tube triode pring 2014 Lecture 6 24

7 Cascode Configuration continued ingle deices with cascode like construction Botto deice: Current gain (no appreciable oltage gain) Top deice: Voltage gain (no current gain) Cobines: with coon-eitter/source/cathode coon-base/gate/grid. esult is like a single coon-eitter/source/cathode deice with drastically reduced Miller capacitance fro the output to the input. Tetrode (tet for 4 terinal) acuu tube adds a fourth grid called a screen to shield the grid and cathode fro the anode iilar MOFET deice incorporates a second gate. Useful for F circuits pring 2014 Lecture pring 2014 Lecture 6 26 JFET Aplifier Configurations Coon ource JFET (bypassed source resistor) Coon ource Aplifier Coon Drain Aplifier [ource Follower] * For polarized [electrolytic] input coupling capacitor, the "+" should be oriented towards the ost positie DC oltage. For exaple, if there is -2V on the gate, and -8V associated with Vin, then the capacitor orientation should be reersed as shown. The input coupling cap for the coon gate configuration will ost often be a polarized electrolytic, since the ipedance at the ource of the JFET is only 1/g in parallel with. Coon Gate Aplifier A out in gl A 1 g gl gl g 1 g or A g L pring 2014 Lecture pring 2014 Lecture 6 28

8 Coon Drain Aplifier (ource Follower) Coon Gate Aplifier A out in g g g ; 1 g 1 g A g A out in gl i gi then g 1 1 g A g L L i ; i if i 0, pring 2014 Lecture pring 2014 Lecture 6 30 Output esistance ource Follower Low Frequency Hybrid π Model i g + V _ I test s d g V + V test eoe and replace it with a test AC oltage generator hort the input signal V i and replace it with its source resistance i. ole for I test, which is a consequence of applying the test generator V test, and for V test in ters of the hybrid-π paraeters. _ To correctly calculate the alue of a bypass capacitor for s, use the parallel cobination of r o and. r o V I test test V g V 1 g pring 2014 Lecture pring 2014 Lecture 3 32

9 OK, now what can we do with these thin? JFET follower This scheatic fro the now obsolete Intersil 7662 datasheet shows how a flying capacitor generates a negatie oltage fro a positie oltage. lightly different connections can double a oltage instead of inerting it. A JFET follower using atched (dual) JFET s. The botto JFET autoatically generates just the right aount of current to bias the top one so Vin is approxiately equal to Vout pring 2014 Lecture pring 2014 Lecture 6 34 JFET ariable attenuator The Dolby B noise reduction circuit used this circuit as a Variable attenuator. Horowitz and Hill go through the equations To show how adding ½ the drain oltage back to the gate oltage Greatly linearizes the JFET resistance. ynchronous ectification Patent 8,493,751 Dr. chlecht, forer MIT Professor of Electrical Engineering ynchronous rectification refers to replacing diode rectifiers with power MOFET, and synchronizing their on/off to the priary. MIT Professor chlecht did not inent the concept, but he cae up with a fiendishly cleer way to drie the MOFET s with effectiely reactie coponents and waste less power in the gate drie. He founded ynqor, now in Boxborough Mass, in Power conerters generating high currents (50A, 100A) at low oltages (3.3V, 1.8V) for digital boards (think Google serer fars) ust use synchronous rectification the forward oltage drop of een hottky rectifiers would kill the efficiency. Fro An introduction to electronics, cabridge Uni Press pring 2014 Lecture pring 2014 Lecture 6 36

10 Neat Circuit Ideas Fro Make a classic phase shift oscillator (3 stages of 60 deg phase shift each any three digital logic inerters will usually do) so you can WATCH the oscillation run around the loop! Works with any odd nuber of stages. Question Is this guaranteed to start up? Why? And what if you had a large (odd) nuber of stages can you start a skinny pulse going around the loop? Wiill it stay skinny or widen and turn into 50-50% duty cycle? More fro sae web site note single ended drie iplies this otor has coutator brushes. I had wrongly assued these drills used brushless otors. 3-LED CHAE This circuit let's you see how a FET turns on and how it works. eoe the connections to the gate of the first FET and the LED will start to illuinate. The gate will start to get a charge on it and the FET will turn on. Place a 1M between gate and 0 and the FET will turn off. This shows the sensitiity of the gate. The charge on the gate ust be reoed for the FET to turn OFF. This circuit will show how the FET turns ON slowly as the oltage on the gate increases and turns OFF slowly as the oltage drops: pring 2014 Lecture pring 2014 Lecture 6 38 Iportant basic power configuration The H bridge Note how the high side MOFET s are drien by leel shift. Four drie signals required. Note the trade off in switching speed ersus static power dissipation in leel shifter. The 10k resistor will not turn off the IF9Z30 ery fast. But otor dries don t operate at ery high frequencies pring 2014 Lecture 6 39 Continuing fro this web site This is a great suary of MOFET failure odes AKA (Also Known As) What NOT to do with a MOFET. WHY MOFETs FAIL There are quite a few possible causes for deice failures, here are a few of the ost iportant reasons: Oer-oltage: MOFETs hae ery little tolerance to oer-oltage. Daage to deices ay result een if the oltage rating is exceeded for as little as a few nanoseconds. MOFET deices should be rated conseratiely for the anticipated oltage leels and careful attention should be paid to suppressing any oltage spikes or ringing. Prolonged current oerload: High aerage current causes considerable theral dissipation in MOFET deices een though the on-resistance is relatiely low. If the current is ery high and heatsinking is poor, the deice can be destroyed by excessie teperature rise. MOFET deices can be paralleled directly to share high load currents. Transient current oerload: Massie current oerload, een for short duration, can cause progressie daage to the deice with little noticeable teperature rise prior to failure pring 2014 Lecture 6 40

11 MOFET failure odes continued hoot-through - cross conduction: If the control signals to two opposing MOFETs oerlap, a situation can occur where both MOFETs are switched on together. This effectiely short-circuits the supply and is known as a shoot-through condition. If this occurs, the supply decoupling capacitor is discharged rapidly through both deices eery tie a switching transition occurs. This results in ery short but incredibly intense current pulses through both switching deices. The chances of shoot-through occurring are iniized by allowing a dead tie between switching transitions, during which neither MOFET is turned on. This allows tie for one deice to turn off before the opposite deice is turned on. No free-wheel current path: When switching current through any inductie load (such as a Tesla Coil) a back EMF is produced when the current is turned off. It is essential to proide a path for this current to free-wheel in the tie when the switching deice is not conducting the load current. This current is usually directed through a free-wheel diode connected antiparallel with the switching deice. When a MOFET is eployed as the switching deice, the designer gets the free-wheel diode "for free" in the for of the MOFETs intrinsic body diode. This soles one proble, but creates a whole new one pring 2014 Lecture 6 41 MOFET failure odes continued low reerse recoery of MOFET body diode: A high Q resonant circuit such as a Tesla Coil is capable of storing considerable energy in its inductance and self capacitance. Under certain tuning conditions, this causes the current to "freewheel" through the internal body diodes of the MOFET deice. This behaiour is not a proble in itself, but a proble arises due to the slow turn-off (or reerse recoery) of the internal body diode. MOFET body diodes generally hae a long reerse recoery tie copared to the perforance of the MOFET itself. This proble is usually eased by the addition of a high speed (fast recoery) diode. This ensures that the MOFET body diode is neer drien into conduction. The free-wheel current is handled by the fast recoery diode which presents less of a "shoot-through" proble pring 2014 Lecture 6 42 MOFET failure odes continued MOFET failure odes continued Excessie gate drie: If the MOFET gate is drien with too high a oltage, then the gate oxide insulation can be punctured rendering the deice useless. Gate-source oltages in excess of +/- 15 olts are likely to cause daage to the gate insulation and lead to failure. Care should be taken to ensure that the gate drie signal is free fro any narrow oltage spikes that could exceed the axiu allowable gate oltage. *** WAIT A MINUTE! This author fails to point out that practically all discrete MOFET s hae a oltage clap on the input. The actual failure echanis is usually you elt the claping zener, and the puddle of olten silicon fors a short. The MOFET ay be fine, but the gate is now shorted to the source, which akes it kind of hard to use. Insufficient gate drie - incoplete turn on: MOFET deices are only capable of switching large aounts of power because they are designed to dissipate inial power when they are turned on. It is the responsibility of the designer to ensure that the MOFET deice is turned hard on to iniise dissipation during conduction. If the deice is not fully turned on then the deice will hae a high resistance during conduction and will dissipate considerable power as heat. A gate oltage of between 10 and 15 olts ensures full turn-on with ost MOFET deices. ***NOTE: The reference to gate oltages of between 10 and 15 olts applies to older or higher oltage power deices (like 20 to 200V). The newer power parts hae long been based on the latest digital process: i.e., they re designed for 5V. Newer power MOFET s hae guaranteed on resistance at lower V oltages consistent with use in 3.3V logic utputs, and hae Vds absolute axiu ratin of 6V or 7V, and siilar abs ax V ratin. Modern logic requires lots of power conersion deices operating at these low oltages pring 2014 Lecture pring 2014 Lecture 6 44

12 Tektronix P6201 FET 900MHz 3pF 1:1 probe (fro Tek anual, found at P6201 Probe Manual.pdf no warranty for iruses! May want to check Tek website first Hi-freq signal path ( tweeter ) pring 2014 Lecture pring 2014 Lecture 6 46 Tek P6201 continued What you can do with a JFET. Fro Linear Technology app. Note 45, Fig 6. ise tie about 30ns, a little slow, too uch capacitie loading of Q1 s source for really high speed. This was a three feeding session circuit. ee next slide. Low freq signal path ( woofer ) uses low-frequency op ap. Hi & lo freq cobined in output stage that dries 50 oh scope input pring 2014 Lecture pring 2014 Lecture 6 48

13 Ji Willia s hoe lab with baby. For further reading and possible inspiration for your projects, read Ji Willias app notes! You gotta loe a guy who titles an app note (#25) : And on the next slide here s the last page: pring 2014 Lecture pring 2014 Lecture pring 2014 Lecture 6 51