Analyzing Methods Study of Outer Loop Current Sharing Control for Paralleled DC/DC Converters

Transcription

1 Analyzing Methods Study of Outer Loop Current Sharing Control for Paralleled DC/DC Conerters Yang Qiu, Ming Xu, Jinjun Liu, and Fred C. Lee Center for Power Electroni Systes The Bradley Departent of Electrical Engineering Virginia Polytechnic Institute and State Uniersity Blacksburg, VA 2406 USA Abstract Outer loop current sharing control ethod is ost widely used for paralleled DC/DC conerters. There are ainly two ethods to analyze its stability and transient perforance. The first ethod uses transfer function odels, while the other uses output ipedance odels. The adantages and disadantages of these two ethods are inestigated and discussed in this paper. * I. INTRODUCTION Copared with centralized power syste, the distributed power syste (DPS) proides seeral adantages such as redundancy, reliability, design standardization and ease of aintenance. Howeer, due to theral and deice stress requireents, unifor current sharing aong paralleled odules is a priary concern. Seeral ethods hae been proposed and practiced by the industry. A copleentary classification of the existing current sharing ethods for DC/DC conerters has been docuented [][2]. The passie droop ethod is siple, but it is hard to achiee high current sharing accuracy and high oltage regulation accuracy at the sae tie [3]. The actie current sharing control, with a current sharing bus as the current reference signal, is widely ipleented. According to the control structure, i.e., the relationship of current sharing control loop with oltage regulation loop, the actie ethod is further classified into outer loop regulation (OLR), inner loop regulation (ILR) and dual loop regulation (DLR). Aong the, OLR ethod is the ost popular industry solution. According to how the current sharing bus is organized aong odules, three bus progra ethods hae eer been proposed, i.e., autoatic aster (AM), with the highest current signal takes the current sharing bus [4]; aerage progra (AP), with the aerage load current signal as current sharing bus [5]; and dedicated aster (DM), only the current inforation fro one prescribed odule is directly connected to the current sharing bus. The fundaental issue of the current sharing control is its relationship with oltage regulation control. Howeer, the control structure for paralleled odules with current sharing is uch ore coplicated than that of a single odule. At the sae tie, ore requireents hae been proposed, such * This work was supported priarily by the ERC Progra of the National Science Foundation under Award Nuber EEC as higher accuracy and better transient response. The current sharing schees need further analysis and understanding to aid the control design. Addressing OLR current sharing, there are ainly two analyzing ethods, one utilizes transfer function odels [6], and the other utilizes output ipedance odels [7][8]. In this paper, these two ethods are inestigated and explored. Adantages and disadantages are discussed. II. Outer Loop Current Sharing Control Fig. shows the configuration of outer loop current sharing with AM bus. Texas Instruent/Unitrode proides coercial chips for this control ethod [4]. Based on regular stand-alone odules, OLR current sharing is easy to realize. The stand-alone odules already has a ery fast current feedback loop as an inner loop to iproe the syste dynaic perforance and stability, and a quite fast oltage loop as the outer loop to regulate the output oltage. If these stand-alone odules are parallel connected using OLR current sharing structure, nothing has to be changed inside each odule, including the current feedback loop and oltage loop design. The only thing need to do is adding a slow current sharing control loop to each odule outside the oltage loop to adjust the oltage reference. With the AM structure, the conerter carrying the largest current is the aster odule and its current seres as the current sharing bus and then the coon current reference for the other odules. The oltage loop reference of the slae odule is adjusted through the current sharing copensator H CS according to the difference between its own output current and the coon current reference. As a result, the output current of the slae odule will follow that of the aster odule. Introduction of the current sharing control akes the whole syste coplicated. More control loops exist, and interactions of the paralleled odules ust be taken into consideration. The function and bandwidth of the control loops are usually designed to be clearly distinguished fro each other to ake sure there is no conflict. The current sharing control is relatiely slow because its bandwidth is liited by the oltage loop. Therefore the output currents of the parallel odules are not quite eenly distributed during the load transient, and in practical applications, soe

2 unnecessary inor alars occur as the load rapidly changes or one odule fails and shuts down. To get further iproeent of the OLR current sharing control, a fundaental understanding of the relationship of the control loops is needed. More analysis addressing this ost popular control schee is necessary. Fig. Outer loop current sharing control structure III. TRANSFER FUNCTION MODEL One ethod to analyze the paralleled conerters with current sharing is the sall signal transfer function odel [6]. Fig. 2 shows the transfer function blocks of a two conerter paralleled syste with OLR+AM current sharing control, with odule # as aster, and odule #2 as slae. In this case, inductor currents are used instead of output currents as the ariables to be controlled in the current sharing schee. The transfer functions of duty cycle to output oltage (G dx, x=,2) and to inductor current (G idxx, x=,2) should be calculated first. Because there exist interactions of one odule to another, G dx and G idxx are different fro those of an indiidual odule. For exaple, G idxx becoes a threepole two-zero function instead of the two-pole one-zero function in an indiidual odule. Transfer functions of one odule s duty cycle to another odule s inductor current (G idxy, x, y=,2, x y) should be considered in this structure, too. There are new loops introduced with the current sharing control. The current sharing loop gain, which physically deterines the current sharing transients, is defined as, T = K H H F G () i id 22 To design H CS to achiee a stable and fast loop, bode plot of T CS excluding H CS is shown in Fig. 3. Based on this figure, a current sharing copensator in the for of K c /(s/ω p +) is proposed by [6]. ω p is placed to get sufficient switching ripple attenuation. K c should be chosen large enough to get sall current sharing error, because H s zero frequency pole cannot guarantee zero current sharing error. The cross-coupling loop gain, which deterines how the aster odule s current is influenced by the current sharing schee, is defined as, T = K H H F G (2) cc i id2 Bode plot of T CS and T CC of a buck conerter syste design exaple are shown in Fig. 4. Because there is no negatie sign in T CC loop, its phase argin should be copared with 360 o, but not 80 o. The oltage control loop gain is changed by the current sharing control. With opening the aster s oltage control feedback, the slae conerter s oltage loop gain is, slae = _ T T (3) cc Where, T is the indiidual odule s oltage loop gain without current sharing control. T = K H F G (4) d The aster odule s oltage loop gain is also odified. ( T Tcc ) _ aster = + (5) T Tcc Total syste loop gain is the su of T _aster and T _slae. T = T T (6) _ total _ aster + _ slae It can be told that if the two odules are exactly identical, _ total = 2 (7) This is because with identical odules, there will be no current difference. The current sharing control will hae no influence on the syste. Fig. 2 Sall signal transfer function odel of two paralleled conerters

3 Fig. 3 Bode plot of T CS excluding H CS T _aster, T _slae and the indiidual odule oltage loop gain T _i are shown in Fig. 5. T _slae is changed draatically fro an indiidual odule. The reason is that current sharing control akes the slae odule becoe a current source. In low frequency region, T _slae is uch less than T _aster.this eans the aster odule take the role of output regulation. To aoid the output oltage regulation fighting between the slae odule and aster odule, T _slae should be saller than T _aster, thus aoiding the unwanted chattering proble, i.e., the aster/slae role change during transient [6]. To ake the current sharing control stable, the current sharing loop and the cross-coupling current sharing loop should be stable. The oltage regulation loops should be stable at the sae tie. Fig. 5 Bode plot of the oltage loop gains IV. OUTPUT IMPEDANCE MODEL An alternatie ethod to analyze the sall signal stability and transient perforance of outer loop current sharing is the systeatic approach. The basic idea of this ethod is shown in Fig. 6 [2]. It utilizes the interface stable concept. To ake the whole syste stable, each odule should be stable, i.e., each odule s output ipedance or output adittance should be stable. At the sae tie, the syste interconnection is stable, i.e., the syste inor loop gain as (8) should be stable. T = / =/ Y (8) o load o load Where, o is the output ipedance of the paralleled odule syste, Y o is the output adittance of the syste. Fig. 4 Bode plot of T CS and T CC Fig. 6 Basic idea utilizing the interface stability concept

4 The sall signal odels to calculate the aster and slae odule s output ipedance are shown in Fig. 7 and Fig. 8 separately. In these figures, ol_x (x=, 2) is the open loop output ipedance. Because the interface concept is utilized and what to be considered is the unterinated output ipedance, there is no interaction for the power stages. Therefore, the aster odule s output ipedance is not influenced by the current sharing control. ol_ o_aster = o_aster = (9) TV While the slae s ipedance is changed to: o _ slae = o _ slae ( + T o _ slae o _ aster CS T ) CS (0) ( o _ aster o _ slae = o (3) TCS ) Fro (3), it can be shown clearly that the current sharing loop gain is critical to both the stability and transient perforance of the syste. Therefore, it is expected to get a high current sharing control loop bandwidth for better transient perforance. The current sharing controller design is a trade-off between faster transient and syste stability. ˆ The current sharing loop gain TCS = K ih H Gd () ol _ 2 o_aster and o_slae are the close loop ipedances of the indiidual aster and slae odules. It is easier to consider the slae odule s stability with the output adittance. Y o _ slae + TCSYo _ aster Yo _ slae = (2) TCS The current sharing loop gain T CS is critical to the stability of slae odule. The copensator can be designed in the sae way as the analyzing ethod with transfer functions. For the buck conerter, the bode plot of T CS excluding H CS is shown in Fig. 9. Finite or infinite DC gain H CS can be designed to get sufficiently sall current sharing difference. A design with the H CS in the for of K c /(s/ω p +) is shown in Fig. 0 and Fig.. In a stable syste, the current sharing loop gain T CS should hae enough phase argin, and the Nyquist plot of T should not encircle (, j0) point if there is no RHP poles in T. Therefore, to get a stable paralleled syste with OLR+AM current sharing, first, each indiidual odule should be stable; second, H CS should be designed to ake T CS stable; and the syste inor loop gain should be exained. It can be also told fro Fig. 0 that inside the current sharing bandwidth, slae odule s output ipedance is pulled to atch the aster odule s. This eans the higher the current sharing bandwidth, the closer the ipedances of the paralleled odules with current sharing, and the better transient perforance [7]. The relationship between the load change and output current difference is: iˆ ˆ ˆ ˆ o = io io2 = o ( ) aster slae Fig. 7 Master odule s sall signal odel to calculate output ipedance Fig. 8 Slae odule s sall signal odel to calculate output ipedance Fig. 9 Bode plot of T CS exuding H CS

5 Fig. 0 Current sharing loop gain and its relationship with output ipedances V. COMPARISON OF TRANSFER FUNCTION MODEL AND OUTPUT IMPEDANCE MODEL The ethod using transfer functions is the direct way to analyze the current sharing control. It is alost sae as analyzing single odules except the odule interactions should be considered. Once eery transfer function is calculated, the loop gains can be deried. Howeer, when analyzing ore than two odules, the nuber of feedback loops grows draatically and this ethod becoes ipractical. Een with only two odules, the transfer functions ay be too coplicated in soe case. For exaple, if the output current inforation is used for load sharing, G idxy and G idxx will becoe fie-pole functions. It is then hard to design the current sharing copensator as proposed. At the sae tie, it is not clearly stated which loop gain is crucial for the syste stability and transient perforance assessent. Copared with the analyzing ethod of transfer functions, the ethod with output ipedance is easy to ipleent because the interface concept decouples the power stages of the paralleled odules and akes the transfer functions sipler, especially in ulti-odule case. Once the unterinated ipedances are deried, each conerter odule can be treated as a black box in the syste stability and transient analysis. It should also be noticed that the current sharing loop gain T CS defined in these two ethods is different fro each other. It is easier to derie with the output ipedance odel because there is no interaction of power stage should be taken into consideration. With both ethods, the current sharing copensator can be designed according to the bode plot of T CS excluding H CS. Howeer, if zero current sharing error is wanted, an infinite DC gain copensator is necessary, and the copensator design will be coplicated to ensure a stable and fast syste. VI. SUMMARY Two analyzing ethods addressing outer loop current sharing control are inestigated and ealuated. The ethod using transfer function odels is the direct way, but ay be too coplicated to use. The interface concept used by output ipedance odels siplifies the analysis by decoupling the power stage of the conerters. Current sharing copensator design is gien in both ethods. The adantages and disadantages of these two ethods are discussed. Fig. Nyquist plot of inor loop gain T ACKNOWLEDGMENT This work was supported priarily by the ERC Progra of the National Science Foundation under Award Nuber EEC

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