Lab1: TSRI Environment

Transcription

1 Lab1: TSRI Environment Lab 1: Basic Synthesis Design Flow Before you start: (TSRI) Login WS trainaxx Account : trainaxx Passowrd: train0xx Uncompress lab file: ( 請在自己的 home directory 下打 ) unix% cd unix% rm -rf SYNOPSYS unix% tar xvfz ~andy/dc_lab_ tgz Setting Design Compile Environment: unix% cp ~andy/.tcshrc ~ unix% cd ~/SYNOPSYS Download Lab File: Design Compile Lab Download: These labs take approximately 0.5 hour to complete S.S. WANG / Lab 1-1 Lab1: NCHU Environment Lab 1: Basic Synthesis Design Flow Before you start: (NCHU) Login WS Account : trainax Passowrd: trainax Uncompress lab file:( 請在自己的 home directory 下打 ) unix% cd unix% rm -rf SYNOPSYS unix% tar xvfz ~andy/dc_lab_ tgz Setting Design Compile Environment: unix% cp ~andy/.tcshrc ~ unix% cd ~/SYNOPSYS Download Lab File: Design Compile Lab Download: These labs take approximately 0.5 hour to complete S.S. WANG / Lab 1-2

2 Lab1: NCKU Environment Lab 1: Basic Synthesis Design Flow Before you start: (NCKU) Login WS cicxx Account : cicxx Passowrd: cicxx@ncku Uncompress lab file: ( 請在自己的 home directory 下打 ) unix% cd unix% rm -rf SYNOPSYS unix% tar xvfz ~cic/dc/dc_lab_ tgz Setting Design Compile Environment: unix% cp ~cic/dc/.cshrc ~ unix% cd ~/SYNOPSYS Download Lab File: Design Compile Lab Download: These labs take approximately 0.5 hour to complete S.S. WANG / Lab 1-3 Lab 1-1: Basic Synthesis Design Flow 1. Change directory SYNOPSYS/lab1 unix% cd ~/SYNOPSYS/lab1 2. Before invoking design vision, please check if there is a file named.synopsys_dc.setup please take a look at this file to see what is defined in this file, then invoke the design vision XG mode unix% ls -la.synopsys_dc.setup unix% gedit.synopsys_dc.setup & unix% dv 3. Read the file lab1.v in Use the dv menu bar File/Read to read the lab1.v in. Is there any problem? What is the error #? S.S. WANG / Lab 1-4

3 Find error 4. Use man #error_no or click the #error_no method 2 method 1 5. How can we fix the error for this error in lab1.v? (You can use vi or other text editor) 6. Read the file lab1.v again to see if there still have any error message or warning message. What else shall we need to modify? S.S. WANG / Lab 1-5 Synthesize Your Design 7. Compile the design Use the dv menu bar Design/Compile Design to synthesize your design. After synthesis, look at the hierarchy view, what happened? One more lab1_dw01_add_0 appears. Why does this lab1_dw01_add_0 appear? ( 合成後 ) S.S. WANG / Lab 1-6

4 Create Design Schematic 8. Create Schematic to see the result after synthesis. How many adders are there used after synthesis? 9. Choose the Ref named lab1_dw01_add_0, Create Schematic to see the structure of this adder. What type of the adder is synthesized cla or ripple or other form? 2 1 S.S. WANG / Lab 1-7 Report timing & area & resources 10. To select the lab1. Use Design/Report Design Resources to see what type of adder is used by DC? 11. Use the dv menu bar Design/Report Area and Timing/Report Timing Path to see the timing & area. area =, timing= 1 2 S.S. WANG / Lab 1-8

5 Set Timing Constraints 12. In the Symbol View, choose all input and output ports and in the dv menu bar, choose Attributes/Optimization Constraints/Timing Constraints Set the Maximum Delay to 0.8, then repeat the step 7. area =, timing= S.S. WANG / Lab Change Different DesignWare 13. Use Design/Report Design Resources to see what type of adder is used by DC? It s cla or ripple or pparch or other implementation form?. What causes this? 14. How to change the type of adder into cla structure? 2 1 S.S. WANG / Lab 1-10

6 Report timing & area & resources 15. Use Design/Report Design Resources to see what type of adder is used by DC? 16. Design/Report Area & Timing/Report Timing Path, is there any difference with step12? area=, timing= S.S. WANG / Lab 1-11 Lab 1 Answers / Solutions 3. Error Message: VER 在 output [8:0] z; 之後多加ㄧ行 reg [8:0] z; ( 或 output reg [8:0] z; 比較快!) 6. 修改 or b or c) 這行改成 => 雖然新版 DC 沒檢查出來但建議修改! 7. 因為合成之後 DC 會將 RTL Code 內的 +, 用實際的 DesignWare Library 取代之 個 ( 因為有用到 Resource Sharing 技巧 ) 9. 從 schematic view 觀察, 可猜測是 Ripple adder 10. 用 report_design_resource 來觀察的確是 rpl 11. Area= um 2, Timing= ns 12. Area= um 2, Timing= ns 13. pparch. 因為我們剛剛有針對 Combination 電路設定 Timing Constraints, Tool 幫我們隨意挑選一個可以滿足 0.8ns 以內完成計算的加法器. 14. set_implementation cla r368 (cell name 不見得一定是 r368 僅供參考!) 設定完之後需要再作ㄧ次合成 => compile 15. cla 16. Area= um 2, Timing= ns. ( 所以 cla 不見得是最好的, 只是很有名!) S.S. WANG / Lab 1-12

7 Lab2-1: Block Level Design (TSMC90) Setting Design Constraints & Compile Design & Report & Analysis These labs take approximately 1 hour to complete S.S. WANG / Lab 2-1 Introduction - Microwave Timer System The top of the hierarchical design consists of 3 blocks, microwave, timer and display. microwave contains a state machine, micro_st, which generates the control signal, and a loader that loads the time we want to cook, cook_time[15:0], to the timer. timer will decrease the cook_time per second, and display unit uses four 7 segments LEDs to display the cook time. As the cook time reach zero, these LED will display "done" to inform the completion of cooking. top display microwave timer converter loader micro_st S.S. WANG / Lab 2-2

8 Microwave Timer Specification The input and output of the top design is described below. clk is the synchronous clock of this design. reset is used to reset the microwave timer. If reset is zero, the design is reset to IDLE state. Until it changed to 1, then the timer start work. test pin is used to test if LEDs are OK. When test is 1, LED will display "8888". cook_time is the time we want to cook. set_time is used to set the cook time. When set_time is 1, cook_time is load into the timer. start_cook indicates starting of cook. When start_cook is changed to 1, cooking starts, and the cook time display is decreased one per second as time passes by. min_msb_led, min_lsb_led, sec_msb_led and sec_lsb_led are the outputs of BCD-to-7-segment converter, which are used to control the LEDs. S.S. WANG / Lab 2-3 Getting Start 1. Enter the directory SYNOPSYS/lab2/lab2-1, unix% cd ~/SYNOPSYS/lab2/lab2-1 unix% ls al 本 Lab 之 Script 是 script.tcl 不喜歡打字的同學可以直接用! 2. Check the contents of.synopsys_dc.setup. unix% gedit.synopsys_dc.setup & 3. Invoke the Design Vision XG mode unix% dv 4. Check the search path, link library, target library and symbol library. We will use slow.db fast.db tpzn90gv3wc.db tpzn90gv3lt.db as link library and target library, generic.sdb as symbol library. File -> Setup If it is ok, Cancel Compare it with the content of.synopsys_dc.setup gedit.synopsys_dc.setup & S.S. WANG / Lab 2-4

9 Read Design 切記 : 5. Read files File -> Read File type: All Files (.*) Click on converter.pla Open 6. To read other verilog files from dir1 & dir2. File -> Analyze Add dir1/top.v dir2/display.v, loader.v, micro_st.v, timer.v, microwave.v Select Enter COOK_TEMP Library OK 注意 : File -> Elaborate Choose COOK_TEMP Library Design: top(verilog) OK 也可使用 AutoRead 方法直接取代步驟 5, 6 3 S.S. WANG / Lab 2-5 Setting Operating Condition & Wire Load 7. To set Operating Conditional Attributes > Operating Environment >Operating Conditions Maximum operating condition: slow slow Minimum operating condition: fast fast 8. Attributes Operating Environment Wire Lode Click on tsmc090_wl10 OK S.S. WANG / Lab 2-6

10 Setting All Clock Constraints 9. View the symbol view of top and click clk port 10. Use Attributes -> Specify Clock to create clock signal (Spec: 4ns, duty cycle:50%, fix clock network & hold time, clock skew 0.1ns, and network latency 1ns). You can set the clock skew and latency in design_vision command line. design_vision> set_clock_uncertainty 0.1 [get_clocks clk] design_vision> set_clock_latency 1 [get_clocks clk] design_vision> set_input_transition 0.5 [all_inputs] design_vision> set_clock_transition 0.1 [get_clocks clk] S.S. WANG / Lab Setting Input Driving Strength / Output Loading 11. Setting input driving strength for clk port design_vision> set_driving_cell -library slow -lib_cell BUFX4 -pin {Y} [get_ports clk] 12.Setting input driving strength for all input port except clk design_vision> set_driving_cell -library slow -lib_cell DFFX1 pin {Q} \ [remove_from_collection [all_inputs] [get_ports clk]] 13. Setting output loading for all output port design_vision> set_load [load_of slow/dffx1/d"] [all_outputs] 不喜歡打字的同學可以將 script.tcl 檔案打開, 複製 step11~step13 的指令後, 直接執行! S.S. WANG / Lab 2-8

11 Setting Input /Output Delay 14. Setting input delay Select all input ports Attributes Operating Environment Input Delay Relative To Clock is set clk Max Rise & Fall as 1 Min Rise & Fall as 0.2 OK 15. Select all the output ports Attributes Operating Environment Output Delay Relative To Clock is set to clk Max Rise and Fall as 1 Min Rise and Fall as 0.1 OK S.S. WANG / Lab 2-9 Setting DRC & Check Design 16.Setting area constraints and design rule constraints in design_vision command line design_vision> set_max_area 0 design_vision> set_max_fanout 10 [all_inputs] design_vision> set_max_transition 0.3 [all_inputs] 17. Check design design_vision> check_design -multiple_designs What's the log message? 18. Uniquify the design converter to fix the above warning. (You also type uniquify) select top Hierarchy -> Uniquify -> Hierarchy OK Cell C133, C139, C143, C147 這些 Cell 合成後就會被最佳化掉了所以在此可以忽略掉! Multiple Instance 問題 S.S. WANG / Lab 2-10

12 Report all Constraints Before Compiler 19. Generate the Port and Design reports to see whether the attributes have been properly set Design -> Report Design, Design -> Report Port (click on verbose), Design -> Report Clocks OK 20. Save design and setup file Save design Select top File -> Save As Set File Name as top_before_compile.ddc, File Format as ddc Click on Save All Designs in Hierarchy Save Save setup file File -> Save Info -> Design Setup top_setup.dc Save Examine the top_setup.dc file in your unix shell unix% gedit top_setup.dc & (or vi top_setup.dc) S.S. WANG / Lab 2-11 Compile Design 21. Compile design Select top Design -> Compile Design set Map / Area Effort as high OK (or design_vision> compile -boundary -map_effort high -area_effort high) Examine which designs were optimized? this is what known as "Hierarchical Compile 22. Explore the schematic Create Schematic to see the result after synthesis. 23. Work with some view commands or zoom tool View -> Zoom -> Zoom In View -> Zoom -> Zoom Out View -> Zoom -> Full View View -> Zoom -> Zoom to Selection 可藉由滑鼠左鍵於電路圖上作局部放大 24. Select top File -> Save As Set File Name as top_after_compile.ddc, File Format as ddc Click on Save All Designs in Hierarchy Save S.S. WANG / Lab 2-12

13 Report and Find Critical Path 25. Check the area, timing, constraints Select top Design Report Area Timing Report Timing Design Report Constraints (click on verbose) Does all of the constraint meet? Which one is the critical path? S.S. WANG / Lab 2-13 Report Multiple Timing Path 26. Generate another version of a timing report Timing Report Timing Max paths per group: 5 Path type: full OK Examine is the critical path only one? 27. Go back top, generate report of Reference, Hierarchy for top Design Report Design Hierarchy Design Report Reference S.S. WANG / Lab 2-14

14 Dynamic Power Optimization 28. Before power optimization, you can see the timing & area & power first. cell area =, timing=, power= 29. Setting power constraints and gate-level power optimization design_vision> set_dynamic_optimization true design_vision> compile -inc 30. After power optimization, you can see the timing & area & power. cell area =, timing=, power= Dynamic Power Improve Capability(%)=, Timing meet constraint? S.S. WANG / Lab 2-15 Lab 2-1 Answers / Solutions 17. Design 'converter' is instantiated 4 times. (LINT-45) Cell 'display/convmm' in design 'top Cell 'display/convml' in design 'top Cell 'display/convsm' in design 'top' Cell 'display/convsl' in design 'top 21. 從 Design 最上層 top 開始ㄧ直到其最下層之所有 block 全部都會被合成與最佳化! ( 因此本 lab 是使用 : top-down 合成方法! 較為省事不需要每個 sub-module 逐一設定 Constraints) 25. No (area constraint not meet)<== 但沒關係因為 area 只要設計者覺得 OK 即可! Critical Path: Start Point: test -> End Point : timer/min_lsb_next_reg[1]/d 26. 最長的 Path Delay(Critical Path) 確實只有一條, 但是從 Report Timing 不難發現, 仍有相當多條的 Path 其 Delay 相當逼近 Critical Path, 不過這些 Path 其實都在附近而已. 28. Cell area = um 2, timing=3.9972ns(met constraint), power= dynamic: uw, leakage: uw 30. Cell area = um 2, timing=3.9907ns(met constraint), power= dynamic: uw, leakage: uw Dynamic Power Improve= % Timing meet constraint? Yes (Power 改善很少, Timing/Area 沒什麼變 ) 結語 : 由於 T90 WLM 太過悲觀, 實際上 Power 改善程度絕對不止這樣! 在下一個 Lab 2-2, 我們會故意拿掉 WLM, 測試 DC 在 Power Improve 程度為何? 如果下一個 Lab 實驗結果真的很好, 可以見得 WLM 不準確也嚴重影響到 Power 最佳化了! S.S. WANG / Lab 2-16

15 Lab2-2: Leakage Power Opt. by Multi-V t (TSMC90) In this lab, we will learn how to reduce the leakage power using TSMC90 Multi-Vt standard cell. The design is the same to lab2-1 These labs take approximately 0.5 hour to complete S.S. WANG / Lab 2-17 Multi-V t Leakage Power Opt. 1. Change directory to synthesis run directory unix% cd ~/SYNOPSYS/lab2/lab2-2/ 2. View the script file, what s the special setting in this script file? unix% gedit script.tcl & 3. Start Design Vision by command unix% dv 4. Execute script file to Read Design & Set Constraints & Synthesis design_vision> source script.tcl 5. Before power optimization, you can see the timing & area & power first. cell area =, timing=, Dynamic & Leakage power= S.S. WANG / Lab 2-18

16 Multi-V t Leakage Power Opt. 6. Setting HVT-Cell Library, power constraints and gate-level leakage power optimization design_vision> set target_library "slow.db slow_hvt.db fast.db fast_hvt.db \ tpzn90gv3wc.db tpzn90gv3lt.db design_vision> set_leakage_optimization true design_vision> compile -inc 7. After power optimization, you can see the timing & area & power. Cell area =, timing=, Dynamic & Leakage power= Dynamic & Leagage Power Improve(%)=, Timing Meet? How to report the ratio of RVT and HVT Cells? HVT Cells Ratio(%)=, RVT Cells Ratio(%)= S.S. WANG / Lab 2-19 Lab 2-2 Answers / Solutions 2. a. 由於 T90 WLM 太過悲觀, 本 lab 故意暫時拿掉, 測試 DC 在 Power Improve 程度為何! b. 故意設定一個 return 指令, 可以讓 script 跑到要的地方後自動中斷之後可以 step-by-step 慢慢執行! 4. Cell area = um2, timing= ns(meet timing constraint), Dynamic Power: uw Leakage Power: uw 6. Cell area = um2, timing= ns(meet timing constraint), Dynamic Power: uw Leakage Power: nw Dynamic Power Improve= 6.20% Leakage Power Improve= 72% ( 這才是正常的表現水準!) Meet Timing constraint? Yes (Leakage Power 改善不少, Area/Timing 仍然差不多!) set HVt_lib "slow_hvt.db:slow" set RVt_lib "slow.db:slow" set_attribute [get_libs $HVt_lib] default_threshold_voltage_group HVt -type string set_attribute [get_libs $RVt_lib] default_threshold_voltage_group RVt -type string report_threshold_voltage_group HVT= 89.08%, RVT=10.92% (DC 換了 89.08%HVT cells, 來減少 72% 的 leakage 的功率消耗!) S.S. WANG / Lab 2-20

17 Labs: CHIP Level Design Using T90 CBDK Lab 3-1: Cell-Based IC Contest Chip Level Synthesis Lab 3-2: Cell-Based IC Contest DC-T CHIP Synthesis These labs take approximately 1.0 hour to complete S.S. WANG / Lab 3-1 Calculation System Block Diagram 題目放在 : ~/SYNOPSYS/lab3/doc S.S. WANG / Lab 3-2

18 Lab 3-1 : CHIP-level Synthesis 1. Change directory to lab3-1 unix% cd ~/SYNOPSYS/lab3/lab View the lab3-1 design directory unix% gedit CS.v & unix% gedit CHIP.v & 3. View all *.tcl files unix% gedit 00_run.tcl & (run all script file) unix% gedit 01_import.tcl & (import all design & CHIP-Level Constraints) unix% gedit 02_compile.tcl & (compile design Constraints) unix% gedit 03_output.tcl & (save file script file) 4. Execute all script files to finish this lab unix% dc_shell -f./00_run.tcl tee run.log ( 執行完後若要開 GUI 可以打 start_gui) 5. Check the area, timing Design Report Area What's the cell area of this design? Timing Report Timing What s the timing of CHIP-Level (current_design CHIP)? What s the delay of output pad Y[7]? What s the delay of input pad X[3]? Design Report Power What's the power of this design? Dynamic Power:, Leakage Power: S.S. WANG / Lab 3-3 Timing Simulation 6. View test bench file and add sdf to this file ( 在此已改好, 所以不用另外加入!) initial $sdf_annotate(`sdffile, CHIP); 7. Begin to simulate synthetic result. Is this function PASS? ( 有興趣者可用 nwave 開.vcd 來看波形 ) unix% ncverilog testfixture.v chip_syn.v -v tsmc090.v -v tpzn90gv3.v +access+r S.S. WANG / Lab 3-4

19 Power Analysis using PrimeTime-PX 8. Before invoking PT-PX, please check.synopsys_pt.setup file unix% ls -la.synopsys_pt.setup unix% gedit.synopsys_pt.setup & What is the difference between.synopsys_dc.setup and synopsys_pt.setup? 9. invoking PrimeTime-PX unix% pt_shell 10. Run PrimeTime-PX Script (pt_script.tcl) to calculate power pt_shell> source pt_script.tcl What s the difference between CHIP_pt.tcl and CHIP_dc.tcl? How to get switch activity information? What s the worst case average power and peak power: What s the best case average power and peak power: What s the core (top) circuit power: S.S. WANG / Lab 3-5 Lab 3-1 Answers / Solutions 5. Cell Area= um 2 CHIP Timing = ns Dynamic Power = mw Leakage Power = uw 實際值 Y[7] pad delay = 3.59ns ( 方法 : report_timing -to [get_ports Y[7]] ) X[3] pad delay = 0.88ns ( 方法 : report_timing -from [get_ports X[3]] ) 8. 由於 PT-PX 只是 Power 分析軟體不需要合成所以 dw_foundation.sldb 相關設定皆不須要唯一需要僅 link_library 的內容! 10. DC 與 PT-PX 主要差在但須砍掉 一個作合成 一個作分析 因此 CHIP_pt.tcl 是由 CHIP_dc.tcl 複製而來 set_dont_touch_network [get_clocks clk] set_fix_hold [get_clocks clk] 因此兩行僅在合成時才會發揮作用所以要移除! Switch Activity 資訊是紀錄 Cell 在真實模擬中其 On/Off 狀況因此該資訊必續作 gate-level sim 才可得然而 PT-PX 讀取該檔案必須要未壓縮格式因此 gate-level sim 必須產生 VCD 格式以便於 PT-PX 分析之用! read_vcd -strip_path test/chip./chip_syn.vcd -time { } 其中 test 為 TestBench module name, CHIP 為 TestBench 中之 Cell name! 該 design 真實運算期間可以透過 waveform 觀察出 50 ~ 1055 期間才有真的在作運算故設定此 Range 以免影響到 average power 值之正確性! S.S. WANG / Lab 3-6

20 Lab 3-1 Answers / Solutions 10. Power (worst case) Corner => 1.1V Power (best case) Corner => 0.9V 正好與 Timing 相反 Timing (worst case) Corner => 0.9V Timing (best case) Corner => 1.1V 因此作 worst case Power Analysis 要先切換至 fast library set_operating_conditions fast report_power 反之作 best case Power Analysis 要先切換至 slow library set_operating_conditions slow report_power 因此 best case: average power = mw peak power = mw ( 差約 10 倍 ) worst case: average power = mw peak power = mw ( 差約 10 倍 ) top 電路在 APR 時會將其擺在 Core 區塊所以針對此分析可以清楚知道未來作 CHIP 其 Core Power Pad 要幾組才夠便相當重要了! Core Power = Total CHIP Power Total IO Power = = 8.5 mw 此值說明了未來 Layout 時只需要用到一組 Core Power/Ground Pad 即可! S.S. WANG / Lab 3-7 Lab3-2: DC-Topographical Flow Lab You will learn the new synthesis flow without wire load model (WLM). The design is same to lab3-1 These labs take approximately 0.5 hour to complete S.S. WANG / Lab 3-8

21 DC-topographical Flow 1. Change directory to lab3-2 directory unix% cd ~/SYNOPSYS/lab3/lab View the.synopsys_dc.setup and script files. What s the difference between lab3-1 and lab3-2 script files? unix% gedit.synopsys_dc.setup & unix% gedit 01_import.tcl & unix% gedit 02_compile.tcl & unix% gedit 03_output.tcl & 3. Enter the design vision topo mode unix% dc_shell -topo -f./00_run.tcl tee run.log ( 注意 : 第一次作本 lab, 因為 compile_ultra 會分析你所有的 db file 並建立 alib 目錄, 所以會比較久!) 4. What s the timing & area & power of this design after synthesis? cell area =, timing=, Dynamic Power:, Leakage Power: S.S. WANG / Lab 3-9 Lab 3-2 Answers / Solutions 2. 在.synopsys_dc.setup 裡多了一行設定 : set_tlu_plus_files -max_tluplus phy_lib/cln90_1p09m+alrdl_typical.tluplus -tech2itf_map phy_lib/t90.map 在 01_import.tcll 裡多了一行設定 : create_mw_lib CS_MW -technology phy_lib/tsmc090_9lm_2thick.tf -open -mw_reference_library "phy_lib/tsmc090g phy_lib/tpzn90gv3" 在 02_compile.tcl: a. 多一行 set_power_prediction true 由於 CTS 尚未處理 (APR 才會處理 ), 所以要請 Tool 針對 Clock tree power 作估測! b. 合成的地方, 要將 compile 指令改成 compile_ultra ( 多加 -no_auto 即不要做 auto_ungroup 功能 ) 在 03_output.tcl: 多一行 write_parasitics -format reduced -output chip_syn.spef 提供給有需要用 PT-PX 的同學, 分析 power 使用! 4. Cell area = um 2, timing=9.7584ns(meet timing constraint 此值表示 APR 也可以達成的數值 ), Power=> dynamic: mw, leakage: uw (Power 比 lab3-1 略高是因為多了 clock tree 估測的 power 值 ) 從本 Lab 可以得知 : 1. 假若後段 APR 是使用 IC Compiler, 從 DC-T mode 提前告知本晶片 APR 後效能大約落在 ns! 2. 像 Lab3-1 有受到 WLM 不準確的影響會讓設計者以為只能跑到 90 幾 MHZ 但從 DC-T mode 可以看出本設計真實效能能上 100 多 MHZ 這便會讓非做到 100MHZ 以上的同學不必再重新改架構也不必重新寫 Code! 可以看出 One-pass Timing Closure Design Flow 的重要性! S.S. WANG / Lab 3-10

22 Labs: Retiming & Increase Pipeline Stage Lab 4: Register Retiming These labs take approximately 0.5 hour to complete S.S. WANG / Lab 4-1 Lab 4: Retiming Registers How can we speed up the arithmetic? by retiming registers out <= (a*b)/c; a b c div out Target: 333MHZ clock period = 3.00 ns slack violation: S.S. WANG / Lab 4-2

23 Getting Start 1. Enter the directory SYNOPSYS/lab4 unix% cd ~/SYNOPSYS/lab4 2. Examine the script.tcl file in your unix shell unix% gedit script.tcl & What s the clock period in script.tcl file? 3. Invoke the Design Vision and execute script file as well unix% dv -f script.tcl 4. Explore the schematic Create Design Schematic to see the result after synthesis. 5. Check the area, timing Select top Design Report Area Timing Report Timing What's the cell area of this design? What s the timing of this design? Does the design meet timing constraint?, slack= What's the timing of MUL?, meet timing constraint?, slack= What's the timing of DIV?, meet timing constraint?, slack= If the slack of multiplier and divider are negative, whether this design can still improve timing by retiming command? Why? S.S. WANG / Lab 4-3 Register Retiming 6. Save the synthesis result before retiming design_vision> write_file format ddc -hier output muldiv_before_retiming.ddc 7. Retiming Register (DC-Ultra Instruction) design_vision> optimize_registers 8. Explore the schematic Create Schematic to see the result after retiming registers. 9. Check the area, timing Design Report Area Timing Report Timing What's the cell area of this design? What s the timing of this design? Does the design meet timing constraint?, slack= Now, what s the timing of output stage?, slack= S.S. WANG / Lab 4-4

24 Increase Pipeline Stage 10. If we want to improve the performance of at least 450MHZ, then how to achieve this goal? 11. Modify script.tcl file, ( 不想修改者可以直接用 script_m.tcl 執行 ) a. read_file -format verilog muldiv_m.v b. clock period to 2.20 ns c. compile -boundary_optimization -map_effort high 12. Invoke the Design Vision and execute script file again unix% dv -f script_m.tcl 13. Before retiming, check synthesis result What's the cell area of this design? What s the timing of input stage? What s the timing of output stage? What s the timing of MUL & DIV? 14. Retiming Register design_vision> optimize_registers 15. After retiming, check retiming result What's the cell area of this design? What s the timing of input stage? What s the timing of output stage? What s the timing of MUL & DIV? What did you get? S.S. WANG / Lab 4-5 Lab 4 Answers / Solutions (1/5) ns 5. cell area= um 2 timing= 4.63 ns No slack= ns MUL timing = 3.39 ns (report_timing -through mult_11_s2/* 即可查出 ) No MUL slack = ns DIV timing = 4.63 ns (report_timing -through div_13_s2/* 即可查出 ) No DIV slack = ns Yes, 因為本設計 DIV 的下一級 pipeline stage( 即 output stage) 還有多出 1.98ns 的空間使用 Retiming 足以將 MUL & DIV 兩者目前缺乏的 timing 補足! ( 雖然 (0.39ns+1.63ns)> 1.98ns 差不到 0.05ns 關於這只要在作個簡單 Timing OPT 一下即可滿足規格! 後續動作作下去便知!) PS: Output Stage slack => 可以用 report_timing -to [all_outputs] 指令查看出來! S.S. WANG / Lab 4-6

25 Lab 4 Answers / Solutions (2/5) 9. cell area= um 2 timing= 3.00 ns Yes, meet timing constraint slack = 0.00 ns (DC 只需花個幾秒鐘就改善了 56.33% 效能! 這是就算使用 compile_ultra timing 永遠也達不成的境界!) output stage timing = 3.00ns slack = 0.00 ns ( 可以用 report_timing -to [all_outputs] 指令查看出來!) Retiming 後的電路結構與 Timing 分布如下 : ( 註 : input stage 可以用 report_timing from [all_inputs] 看出! 請自行試驗!) MHZ 達成目標! S.S. WANG / Lab 4-7 Lab 4 Answers / Solutions (3/5) 10. 因為本設計已用 Retiming 最佳化過假若又要大幅提升效能至 450MHZ 最快方法就是將原本設計由 3- stage pipeline 提升到 4-stage pipeline 修改 RTL Code 如下 : ( 懶得改的同學可以直接使用 muldiv_m.v) 修改完 RTL Code 其電路架構圖如下頁 S.S. WANG / Lab 4-8

26 Lab 4 Answers / Solutions (4/5) 修改後此時電路結構會像 4-stage Pipeline 結構 : 想達成 450MHZ 目標 Retiming 後其電路結構 &Timing 約略如下 : 目標達成 450MHZ S.S. WANG / Lab 4-9 Lab 4 Answers / Solutions (5/5) 13. cell area= um 2 input stage timing = 0.65ns ( 這區域沒有 comb 但卻被 input delay & setup time 用去 ) output stage timing = 1.11ns ( 這區域沒有 comb 但卻被 clk-to-q & output delay 用去 ) MUL stage timing = 3.06ns DIV stage timing = 4.12ns 15. cell area= um 2 input stage timing = 2.15ns ( 這區域原先沒有 comb 現在有 MUL 的 Cell) output stage timing = 2.20ns ( 這區域原先沒有 comb 現在有 DIV 的 Cell) MUL stage timing = 2.20ns DIV stage timing = 2.20ns 是的 450MHZ 目標輕鬆達成! 從本實驗可以看出當 Pipeline 級數越多效能往上成長空間便越大因此同學可善用此概念寫 Code 時就盡量多增加 Pipeline 級數 Timing 收斂便會越容易有時還可以因級數多效能越容易達成總面積反而較低! 因為你有來上課學會了 Retiming 這功能將會永遠伴隨著你千萬別讓這功能睡著了 ~ 另外本 Lab 你也得到一個概念如下 : Q: 為何我在還沒切割 pipeline 之前就已經知道 4-stage pipeline 可以達到 450MHZ? A: 因為 (MUL + DIV) 的 Delay = = 8.02ns ~= 8.00ns (page Lab4-2 有寫 ) 假若分成 4-stage pipeline stage 效能可提升 4 倍因此每一級極限是 8.0/4 =2.0ns 但要考量 FF setup time & clock-to-q => 大約 0.2ns ( 此值可能更大但可以請 DC 作優化即可!) 因此 2.0ns + 0.2ns = 2.20 ns => 超過 450MHZ ( 此效能算是本題 4-stage 的極限了!) S.S. WANG / Lab 4-10