PWRficient Architecture in Critical Embedded Systems

Transcription

1 PWRficient Architecture in Critical Embedded Systems Breakthrough Performance/Watt Multicore Processor Peter Bannon VP of Architecture and Verification Bus & Boards, 2007 January 15 th, /15/07 Copyright P.A. Semi, Inc.--Bus and Boards

2 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Agenda The Power Problem PWRficient Platform Processors PWRficient 1682M platform processor PA6T core CONEXIUM coherent interconnect architecture ENVOI I/O System Frequency & Power Summary Example System Designs Low Power Design Conclusion

3 The Power Problem 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards

4 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Energy Efficiency is a Dominant Industry Theme We are at the point of new wealth creation when it comes to green technology Customers continue to demand solutions that focus on low-power consumption and quieter operation. Bill Joy, co-founder, Sun Microsystems Bob Brewer, corporate vice president, Desktop Division, AMD; from Dec 2006 press release The industry is going through the most profound shift in decades, moving to an era where performance and energy efficiency are critical in all market segments and all aspects of computing Paul Otellini, President & CEO Intel IDF, September 2006 P.A. Semi s green contribution: the world s most power-efficient high-performance processor

5 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Useful Power Is Decreasing 140 Useful power peaked in Power Leakage

6 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards The Escalating Power Problem Power Density Shrinking device geometries provides Faster gates Increased density BUT Capacity Gap Moore s Law means more power Area/Gate 250nm 180nm 130nm 90nm 65nm Process Technology 45nm EXCESSIVE POWER DISSIPATION LIMITS USABLE GATE CAPACITY

7 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Year Operating Cost vs. Server Cost Yr. Operating Cost Server Cost

8 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Choosing Power Over Ultimate Performance Old design point Watts New design point Performance Look for the exponential opportunities in power/performance Give up some performance for substantial power decrease

9 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Design Choices for Low Power Design choices at several levels favor low power CMOS process target Circuit design style and sizing Micro-architecture features Integration Saves interface power Management Voltage/frequency scaling Multiple power planes for optimal voltage selection per region Clock gating to reduce power of idle circuits Active and pre-charge standby modes in DRAM array PCIe power saving modes Nap and Sleep modes for CPU

10 PWRficient Family Overview Platform Processor 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards

11 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards P.A. Semi Introduction Santa Clara-based fabless processor company Developing Power Architecture TM microprocessors under license from IBM Industry veterans lead 150-strong team Pioneering methodology for high-performance, low-power design Founded in 2003, broke out of stealth mode in October 2005 Started design in September 2004 Unveiled PWRficient TM Platform Processors at MPF 2005 Now sampling family of high-performance, 64-bit, multicore SoC devices High-speed I/O integration Fabricated on 65nm technology Target markets Telecom, datacom, storage Military/aerospace embedded computing and control Vision to dramatically reposition the performance per watt experience for high-performance embedded computing.

12 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Power Architecture Processors (PowerPC) Will be in 50% of the world s automobiles by 2007 Runs 4 of the world s top 5 fastest supercomputers and 44 of the top 100 Dominant in major embedded markets automotive control networking & communications gaming consoles 64% of VME and CompactPCI SBC s North America and Europe (Source: VDC)

13 PWRficient Family PA6T core the CPU Power Architecture compliant, 64-bit, high-performance FPU & VMX 2GHz worst-case power dissipation Provides a high-performance alternative to leverage existing Power Architecture software (from IBM, Freescale, AMCC) CONEXIUM the on-chip coherent interconnect Scalable cross-bar interconnect 1 8 SMP cores 1 or 2 L2 caches, sized 512KB 8MB bit DDR2 memory controllers ENVOI the I/O system SERDES I/O PCI Express TM, XAUI, SGMII, SATA Offload engines TCP/IP, iscsi, cryptography, and RAID Support I/O Boot bus, UARTs, SMBus, GPIOs 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards

14 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards PWRficient PA6T-1682M Block Diagram DDR2 Controller 64KB I-Cache 64KB D-Cache PA6T 2GHz Core 2MB L2 Cache 64KB I-Cache 64KB D-Cache PA6T 2GHz Core DDR2 Controller CONEXIUM Interchange Power Control System Control Interrupt/GPIO TTM* PTM I/O Cache Bridge DMA Offload Engines SMBus (3) UART (2) Boot Bus Octal PCI Express Dual 10GbE XAUI Quad GbE SGMII ENVOI Intelligent I/O Configurable SERDES (24) *Transaction trace memory Peripheral trace memory

15 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards PWRficient PA6T Core Instruction Fetcher/Decoder Branch Prediction I Cache MMU Instruction Scheduler ALU VMX Unit FPU D Cache Reg File LSU BIU Power Architecture rev GHz 64-bit core with FP and VMX Hypervisor and virtualization support 64KB L1 I Cache & 64KB D Cache Idle and sleep modes 11M logic transistors Super-scalar, out-of-order design Quad fetch into 64-entry scheduler Issue up to 3 per cycle Strongly ordered memory model Issue out of order, retire in order 15 transactions in flight Max Power 2.0GHz ( thermal virus ) Performance Estimated 4,400 Dhrystone MIPS per core

16 Processor Pipeline Multi-Issue, Out-of-Order, Superpipelined IP IF IC DE UC MP SE SP IS RR AL AD RT WB AG TR DC DD RT WB Reduced instruction issue IERAT width to save power ~ N 2 to N 3 Next Line uierat I-Cache RSB TAP Select Taken Not Taken Target Dec Predicted Target useq udec Map Eval RF Map Dep Map Increased branch Pick 0 Pick 1 Pick 2 Issue Micro Op Buffer Int RF CR BR Integer Integer/Br 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards FPU RF VMX RF Addr Gen prediction resources to reduce false speculation FPU Arithmetic 8 FPU Compare 4 VMX Float 8 VMX Complex Integer 6 VMX Permute 2 VMX Easy Int 2 D ERAT SLB TLB HTW D-Cache Load/Store Queue Longer pipeline to accommodate slower wire delays MRB SNP Dup Tag CONEXIUM Data Addr

17 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards DDR2 Memory Controller ~5 Watts for active DRAM rank ~1 Watt for standby DRAM rank DRAM is a significant percentage of system power SOC 13 Watt typical 2 x 2 DIMM memory is ~12 Watts DRAM controller manages power Extensive clock gating within the controller Use of DDR2 power saving modes Precharge standby Active standby Sorts requests to maximize power saving DDR2 DDR2 PWRficient 10GbE Ports DDR2 DDR2

18 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards ENVOI Intelligent I/O Interoperability between PCI Express, packets, DMA, and memory Centralized DMA model Shared resources saves area and power, which enables integration Idle functions are clock gated or powered off CONEXIUM Interchange I/O Cache Bridge DMA, Offload 8 x PCI Express 2 x 10GbE XAUI 4 x GbE SGMII ENVOI Intelligent I/O Configurable SERDES 24 multi-mode SERDES Boot time configurable Flexible mapping to MACs & PCI Express

19 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Server-Class Reliability Features Guiding principles Arrays protected based on predicted soft error rates Machine check architecture logs all detected errors Interrupt notification based on programmable thresholds Error propagation ensures that erroneous data is never used I/O protocol engines provide in-band and/or out-of-band error notification where possible per protocol definition ECC protection L1 data cache data L2 tags and data I/O cache and buffers DDR memory controller supports ECC memories Includes scrubbing engine Combined CRC/ECC for single bit correct, double detect, chip fail detect Parity protection CONEXIUM bus L1 instruction cache tags and data L1 data cache tags

20 Example System Block Diagrams 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards

21 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Advanced Mezzanine Card (AMC) RJ11 Front Panel Hot Swap UART XAUI Compact Flash PWR ficient LPC Flash DDR2 DDR2 UART IPMI µc SGMII 4x PCIe 8x PCIe SM Bus Rear Card Edge High-performance, low power Dual-core 2GHz under 40W in a single-width mid-size module Flexible I/O options Support varying widths of PCIe to card edge Support XAUI or SGMII to the card edge Support GbE or XAUI to the front panel Multiple boot options LPC flash SPI flash

22 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards ATX form-factor Motherboard Extensive I/O 2x USB USB OTG 2x GbE JTAG 2x UART Four PCI slots One x16 PCI Express One x4 PCI Express One x1 PCI Express PCIe 16x PCIe 4x PCIe 1x PCI Power PCI 32/33MHz Two GbE ports Separate XAUI option card for x4 PCIe slot IDE port Memory sockets Four DIMM sockets CompactFlash socket DDR2 Boot ROM emulator socket Standard JTAG Emulators ROM Corelis JTAG controller WindRiver ICE and Probe IDE Compact Flash

23 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Higher-end fileserver/nas DDR2 DDR2 Backup battery Full Redundancy Requires use of SAS discs No single point of failure (for RAID discs) PCIe Links to SAS controller SGMII XAUI PWR ficient PCIe SAS PCIe/XAUI Link between CPUs Allows metadata log from one to other SGMII XAUI PCIe PWR ficient PCIe SAS Memory controller supports backup battery Can use memory for file log Care taken for reset and power fail DDR2 DDR2 Backup battery Assist engines TCP assist CRC engine or signatures for digest RAID XOR option

24 Low-Power Design 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards

25 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Power Efficient POWER IS FIRST-ORDER DESIGN PRINCIPLE > 25,000 gated clocks PADS CPU MC MC optimizes DRAM power Separate power rails for cores, I/O pads PADS CPU L2 L2 PADS L2 cache and I/O are coherent with core off Turn off unused I/Os IO SERDES PwrCtl Dynamic power-control hardware and software voltage/frequency management

26 Fine-Grained Clock Gating Reduces Dynamic Power 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Coarse-Grained Clock Gating % of Flops Clocked Normal Operation Thermal Virus Time

27 Device-Specific V dd Reduces Static and Dynamic Power 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Conventional approach Operate at 1.1V across entire process range Fast parts tend to be very leaky P.A. Semi approach Operate at device-specific optimal V dd Partition power plane for optimal voltage selection per region Enables full process range for power yield V 1.1V 1.1V 0.8V 0.9V 1.1V Leakage Power Dynamic Power

28 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Voltage/Frequency Scaling PA6T-1682M PA6T Core PA6T Core VID_CP0 6 VDD_CP0 VID_CP1 6 VDD_CP1 VRM VRM Multiple power planes for maximum control VID regulators for cores, SoC Support for either or both cores powered down Low power I/O coherent nap mode PA6T-1682M-FCN Max Freq 2.0GHz Typ 13W Max 25W SoC VID_SoC VDD_SoC VRM PA6T-1682M-FCG 1.5GHz 8W 15W PA6T-1682M-FCD 1.0GHz 6W 10W I/O coherent nap 2W* *PA6T-1682M-FCN nap power may be higher

29 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Comparison with 65nm 2GHz processors PWRficient 1682M takes less total power than competing support chipsets alone 3x - 4x advantage in total system power* compared to contemporary 65nm dual-core processors Reduced system cooling and chip count result in improved system reliability 120W 100W 80W 60W 40W 20W M 25W 2GHz 970MP Athlon64 x2 Core 2 Duo I/O (Northbridge, Southbridge, 10GbE MACs)

30 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Summary PWRficient processors set the bar for ultimate energy conservation at full performance Lowest total energy for a computation or transaction Power conservation a key initiative from architectural concept though design implementation High levels of integration enable low latency, high bandwidth interfaces to cache, memory, & IO

31 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards Contact P.A. Semi For further information, please visit P.A. Semi web site at: Kindly direct sales inquiries to: Full contact information: P.A. Semi, Inc Freedom Circle, Floor 8 Santa Clara CA USA Main: Fax:

32 Thank You The P.A. Semi name and the P.A. Semi logo and combinations thereof are trademarks of P.A. Semi, Inc. The Power name is a trademark of International Business Machines Corporation, used under license therefrom. SPECint and SPECfp are registered trademarks of the Standard Performance Evaluation Corporation (SPEC). All other trademarks are the property of their respective owners. 1/15/07 Copyright P.A. Semi, Inc.--Bus and Boards