Yield Is Everyone s s Issue. John Kibarian CEO, President and Founder PDF Solutions

Transcription

1 Yield Is Everyone s s Issue John Kibarian CEO, President and Founder PDF Solutions

2 Nanometer Technologies New Materials at Every Node 248nm Al-Cu TEOS 248nm + OPC Al-Cu FSG 248nm + OPC Cu FSG 193nm + OPC/PSM Cu Low-k 193nm + OPC/PSM Cu Low-k 193nm + OPC/PSM Cu Low-k Dual Poly Dual Poly Dual Poly Dual Poly/SiGe Dual Poly/SiGe Metal/Multigate SiO2 SiO2 SiO2 SiO2 SiON SiO2/SiON 3D SiO/SiN High-k Ti-Si Co-Si Co-Si Co-Si Ni-Si Ni-Si Ni-Si/TBD P-Epi P-Epi P-Epi Epi/SOI SOI/Strained silicon-sige FD-SOI/UTB- SOI *Red shows use for mainstream CMOS With With critical-area area and and feature-count doubling per per node, node, reaching the the same same yield yield requires twice twice the the manufacturing efficiency with with new new materials as as achieved d with with old old materials

3 New Materials and Complexity Drive Process-Design Integration ITRS node (ITRS) Max.# ASIC Transistors/cm 2 (ITRS) Litho Resist CD control (nm, 3sigma) 0.18-µm 20M nm 90M 7 90-nm 180M 5 65-nm 360M 3 Process-design complexity increasing at at each new node Major Material Changes none Cu Low-k Ni, SOI True SOC drives more complex IC functionalities New functionalities mandate more Process-Design Integration New process-modules for new materials create new yield loss mechanisms Billions of design features must be modeled, optimized, controlled Process margins inherently low as micro-electronics nano-electronics Systematic yield loss mechanisms, often not visually detectable, now dominant over visual defects

4 Process-Design Integration Issues Drive a Process-Design Yield Gap Limited Yield 100% 90% 80% 70% 60% 50% Critical Area Based (Metal, Poly) Feature Based (Contacts, Vias) ITRS Node (microns) Assumes Assumes data data from from ITRS ITRS 2001, 2001, with with the the following following additional additional per-node per-node assumptions assumptions from from PDF s PDF s client client engagement engagement history: history: ASIC Chip area +10%; # Metal layers increasing ASIC Chip area +10%; # Metal layers increasing Metal Area +2x per layer; -55% in Fail Rate Metal Area +2x per layer; -55% in Fail Rate # vias +2x; -45% in Fail Rate # vias +2x; -45% in Fail Rate # contacts +2.5x; -45% in Fail Rate # contacts +2.5x; -45% in Fail Rate Process-Design Yield Gap Contact Contact fail fail rates rates must must be be less less than than 3 3 ppb ppb Via Via modules modules fail fail rates rates must must be be less less than than 2 2 ppb ppb Need Need a a process process window window that that spans spans layout layout variations variations Capability exists to reduce contamination limited yield Visible defects Random defect density but Feature limited yield now dominates functional yield loss mechanisms Non-visible defects Process-design systematics New capabilities needed to achieve yields

5 New Key Process Elements will Increase Design-Yield Gap Issues 90nm Backend integration issues LowK: stress and rel CMP - multi-layer issues Product ramp issues Yield-performance tradeoffs 65nm Litho Layout, tool, OPC/PSM integration issues Front end/transistor Layout dependent performance Product ramp issues Parametric control 45nm Litho Layout, eqp, OPC/PSM integration issues Front end/transistor New transistor architectures Product ramp issues Reliability control

6 To Resolve This Growing Gap Yield is Everyone s Issue Prior to 130nm Yield was driven primarily by Product Engineers Implementation was done primarily by the Fab Design Teams participation was non existent At 130nm and beyond, Process-Design Integration Issues require all elements to work in tandem to achieve yields necessary to hit product volumes and business profits The industry is realizing the issue, what is needed are solutions that: Are standardized to allow rapid implementation Consider specific process- design interactions Grounded in the reality of 2-3 ppb failure rates Have unique business models ensuring the provider is aligned to not only pointing out issues but helping resolve them

7 PDF Solutions PDF Solutions is the leading provider of Process-Design Integration technologies and services Close the Design-to-Silicon-Yield gap Create more manufacturable ICs, more capable processes Work side-by-side with customers to achieve measurable results

8 Major Elements PDF Solutions Offering Integrated Yield Ramp (IYR) Solution Helps processes ramp to yield faster, historically 2X faster Provides an infrastructure to help maintain yield improvements throughout the life of the process pdfx Design for Manufacturability Environment Provides designers with the ability to make yield trade offs Provides process aware DFM capability to designer New Solutions for the Product Engineer datapower Yield Management System WAMA wafer level DFM

9 PDF Process-Design Integration Process-Design Integration knowledge base CV Infrastructure Process Benchmarks Failure Analysis Design Benchmarks Layout Sensitivites Fab and Test Fab Data datapower Filtered Fab Data pdfastest pdcv CV test chips Layout Dependant Models Fail Rates Performance Variability Module Sensitivities Product Design Analog Circuit Surfer Digital pdfx WAMA YRS Module Priorities Product Hot Spots Yield Entitlement Layout Statistical Spice Models Yield and Variability Models Optimized Shotmap Product Analysis Process Optimization Yield Learning Design Optimization

10 Solution: Integrated Yield Ramp Process-Design Integration knowledge base CV Infrastructure Process Benchmarks Failure Analysis Design Benchmarks Layout Sensitivites Fab and Test Fab Data datapower Filtered Fab Data pdfastest pdcv CV test chips Layout Dependant Models Fail Rates Performance Variability Module Sensitivities Product Design Analog Circuit Surfer Digital pdfx WAMA YRS Module Priorities Product Hot Spots Yield Entitlement Layout Statistical Spice Models Yield and Variability Models Optimized Shotmap Product Analysis Process Optimization Yield Learning Design Optimization

11 Integrated Yield Ramp (IYR) Solution Integrated Yield Ramp (IYR) Solution is the linchpin to PDF s ability to drive improved yields The IYR Solution is comprised of 3 major elements Technology: Integrated Technology Infrastructure Process: Patented Process-Design Integration Methodology People: PDF Team integrated with Client s organization, measured to common goals IYR Solution is customized to Each process node Each customers specific process implementation

12 IYR Patented & Proven Methodology Pred Module Yield Poly all poly 0.99 M1 shorts 0.95 M2 shorts 0.96 M3 shorts 0.98 Contact N+AA 0.97 Contact P+AA 0.98 Contact N+Contact 0.98 V2 Borderless 0.90 V2 Border 1.00 V3 all 0.99 Parametric VthP 0.97 Total 0.70 Product Layout Analysis Functional & Parametric Yield Modeling CV-based Module Characterization Process split and validation Yield Gap, Yield Loss Pareto and Yield Issue Prioritization Root Cause Hypotheses Localization, Visualization Product Data Filtering, Modeling Product Manufacturing Data Process split and validation

13 Yield Pareto Issue vs. Improvement vs. Time Defect Process Problems Equipment Problems Mechanism Apr Jul Aug Sep Oct Nov Dec Jan Now Random Defect Limited Yield 48% 48% 55% 60% 62% 72% 67% Functional 70% LY 71% Systematic Contact Open 100% 96% 96% 96% 96% 96% 96% 96% 100% 100% Random Defect Limited Yield DRAM process improvements 40% 100% 100% 100% 100% 100% 100% 100% 100% Systematic Contact Open BEOL PDF topography Yield Ramp Team 95% 80% 80% 80% 80% 89% 100% 100% 100% 100% DRAM process improvements PID Issue 90% 90% 90% 90% 100% 100% 100% 100% 100% CMP Process identifies condition and BEOL Topography 90% 100% 100% 100% 100% PID Issue 60% DRAM systematic 82% 82% 86% 81% 85% 100% 100% quantifies signatures CMP Process condition DRAM wafer-edge parametric 95% 95% 95% 95% 93% 92% 90% 90% 100% DRAM systematic Wafer for for bin key X center yield fail issues 69% 40% 69% 69% 100% 100% 100% 100% 100% 100% DRAM wafer-edge parametric DRAM bin Y (scanner Z) 96% 100% 100% 100% 100% 100% 100% Front-half with advanced of lot yield loss (eq tools Wafer bin X center fail Q) 20% 98% 98% 100% 100% 100% DRAM bin Y (scanner Z) DRAM failure (eq W) 94% 94% Center and die methods 100% 100% 100% 100% 0% DRAM failure (eq W) Random wafer equipment dependency Center die 96% 98% 98% 98% Apr Jul Aug Sep Oct Nov Dec Jan Now Front-half of lot yield loss (eq Q) Random wafer equipment dependency Functional LY 10% 22% 20% 32% 37% 48% 48% 58% 65% Speed LY 50% 50% 80% 80% 93% 96% 96% 95% 97% Total Yield 5% 11% 16% 26% 35% 46% 46% 55% 63%

14 Client Results High Volume Game Chip Product Product introduction introduction percentage percentage points points over over baseline baseline Mature Mature yield yield 5 5 percentage percentage points points over over baseline baseline Estimated Estimated cost cost savings savings > US$100 million > US$100 million Data shown starts at mass production Yield Improvement Performance with PDF Baseline (previous node without PDF) Time Program started during integration Length of integration phase equivalent for both nodes Customer has has engaged with PDF on on all all subsequent process nodes Actual data printed with permission

15 Solution: Process-Aware DFM Process-Design Integration knowledge base CV Infrastructure Process Benchmarks Failure Analysis Design Benchmarks Layout Sensitivites Fab and Test Fab Data datapower Filtered Fab Data pdfastest pdcv CV test chips Layout Dependant Models Fail Rates Performance Variability Module Sensitivities Product Design Analog Circuit Surfer Digital pdfx WAMA YRS Module Priorities Product Hot Spots Yield Entitlement Layout Statistical Spice Models Yield and Variability Models Optimized Shotmap Product Analysis Process Optimization Yield Learning Design Optimization

16 pdfx Product Overview Verification Client Design Flow Architectural Design Logical Design Physical Design pdfx DFM Software Technology Kit Yield Gap Estimator Models Yield Optimizer Extended IP Standard IP Platform Optimizes to product-specific objectives within design constraints Die cost: best Good Die per Wafer (GDPW) Yield variability: best process window for yield Performance variability: best process window for performance Target Manufacturing Date Range: best solution for the process maturity

17 Delivering DFM Results DBYI Service Results Client 1 : IDM 0.13u CMOS technology Client 2 : IDM 0.15u edram technology pdfx Service Results Client 3 : Fabless 0.13u CMOS technology pdfx Results Client 4 : IDM 0.13u CMOS technology Client 5 : Fabless 0.13u CMOS technology Chang e in Good Die p er W afer ( % ) 16% PDF"DBYI" SERVICES CLIENT pdfx 14% 12% 10% 8% 6% 4% 2% 0% Client 1 Client 2 Client 3 Client 5 Client 4 Based on simulated results over the life of each product.

18 Solution: Volume Manufacturing Process-Design Integration knowledge base CV Infrastructure Process Benchmarks Failure Analysis Design Benchmarks Layout Sensitivites Fab and Test Fab Data datapower Filtered Fab Data pdfastest pdcv CV test chips Layout Dependant Models Fail Rates Performance Variability Module Sensitivities Product Design Analog Circuit Surfer Digital pdfx WAMA YRS Module Priorities Product Hot Spots Yield Entitlement Layout Statistical Spice Models Yield and Variability Models Optimized Shotmap Product Analysis Process Optimization Yield Learning Design Optimization

19 datapower YMS Platform Worksheet Analysis Environment MES/WIP Equipment Metrology Events Defect PCM/E-test Sub-Cons Wafer Sort SFC Assembly Final Test Bitmap Preprocessors Optional IFF Data Readers ASCII Binary Defect Format Files Integrated database Financials ERP Batch Manager database datavue report list Search: F olders Interactive Web Reports home new report scheduler Administrator John Q. Miller November 02, 2002 [11:25:44 local time] update browse R eports unsubscribe manage By: Author subscribe SQL ASCII External Software datavue home new report scheduler Administ rator J ohn Q. Miller November 02, 2002 [11:25:44 local time] templates report builder publish Collect & Manage Data Analyze & Report

20 datapower Drill-down Analysis Example Bin Pareto by Product & Lots Drill-down to Bin Stacks by Wafer Drill-down to Wafer Map

21 WAMA Wafer Level DFM Customer s vs. WAMA Placement Actual Customer Layout Actual WAMA Layout Good Die increase 4% Gross Die per wafer = 433 Good Die per wafer = 327 Gross Die per wafer = 439 Good Die per wafer = 341

22 Conclusion Resolving Process-Design Integration issues is critical to success in the nanometer-era Success requires involvement by all product functions Product Functions need the proper methodologies and tools Are standardized to allow rapid implementation Consider specific process-design interactions Grounded in the reality of 2-3 ppb failure rates A partner whose business model is tied to their success At 90nm and Beyond, Yield is Everyone s Issue