PowerPC 405 GP Overview

Transcription

1 PowerPC 405 GP Overview Marcelo T Pereira LISHA/UFSC trier@lisha.ufsc.br October 1, 2002 October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 1

2 Khomp Plataform Software/Hardware Integration UART UART ENERGY ETHERNET PCI CPLD FLASH PPC405GP GENERIC BUS - ROM Boot GENERIC BUS - E1 16bdata- 23b address- jtag - serial bus - 96pin DSP Serial BUS FPGA I/O - E1 SDRAM SDRAM FPGA DSP October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 2

3 PPC405GP - Logical Architecture October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 3

4 PPC405P - Overview 2 Cache types 16KB Instruction Cache transfer 1 or 2 instructions 8KB Data Cache transfer 1,2,3,4 or 8 bytes/cicle 5-stage pipeline 3 timers Programmable Interval Timer PIT Fixed Interval Timer FIT Watchdog Timer MMU - 4GB address space Translation of logical into physical address On-Chip Memory - 4KB Device Control Register Bus - DRC Bus Access and Status of peripheral registers October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 4

5 PPC405GP - Registers Grouped by categories: General Purpose Registers - GPRs Special Purpose Registers - SPRs Time Base Registers - TBRs Machine Status Register - MSR Condition Register - CR Device Control Registers - DCRs Memmory Management Input/Output - MMIO Access to register could has different instructions October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 5

6 PPC405GP - Registers General Purpose Registers - GPRs - 32 bits Special Purpose Registers - SPRs - 32 bits Special commands ex: mtspr, mfspr Count Register - CTR - decrement in loops Link Register - LR - return address Fixed Point Exception Register - XER - overflow/carry SPR General[0-7] - SPRGn - temporary data for context Processor Version Register - PVR - read only October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 6

7 PPC405GP - Registers Condition Register - CR[0-7] - 8 fields of 4bits LT, GT, EQ, SO - bits 0, 1, 2, 3 respectively Time Base - 64 bits - TBL/TBU TB Lower (32b) / TB Upper (32b) - mftb, mtspr Machine State Register - MSR - 32 bits mtmsr, mfmsr - control interrupts, debug, etc Device Control Registers - DCRs - 32 bits mtdcr, mfdcr - on-chip buses, peripherals Access: Direct (ex DMA) or Indirect (ex EBC, SDRAM) October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 7

8 Device Control Register Defined architecturally outsite the processor core The IBM PowerPC Embedded Environment defines the existence of DCRs address space and functions But it doesn t define any DCR (physically) Indirect Access 1 Write an offset to an address DCR 2 Read data from or write data to a data DCR Example: 1 EBC Config Address - r/w - DCR number = 0x010: 0x00 = Bank Configuration 0 0x01 = Bank Configuration 1 2 EBC Config Data - r/w October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 8

9 Memory-Mapped Input/Output Registers Accessed using load/store instructions Mapped in Address Space Access: Direct (UART) or Indirect (PCI) Ex1: Direct access UART 0-0xEF Interrupt Identification Register Ex2: Indirect access PCI - PCI Config Address - r/w - 0xEEC x01 - PCI Vendor ID 0x03 - PCI Device ID PCI Config Data - r/w - 0xEEC00004 October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 9

10 4 data types: Data Types and Alignment Bytes - 8bits Halfwords - 16bits Words - 32 bits Strings - 1 to 128 bytes Data represention is independent of alignment issues Instruction is always word-alignment Byte Ordering - special command: byte-reverse word Big Endian MSB LSB Litlle Endian LSB MSB October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 10

11 Instruction Set Storage Reference (load, store) Arithmetic (add, subtract, negate, multiply, divide, etc) Logical (and, or, xor, not, nand, etc) Comparison (compare, compare immediate, etc) Branch (branch, branch to LR, etc) Condition Register Logical (cand, cror, etc) Rotate (rotate, shift left, etc) October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 11

12 Instruction Set Shift (shift left, shift right) Cache Management (invalidate, flush, store, etc) Interrupt Control (move from/to MSR, return from interrupt) Process Management (system call, move from/to DCR, etc) October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 12

13 Instruction Set - Example (branch) Uncondicional Branch (b) b[l][a] <addr> = b, bl, ba, bla b = branch: PC=PC+<addr> l = link register: LR=PC a = absolute: PC=<addr> <addr> = signed address: 26bits - max (+/-)32MB Condicional Branch (bc) - 16 bits - max (+/-)32KB October 1, 2002 Marcelo T Pereira ( lisha ufsc br) 13