Caching Mechanisms for Mobile and IOT Devices

Transcription

1 Caching Mechanisms for Mobile and IOT Devices Masafumi Takahashi Toshiba Corporation JEDEC Mobile & IOT Technology Forum Copyright 2016 Toshiba Corporation

2 Background. Unified concept. Outline The first example: Flash as Main Memory. The second example: UFS Unified Memory Extension. The third example: Network to Flash caching.

3 Problem and Solution. BACKGROUND

4 Problems in IOT Many devices connected with the network. Complicated and heterogeneous access methods for contents in different layers. Memory CPU DRAM DRAM My device Storage Flash Flash Flash Network Network Remote devices

5 Solution: Caching The Single-level store (SLS) model. Everything mapped in a single virtual space. Access only by LOAD/STORE instructions. Memory Storage CPU Cache DRAM DRAM Cache Flash Flash Flash Single address space Network Network DRAM Flash I/O, etc.

6 Proposed Caching Mechanisms Flash to DRAM. Network to Flash. Network to DRAM. Everything to DRAM after all. Memory Storage CPU Cache DRAM DRAM Cache Flash Flash Flash Network Network

7 Single-Level Store (SLS). UNIFIED CONCEPT

8 Problems: Gap in Cost and Speed Results in Complicated Access L1 L2 L3/L4 DRAM/ MRAM Memory-like-SCM Storage-like-SCM Performance SSD Capacity SSD Archival SSD NL/Cold HDD Fast but expensive main memory: ~10 ns latency; ~$30 / 4 GB. LOAD/STORE READ/WRITE Complicated access: hierarchical and heterogeneous. Slow but cheap storage: ~100 ms latency (Flash), ~$300 / 500 GB (SSD), ~10 ms latency (HDD), ~$30 / 1 TB (HDD).

9 Layers are not Logical but Physical: - Turing Machine vs Today s Computer- Turing machine (A single layer) Just a single layer: Infinite tape. Today s computer (Many layers) Many layers. Some are visible / invisible. Turing Machine CPU core MMU L1 cache L2 cache R1 R2 Registers Infinite tape DRAM (Memory) SSD (Storage) SATA IF SSD controller SSD MMU DRAM cache NAND flash Remote storage

10 Solution: Single-Level Store (SLS) L1 L2 L3/L4 DRAM/ MRAM LOAD/STORE for coding Memory-like-SCM Storage-like-SCM Performance SSD Simple access: flat and homogeneous. Capacity SSD Archival SSD NL/Cold HDD READ/WRITE in background

11 Single-Level Store (SLS) is Like Automatic-Transmission Car Complicated but faster for experts Easier and faster for most users

12 Ultimate Goal: Network-transparent Virtual Multi-core Computer Multi-core MPU segment thread segment The same abstract model. MPU Distributed Computer MPU segments thread Local Memory Local Memory Main Memory Huge Address Space

13 Flash as Main Memory. THE FIRST EXAMPLE: FLASH TO DRAM CACHING

14 Flash Memory as Main Memory Goal: LOAD/STORE for accessing flash memory. Problems: short memory cell lifetime and long access latency. LOAD/STORE CPU Data Flash memory Slide 14

15 Flash Memory as Main Memory Solution: caching on DRAM. By introducing Storage Memory Management Unit (SMMU). LOAD/STORE Data CPU Data DRAM SMMU Flash memory READ/WRITE upon page fault Slide 15

16 Prototype of Flash-based Main Memory FPGA implementation of SMMU. Flash memory PCI Express to host DRAM FPGA for SMMU LOAD/STORE Data CPU Data DRAM SMMU READ/WRITE upon page fault Flash memory Slide 16

17 Extending Lifetime of Flash Memory 82% write-back reduction of cached data. Compression, priority based on data types. Good for 2 years of continuous usage Write-back traffic [MB/s] Elapsed time [sec] GB flash memory 128MB DRAM cache Video playback Naïve full write-back Write-back reduction Slide 17

18 UFS Unified Memory Extension. THE SECOND EXAMPLE: FLASH TO DRAM CACHING

19 Latency Problem of Flash Goal: Fast and low-cost access to flash memory. Problem: Flash Translation Layer (FTL) cache is slow and expensive for IoT devices. Address is translated in FTL to reduce No. of erase operation. Host Storage FTL data request DRAM + SMMU User data access Memory controller FTL cache FTL data User data access FTL Flash memory User data

20 Low-latency Access Using Host DRAM Solution: Move FTL cache to the host. Latency reduced by half. 270ms to 133ms. Host Storage FTL cache DRAM + SMMU FTL data request FTL data User data access Memory controller FTL cache User data access FTL Flash memory User data

21 Result of a Prototype Device (UFS) Random read [KIOPS] 100 Embedded SSD Our work Sequential read: 690MB/s Random read: 66.3KIOPS Sequential read [MB/s]

22 UFS Unified Memory Extension An optional feature of UFS 2.0. Device: JESD220-1 Host: JESD223-1 Standards are available from the JEDEC website. Cover pages

23 Mobile Peer-to-Peer. THE THIRD EXAMPLE: NETWORK TO FLASH CACHING

24 Spectrum Crisis Mobile traffic > network speed. Wireless communication bottleneck.

25 Solution: Caching to Flash Use neighbors flash as cache. A la CCN/NDN in the future. Efficient data relay. Reliable multicast. Low-interference multi-hop. cache cache cache cache cache

26 Reliable Multicast Unicast: reliable but not efficient. Multicast: efficient but not reliable. Repair request for reliability. Unicast Multicast Repair request

27 Low-Interference Multi-Hop Autonomous selection of relay nodes. Monitoring signal levels of others.

28 Simulation

29 Simulation Snapshot Proposed method Naïve method Source device

30 Simulation Result 7000 nodes in 50 sec (vs 1000 for naïve method). Conditions: 128kB data, IEEE n, 19.5Mbps. # of satisfied devices Proposed method 2000 Naïve method Elapsed time [sec] Slide 30

31 Uniform Concept for Mobile and IOT Devices. SUMMARY

32 Uniform concept. Summary Single-level store through the network. Upper layer as cache of lower layers. Examples. Flash to DRAM. Flash as main memory. UFS unified memory extension. Network to flash. Mobile peer-to-peer.