Computer Organization
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1 Computer Organization and Architecture Designing for Performance Ninth Edition William Stallings International Edition contributions by R. Mohan National Institute of Technology, Tiruchirappalli PEARSON Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo
2 Contents Online Resources 11 Preface 13 About the Author 21 Chapter 0 Reader's and Instructor's Guide Outline of the Book A Roadmap for Readers and Instructors Why Study Computer Organization and Architecture? Internet and Web Resources 27 PART ONE OVERVIEW 28 Chapter 1 Introduction Organization and Architecture Structure and Function Key Terms and Review Questions 36 Chapter 2 Computer Evolution and Performance A Brief History ofcomputers Designing for Performance Multicore, MICs, and GPGPUs The Evolution of the Intel x86 Architecture Embedded Systems and the ARM Performance Assessment Recommended Reading Key Terms, Review Questions, and Problems 82 PART TWO THE COMPUTER SYSTEM 87 Chapter 3 A Top-Level View of Computer Function and Interconnection Computer Components Computer Function Interconnection Structures Bus Interconnection Point-to-Point Interconnect PCI Express Recommended Reading Key Terms, Review Questions, and Problems 130 Chapter 4 Cache Memory Computer Memory System Overview Cache Memory Principles Elements of Cache Design 145
3 6 CONTENTS 4.4 Pentium 4 Cache Organization ARM Cache Organization Recommended Reading Key Terms, Review Questions, and Problems 169 Appendix 4A Performance Characteristics of Two-Level Memories 174 Chapter 5 Internal Memory Semiconductor Main Memory Error Correction Advanced DRAM Organization Recommended Reading Key Terms, Review Questions, and Problems 203 Chapter 6 External Memory Magnetic Disk RAID Solid State Drives Optical Memory Magnetic Tape Recommended Reading Key Terms, Review Questions, and Problems 240 Chapter 7 Input/Output External Devices I/O Modules Programmed I/O Interrupt-Driven I/O Direct Memory Access I/O Channels and Processors The External Interface:Thunderbolt and Infiniband IBM zenterprise 196 I/O Structure Recommended Reading KeyTerms, Review Questions, and Problems 282 Chapter 8 Operating System Support Operating System Overview Scheduling Memory Management Pentium Memory Management ARM Memory Management Recommended Reading Key Terms, Review Questions, and Problems 326 PART THREE ARITHMETIC AND LOGIC 331 Chapter 9 Number Systems The Decimal System Positional Number Systems The Binary System Converting Between Binary and Decimal 334
4 CONTENTS Hexadecimal Notation Recommended Reading Key Terms and Problems 339 Chapter 10 Computer Arithmetic The Arithmetic and Logic Unit Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic Recommended Reading Key Terms, Review Questions, and Problems 381 Chapter 11 Digital Logic Boolean Algebra Gates Combinational Circuits Sequential Circuits Programmable Logic Devices Recommended Reading Key Terms and Problems 423 PART FOUR THE CENTRAL PROCESSING UNIT 427 Chapter 12 Instruction Sets: Characteristics and Functions Machine Instruction Characteristics Types of Operands Intel x86 and ARM Data Types Types of Operations Intel x86 and ARM Operation Types Recommended Reading Key Terms, Review Questions, and Problems 463 Appendix 12A Little-, Big-, and Bi-Endian 469 Chapter 13 Instruction Sets: Addressing 13.1 Addressing Modes x86 and ARM Addressing Modes Instruction Formats x86 and ARM Instruction Formats Assembly Language Recommended Reading KeyTerms, Review Questions, Modes and Formats 473 and Problems 501 Chapter 14 Processor Structure and Function Processor Organization Register Organization Instruction Cycle Instruction Pipelining The x86 Processor Family 534
5 8 CONTENTS 14.6 The ARM Processor Recommended Reading Key Terms, Review Questions, and Problems 549 Chapter 15 Reduced Instruction Set Computers Instruction Execution Characteristics The Use of a Large Register File Compiler-Based Register Optimization Reduced Instruction Set Architecture RISC Pipelining MIPS R SPARC RISCVersus CISC Controversy Recommended Reading KeyTerms, Review Questions, and Problems 591 Chapter 16 Instruction-Level Parallelism and Superscalar Processors Overview Design Issues Pentium ARM Cortex-A Recommended Reading KeyTerms, Review Questions, and Problems 627 PART FIVE PARALLEL ORGANIZATION 633 Chapter 17 Parallel Processing Multiple Processor Organizations Symmetric Multiprocessors Cache Coherence and the MESI Protocol Multithreading and Chip Multiprocessors Clusters Nonuniform Memory Access Vector Computation Recommended Reading KeyTerms, Review Questions, and Problems 679 Chapter 18 Multicore Computers Hardware Performance Issues Software Performance Issues Multicore Organization Intel x86 Multicore Organization ARM 11 MPCore IBM zenterprise 196 Mainframe Recommended Reading KeyTerms, Review Questions, and Problems 709
6 CONTENTS 9 Appendix A Projects for Teaching Computer Organization and Architecture 713 A.l Interactive Simulations 714 A.2 Research Projects 716 A.3 Simulation Projects 716 A.4 Assembly Language Projects 717 A.5 Reading/Report Assignments 718 A.6 Writing Assignments 718 A.7 Test Bank 718 Appendix B Assembly Language and Related Topics 719 B.l Assembly Language 720 B.2 Assemblers 728 B.3 Loading and Linking 732 B.4 Recommended Reading 740 B.5 KeyTerms, Review Questions, and Problems 741 ONLINE CHAPTERS1 PART SIX THE CONTROL UNIT 19-1 Chapter 19 Control Unit Operation Micro-operations Control of the Processor Hardwired Implementation Recommended Reading KeyTerms, Review Questions, and Problems Chapter 20 Microprogrammed Control Basic Concepts Microinstruction Sequencing Microinstruction Execution Tl Recommended Reading KeyTerms, Review Questions, and Problems ONLINE APPENDICES Appendix C Hash Tables Appendix D Victim Cache Strategies D.l Victim Cache D.2 Selective Victim Cache 'Online chapters, appendices, and other documents are Premium Content, available via the access card at the front of this book.
7 10 CONTENTS Appendix E Appendix F Interleaved Memory The International Reference Alphabet Appendix G Virtual Memory Page Replacement Algorithms G.l Optimal G.2 Least Recently Used G.3 First-In-First-Out G. 4 Other Page Replacement Algorithms Appendix H H. l Recursion Recursive Procedures H.2 Activation Tree Representation H.3 Stack Processing H. 4 Recursion and Iteration Appendix I I. 1 Pipeline 1.2 Reorder Buffers Additional Instruction Pipeline Topics Reservation Tables 1.3 Tomasul o s Algorithm 1.4 Scoreboarding Appendix J J.l Linear Tape Open Technology LTO Generations J.2 LTO Format J.3 LTO Operation Appendix K DDR SRAM Appendix L L.l Protocols and Protocol Architectures Introduction L.2 The TCP/IP Protocol Architecture L.3 The Role of an Internet Protocol L.4 IPv4 L.5 IPv6 L.6 The OSI Protocol Architecture Appendix M Appendix N Scrambling Timing Diagrams Appendix O Stacks 0.1 Stack Structure 0.2 Stack Implementation 0.3 Expression Evaluation Glossary 745 References 755 Index 767
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