MM74HC595 8-Bit Shift Registers with Output Latches

Transcription

1 MM74HC595 8-Bit Shift Registers with Output Latches General Description The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power coumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contai an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pi for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to CC and ground. Features September 1983 Revised July 2004 Low quiescent current: 80 µa maximum (74HC Series) Low input current: 1 µa maximum 8-bit serial-in, parallel-out shift register with storage Wide operating voltage range: 2 6 Cascadable Shift register has direct clear Guaranteed shift frequency: DC to 30 MHz MM74HC595 8-Bit Shift Registers with Output Latches Ordering Code: Order Number Package Number Package Description MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC595N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table RCK SCK SCLR G Function X X X H Q A thru Q H = 3-STATE X X L L Shift Register cleared Q H = 0 X H L Shift Register clocked Q N = Q n-1, Q 0 = SER X H L Contents of Shift Register traferred Top iew to output latches 2004 Fairchild Semiconductor Corporation DS

2 MM74HC595 Logic Diagram (positive logic) 2

3 Absolute Maximum Ratings(Note 1) (Note 2) Supply oltage ( CC ) 0.5 to +7.0 DC Input oltage ( IN ) 1.5 to CC +1.5 DC Output oltage ( OUT ) 0.5 to CC +0.5 Clamp Diode Current (I IK, I OK ) ±20 ma DC Output Current, per pin (I OUT ) ±35 ma DC CC or GND Current, per pin (I CC ) ±70 ma Storage Temperature Range (T STG ) 65 C to +150 C Power Dissipation (P D ) (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260 C Recommended Operating Conditio Min Max Units Supply oltage ( CC ) 2 6 DC Input or Output oltage ( IN, OUT ) 0 CC Operating Temperature Range (T A ) C Input Rise or Fall Times (t r, t f ) CC = CC = CC = Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mw/ C from 65 C to 85 C. MM74HC595 DC Electrical Characteristics (Note 4) T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Symbol Parameter Conditio CC Units Typ Guaranteed Limits IH Minimum HIGH Level Input oltage IL Maximum LOW Level Input oltage OH Minimum HIGH Level IN = IH or IL Output oltage I OUT 20 µa Q H IN = IH or IL I OUT 4.0 ma I OUT 5.2 ma Q A thru Q H IN = IH or IL I OUT 6.0 ma I OUT 7.8 ma OL Maximum LOW Level IN = IH or IL Output oltage I OUT 20 µa Q H IN = IH or IL I OUT 4 ma I OUT 5.2 ma Q A thru Q H IN = IH or IL I OUT 6.0 ma I OUT 7.8 ma I IN Maximum Input IN = CC or GND 6.0 ±0.1 ±1.0 ±1.0 µa Current I OZ Maximum 3-STATE OUT = CC or GND 6.0 ±0.5 ±5.0 ±10 µa Output Leakage G = IH I CC Maximum Quiescent IN = CC or GND µa Supply Current I OUT = 0 µa Note 4: For a power supply of 5 ±10% the worst case output voltages ( OH, and OL ) occur for HC at 4.5. Thus the 4.5 values should be used when designing with this supply. Worst case IH and IL occur at CC = 5.5 and 4.5 respectively. (The IH value at 5.5 is 3.85.) The worst case leakage current (I IN, I CC, and I OZ ) occur for CMOS at the higher voltage and so the 6.0 values should be used. 3

4 MM74HC595 AC Electrical Characteristics CC = 5, T A = 25 C, t r = t f = 6 Guaranteed Symbol Parameter Conditio Typ Limit Units f MAX Maximum Operating MHz Frequency of SCK t PHL, t PLH Maximum Propagation C L = 45 pf Delay, SCK to Q H t PHL, t PLH Maximum Propagation C L = 45 pf Delay, RCK to Q A thru Q H t PZH, t PZL Maximum Output Enable R L = 1 kω Time from G to Q A thru Q H C L = 45 pf t PHZ, t PLZ Maximum Output Disable R L = kω Time from G to Q A thru Q H C L = 5 pf t S Minimum Setup Time 20 from SER to SCK t S Minimum Setup Time 20 from SCLR to SCK t S Minimum Setup Time 40 from SCK to RCK (Note 5) t H Minimum Hold Time 0 from SER to SCK t W Minimum Pulse Width 16 of SCK or RCK Note 5: This setup time eures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register. AC Electrical Characteristics CC = , C L = 50 pf, t r = t f = 6 (unless otherwise specified) T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Symbol Parameter Conditio CC Units Typ Guaranteed Limits f MAX Maximum Operating C L = 50 pf Frequency t PHL, t PLH Maximum Propagation C L = 50 pf Delay from SCK to Q H C L = 150 pf C L = 50 pf C L = 150 pf C L = 50 pf C L = 150 pf t PHL, t PLH Maximum Propagation C L = 50 pf Delay from RCK to Q A thru Q H C L = 150 pf C L = 50 pf C L = 150 pf C L = 50 pf C L = 150 pf t PHL, t PLH Maximum Propagation Delay from SCLR to Q H t PZH, t PZL Maximum Output Enable R L = 1 kω from G to Q A thru Q H C L = 50 pf C L = 150 pf C L = 50 pf C L = 150 pf C L = 50 pf C L = 150 pf MHz 4

5 AC Electrical Characteristics (Continued) Symbol Parameter Conditio CC T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Units Typ Guaranteed Limits t PHZ, t PLZ Maximum Output Disable R L = 1 kω Time from G to Q A thru Q H C L = 50 pf t S Minimum Setup Time from SER to SCK t R Minimum Removal Time from SCLR to SCK t S Minimum Setup Time from SCK to RCK t H Minimum Hold Time SER to SCK t W Minimum Pulse Width of SCK or SCLR t r, t f Maximum Input Rise and Fall Time, Clock t THL, t TLH Maximum Output Rise and Fall Time Q A Q H t THL, t TLH Maximum Output Rise & Fall Time Q' H C PD Power Dissipation G = CC 90 Capacitance, Outputs G = GND 150 pf Enabled (Note 6) C IN Maximum Input pf Capacitance C OUT Maximum Output pf Capacitance Note 6: C PD determines the no load dynamic power coumption, P D = C PD CC 2 f + I CC CC, and the no load dynamic current coumption, I S = C PD CC f + I CC. MM74HC

6 MM74HC595 Timing Diagram 6

7 Physical Dimeio inches (millimeters) unless otherwise noted MM74HC Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7

8 MM74HC595 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 8

9 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) MM74HC Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9

10 MM74HC595 8-Bit Shift Registers with Output Latches Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.