Lecture 17: Virtual Memory: Concepts

Transcription

1 CSCI-UA.2-3 Computer Systems Organization Lecture 7: Virtual Memory: Concepts Mohamed Zahran (aka Z) Some slides adapted (and slightly modified) from: Clark Barrett Jinyang Li Randy Bryant Dave O Hallaron

2 Physical Addressing CPU Physical address (PA) 4 Main memory : : 2: 3: 4: 5: 6: 7: 8:... M-: Data word Used by microcontrollers like those in Arduino, cars etc. Simple but fragile to program for: Buffer overrun in buflab corrupts Firefox memory!

3 Butler Lampson, co-inventor of PC All problems in CS can be solved by another level of indirection

4 Virtual Addressing CPU Chip CPU Virtual address (VA) 4 MMU Physical address (PA) 4 Main memory : : 2: 3: 4: 5: 6: 7: 8:... M-: Data word Used in all modern servers, desktops, and laptops

5 Why Virtual Memory (VM)? Simplified memory management Each process gets an ``exclusive linear address space Process Isolation Different processes have different virtual address spaces One process can t interfere with another s memory Uses main memory efficiently Use DRAM as a cache for the parts of a virtual address space

6 Address translation Key idea of VM: each process has its own virtual address space Strawman view of addr translation VA=x8 VA.. PA PA=x98 x8 x98 Valid address: [,2^32) for 32-bit machine [,2^64) for 64-bit machine invalid Valid address: [,2^m) depending on how much memory your machine has Granularity of mapping? Byte-level: Map each byte in VA to a byte in PA Page-level: Map each consecutive 2^p-byte address range in VA to a 2^p-byte address range in PA

7 Address Translation w/ a Page Page table base register (PTBR) How kernel tells h/w where to find the page table Table Virtual address n- Virtual page number (VPN) p p- Virtual page offset (VPO) Page table address for process Page table Valid Physical page number (PPN) PTE (page table entry) Valid bit = : page not in memory (page fault) m- p p- Physical page number (PPN) Physical page offset (PPO) Physical address

8 Page Table Base Register (PTBR) The operating system maintains information about each process in a process control block. The page table base address for the process is stored there. The operating system loads this address into the PTBR whenever a process is schedule for execution. Only the kernel can access PTBR

9 Address Translation: Page Hit CPU Chip CPU VA MMU 2 PTEA PTE 3 PA Cache/ Memory 4 Data 5 ) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor

10 Address Translation: Page Fault Exception 4 Page fault handler CPU Chip 2 PTEA CPU VA 7 MMU PTE 3 Cache/ Memory ) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in memory 4) Valid bit is zero, so MMU triggers page fault exception in kernel If VA is invalid, then kill process (SIGSEGV) If VA has been paged out to disk, then swaps in faulted page, update page table, resume faulted process

11 Speeding up Translation with a TLB VA->PA translation can be expensive One additional memory reference for every normal memory reference! Not too bad? Page table entries (PTEs) are cached in L like others PTEs may be evicted by other data references PTE hit still requires a small L delay Solution: Translation Lookaside Buffer (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages

12 TLB Hit CPU Chip TLB 2 PTE VPN 3 CPU VA MMU PA 4 Cache/ Memory Data 5 A TLB hit eliminates a memory access

13 TLB Miss CPU Chip TLB 4 2 PTE VPN 3 CPU VA MMU PTEA PA Cache/ Memory 5 Data 6 A TLB miss incurs an additional memory access (the PTE) Fortunately, TLB misses are rare. Why?

14 Reduce Page Table Size 4KB-page, 48-bit address space, 8-byte PTE Size of page table needed? * 2 3 = 2 39 = 52 GB Wasteful: most PTEs are invalid Solution: multi-level page table Example: 2-level page table Level table: each PTE points to a page table Level 2 table: each PTE points to a page Level Table... Level 2 Tables...

15 A Two-Level Page Table Hierarchy Level page table Level 2 page tables Virtual memory VP PTE PTE PTE 2 (null) PTE 3 (null) PTE 4 (null) PTE... PTE 23 PTE... VP 23 VP VP 247 2K allocated VM pages for code and data PTE 5 (null)... PTE 6 (null) PTE 7 (null) PTE 23 Gap 6K unallocated VM pages PTE 8 (K - 9) null PTEs 23 null PTEs 32 bit addresses, 4KB pages, 4-byte PTEs PTE unallocated pages VP unallocated pages allocated VM page for the stack

16 Why Two-level Page Table Reduces Memory Requirement? if a PTE in the level table is null, then the corresponding level 2 page table does not even have to exist. Only the level table needs to be in main memory at all times. The level 2 page tables can be created and paged in and out by thevmsystem as they are needed.

17 VM For memory management and protection For caching

18 Memory management and protection Each process has an exclusive VA space One process cannot overwrite another one s memory! Sharing among processes Map different virtual pages to the same physical page Virtual Address Space for Process : VP VP 2... PP 2 Physical Address Space (DRAM) PP 6 (e.g., libc code, kernel) Virtual Address Space for Process 2: VP VP 2... PP 8...

19 Simplified Linking and Loading Linking Each program has similar virtual address space Code, stack, and shared libraries always start at the same address Loading execve()causes kernel to allocate virtual pages Kernel copies.text and.data sections, page by page, from disk to memory xc x4 x848 Kernel virtual memory User stack (created at runtime) Memory-mapped region for shared libraries Run-time heap (created by malloc) Read/write segment (.data,.bss) Read-only segment (.init,.text,.rodata) Unused Memory invisible to user code %esp (stack pointer) Loaded from the executable file

20 Memory Protection How to protect shared pages from corruption? E.g. bad process overwrites shared kernel code/data, shared libc code etc. Extend PTEs with permission bits Process i: Process j: VP : VP : VP 2: SUP No No Yes READ Yes Yes Yes WRITE No Yes Yes Address PP 6 PP 4 PP 2 SUP: whether processes must be running in kernel (supervisor) mode to access the page. VP : VP : VP 2: SUP No Yes No READ Yes Yes Yes WRITE No Yes Yes Address PP 6 PP 9 PP Physical Address Space PP 2 PP 4 PP 6 PP 8 PP 9 PP

21 VM as a Tool for Caching Not all processes valid VA pages fit in physical memory Key idea: treat DRAM-resident pages as a cache of on-disk pages Virtual memory Physical memory VP VP Unallocated Cached Uncached Unallocated Empty Empty PP PP Cached Uncached Empty Cached Uncached Virtual pages (VPs) stored on disk Physical pages (PPs) cached in DRAM

22 VM for Caching General mechanism: On page fault, load corresponding on-disk page to memory, evict a previously memory-resident to disk, set appropriate PTE entry Which entity should be performing this task? User-level process? OS? Hardware? VM Caching policy (more sophisticated than CPU cache) Fully associative: any VP can be mapped to any PP Write-back

23 Page Hit Page hit: reference to VM word that is in physical memory (DRAM cache hit) Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 PP PP 3 VP 6 VP 7

24 Page Fault Page fault: reference to VM word that is not in physical memory (DRAM cache miss) Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Kernel figures out where to find the corresponding on-disk page Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 VP 6 VP 7 PP PP 3

25 Handling Page Fault Page miss causes page fault (an exception) Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 PP PP 3 VP 6 VP 7

26 Handling Page Fault Page miss causes page fault (an exception) Page fault handler selects a victim to be evicted (here VP 4) Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 4 Virtual memory (disk) VP VP 2 VP 3 VP 4 PP PP 3 VP 6 VP 7

27 Handling Page Fault Page miss causes page fault (an exception) Page fault handler selects a victim to be evicted (here VP 4) Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 3 Virtual memory (disk) VP VP 2 VP 3 VP 4 PP PP 3 VP 6 VP 7

28 Handling Page Fault Page miss causes page fault (an exception) Page fault handler selects a victim to be evicted (here VP 4) Offending instruction is restarted: page hit! Virtual address Valid PTE PTE 7 Physical page number or disk address null null Memory resident page table (DRAM) Physical memory (DRAM) VP VP 2 VP 7 VP 3 Virtual memory (disk) VP VP 2 VP 3 VP 4 PP PP 3 VP 6 VP 7

29 Why should VM caching work? Locality! At any point in time, programs tend to access a set of active virtual pages called the working set Programs with better temporal locality will have smaller working sets If (working set size < main memory size) Good performance for one process after compulsory misses If (working set sizes > main memory size ) Thrashing: Performance meltdown where pages are swapped (copied) in and out continuously

30 Conclusions Programmer s view of virtual memory Each process has its own private linear address space Cannot be corrupted by other processes System view of virtual memory Simplifies memory management & protection Uses memory efficiently by caching virtual memory pages