CSC 2405: Computer Systems II

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1 CSC 2405: Computer Systems II Spring 2013 (TR 8:30-9:45 in G86) Mirela Damian Introductions Mirela Damian Room 167A in the Mendel Science Building Teaching Assistant Mohan Kumar Puttasiddaiah Programming assistants Mendel G85, in the left corner of the room 2 1

2 Course Goals: Look under the hood Help you learn what happens under the hood of computer systems Two downward tours: 2400: Language levels tour High-level language (C) assembly language machine language (IA-32) 2405: Service levels tour High-level language (C) standard libraries operating system (Unix) 3 Structure of Course (Part I) Computer Systems Overview Processes Creating and executing processes Then study process cooperation Communication through pipes, sockets Signaling processes Implement a smart Unix shell Midterm 4 2

3 Structure of Course (Part II) Implement a process simulator Threads Sharing global data Synchronization with semaphores Then study multi-threaded servers Memory Management Security Final Exam 5 Course Schedule Very generally Weeks Lectures 1-2 Computer Systems Overview 2-7 Processes Midterm 8-11 Online lectures Project work Spring Break Easter Break Threads, Memory Management, Security See course web site for details 6 3

4 Course Resources NO Required textbooks Lots of online resources Class website 7 Class Work Programming projects Writing your own Unix shell Implementing your own process scheduler Etc. Several smaller assignments One midterm, one final exam Group work Only if specified in the assignment Individual learning assessed through quizzes 8 4

5 Facilities for Programming Unix cluster Machines: csgate, tanner, degas, cezanne, picasso,rodin, cassatt, gauguin, matisse List displayed when logging into csgate Linux machines felix, helix Logging in to the machines remotely SSH available for download from the CSC website 9 Grading and Schedule Assignments & Quizzes (50%) On time (no late submission) First assignment is available now Exams (45%) Class participation (5%) No makeup assignments or exams Lecture attendance is mandatory 10 5

6 Key to Success Start early to allow time for debugging. 11 Computer System Overview A modern computer consists of: One or more processors Main memory Disks Printers Various input/output devices Managing all these components requires a layer of software the operating system University 12 6

7 Computer System Architecture This model provides a good study framework. University 13 Main Memory (Review) The only large storage area that CPU can access directly Hence, any program executing must be in memory Main memory is an array of bytes or words: Memory Addresses Memory University 14 7

8 Memory Hierarchy (Review) A typical memory hierarchy. The numbers are very rough approximations. Cache Principle The more frequently data is accessed, the faster the access should be. University 15 Central Processing Unit (CPU) Runs the loop Fetch-Decode-Execute Fetch Cycle Decode Cycle Execute Cycle START START Fetch Next Decode Execute Execute Execute HALT q Fetch the next instruction from memory q Decode the instruction to figure out what to do q Execute the instruction and store the result University 16 8

9 Fetch-Decode-Execute Where is the next instruction held in the machine? - CPU register called the Program Counter (PC) holds the address of the instruction to be fetched next Fetch cycle - Copy instruction from memory into Register Decode cycle - Decode instruction and fetch operands, if necessary Execute cycle - Execute the instruction - Increment PC by the instruction length after execution (assuming that all instructions are the same length) University 17 Device Controller (Review) Special-purpose processor In charge of a particular device type Has registers (data, control, status) Has local buffer storage I/O is from the device to local buffer of controller CPU moves data from/to memory to/from local buffer I/O devices and CPU can execute concurrently University 18 9

10 I/O Operation Example c = getchar(); Keyboard What happens? Keyboard Controller CPU University 19 Input / Output (I/O) To start an I/O operation, the CPU tells the controller: - The chunk size be transferred (eg, one character) - Goes off to do something else The device controller: - Checks registers to determine what to do (read, write) - Transfers data to/from device from/to local buffer - Informs the CPU when transfer is complete HOW? We will answer this briefly. University 20 10

11 Where Does the OS Fit? System Calls (Traps) Web Browser Music Player Users and User Programs Operating System Interrupts Device Control University 21 Communicating with the OS: Exceptions (Traps and Interrupts) University 11

12 Here is an analogy... Teacher each student is is OS I/O device 23 Inefficient solution: Polling ask OS device 1 ready? device 2 ready?... device n ready? 24 12

13 Turn the situation upside down OS device 1 device 2... device n

14 The analogy continues... Student with a question raises hand Teacher (tries to) answer question is is device ready sends interrupt request OS handles interrupt 27 Types of Exceptions 1. Interrupts 2. Traps 14

15 Exceptions l An exception is a transfer of control to the OS in response to some event (i.e., change in processor state) User Process OS event current! next! exception exception processing by exception handler exception return (optional) Asynchronous Exceptions (Interrupts) l Caused by external events l Examples: I/O interrupts l Hitting CTRL-C at the keyboard l Arrival of a packet from a network l Arrival of a data sector from a disk Hard reset interrupt l Hitting the reset button Soft reset interrupt l Hitting Ctl-Alt-Delete on a PC 15

16 Synchronous Exceptions l Caused by events that occur as a result of executing an instruction: Traps l Intentional l Examples: system calls, breakpoint traps l Returns control to next instruction Faults l Unintentional but possibly recoverable l Examples: page faults (recoverable), protection faults (unrecoverable). l Either re-executes faulting ( current ) instruction or aborts. Aborts l Unintentional and unrecoverable l Examples: parity error, machine check. l Aborts current program Example Synchronous Exceptions l Divide by zero n / 0 l Segmentation fault program tries to access memory it doesn t own l Abnormal termination abort l Overflow usually mult or add l Bad or illegal instruction no such function l Termination request program requests to exit 16

17 Interrupt Vectors n-1 Exception! numbers! interrupt vector... code for exception handler 0 code for exception handler 1 code for exception handler 2... code for exception handler n-1 Each type of event has a unique exception number k Index into jump table (a.k.a., interrupt vector) Jump table entry k points to a function (exception handler). Handler k is called each time exception k occurs. Interrupt Handling l The interrupt architecture Must save the Program Counter (PC) prior to transferring control to the interrupt service routine (interrupt handler) Restore PC upon returning from interrupt l Interrupt handler Save registers that are to be modified onto the stack Service request (eg, copy data from local buffer in memory) Mark the process blocked on I/O as ready to run Restore registers from the stack l Interrupted computation resumes as the point it left off. University 34 17

18 Hardware Interrupts Hardware may trigger interrupts at any time by sending a signal to the CPU by way of system bus (sets CPU interrupt PIN) When the CPU is interrupted - Stops what it is doing - Transfers control to the Interrupt Vector University 35 CPU Check for Interrupts Every Fetch Cycle Decode Cycle Execute Cycle START START Fetch Next Decode Execute Execute Execute HALT??? University 36 18

19 CPU Cycle with Interrupts Interrupts must be handled quickly Fetch Cycle Decode Cycle Execute Cycle Interrupt Check Interrupts disabled START START Fetch Decode Execute Execute Interrupts Enabled Interrupts are a critical part of a computer system - They allow a program to be interrupted, so the computer may deal with an urgent event All modern computer systems are interrupt-driven Check Check for for Interrupt: Interrupt: Process Process Interrupt Interrupt HALT START University 37 Direct Memory Access I/O To start an I/O operation, the CPU tells the DMA controller: - The chunk size to be transferred (eg, 4096 bytes of data) - The memory address where the chunk ought to be stored The DMA controller - Accesses the device via its controller - Transfers the chunk from/to device to/from system MEMORY - Interrupts CPU when transfer is complete Benefits - The CPU is only involved at the start and end of transfer - Interrupts are now less frequent - Hence, CPU can do a lot of work between interrupts University 38 19

20 DMA Example count = read(fd,buffer,nbytes); Memory Disk drive CPU Disk Controller University 39 Software Interrupts Software may trigger interrupts by system calls or illegal operations (such as invalid memory access, divide by zero) System Calls (Traps) Users and User Programs Operating System Hardware University 40 20

21 Trap Walkthrough What happens when a user executes a system call such as read? In Unix, for instance: count = read(fd,buffer,nbytes) which reads up to nbytes from the file described by fd into buffer. The actual number of bytes read is returned Steps: 1. Push third parameter on to the stack. 2. Push second parameter on to the stack. 3. Push first parameter on to the stack. 4. Call the library routine, which involves pushing the return address on to the stack and jumping to the routine. University 41 Trap Walkthrough University 42 21

22 Trap Walkthrough 5. Machine/OS dependent actions. One is to put the system call number for read in a well defined place, e.g., a specific register. This requires assembly language. 6. Trap to the kernel (assembly language). This enters the operating system properly and shifts the computer to privileged mode. 7. Use the system call number to access the interrupt vector pointing to the handler for this trap. 8. The read system call handler processes the request (see below). University 43 Trap Walkthrough 9. Return to user mode (ret) and jumps to the location right after the trap. 10. The library routine returns (count is also returned). 11. The stack is popped (ending the function call read). University 44 22

23 Trap Example l Opening a File User calls open(filename, options) 0804d070 < libc_open>: d082: cd 80 int $0x80 804d084: 5b pop %ebx... l Function open executes system call instruction int OS must find or create file, get it ready for reading or writing Returns integer file descriptor User Process OS int pop exception return Open file Fault Example #1 l Memory Reference User writes to memory location That portion (page) of user s memory is currently on disk int a[1000]; main () { a[500] = 13; } 80483b7: c d d movl $0xd,0x8049d10 Page handler must load page into physical memory Returns to faulting instruction Successful on second try User Process OS event movl return page fault Create page and load into memory 23

24 Fault Example #2 l Memory Reference User writes to memory location Address is not valid int a[1000]; main () { a[5000] = 13; } 80483b7: c e d movl $0xd,0x804e360 Page handler detects invalid address Sends SIGSEG signal to user process User process exits with segmentation fault User Process OS event movl page fault Detect invalid address Signal process The Operating System Resource Principle An Operating Systems is a set of algorithms that allocates resources to processes. Beautification Principle An Operating Systems is a set of algorithms that hide the details of the hardware and provide a more pleasant environment University 48 24

25 Summary Main computer system components: - CPU, Memory, I/O Devices Fetch-Decode-Execute-InterruptCheck cycle I/O device controllers - Special processors - Use local buffers for I/O transfer Software interrupts (system calls, traps) vs. hardware interrupts Interrupt handling steps Interrupt-Driven I/O with DMA University 50 25

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